gem5  v21.1.0.2
gic_v3.hh
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40 
41 #ifndef __DEV_ARM_GICV3_H__
42 #define __DEV_ARM_GICV3_H__
43 
44 #include "arch/arm/interrupts.hh"
45 #include "dev/arm/base_gic.hh"
46 #include "params/Gicv3.hh"
47 
48 namespace gem5
49 {
50 
51 class Gicv3CPUInterface;
52 class Gicv3Distributor;
53 class Gicv3Redistributor;
54 class Gicv3Its;
55 
56 class Gicv3 : public BaseGic
57 {
58  protected:
59  friend class Gicv3CPUInterface;
60  friend class Gicv3Redistributor;
61 
69  uint64_t redistSize;
70 
71  public:
72 
73  // Special interrupt IDs, as per SPEC 2.2.1 section
74  static const int INTID_SECURE = 1020;
75  static const int INTID_NONSECURE = 1021;
76  static const int INTID_SPURIOUS = 1023;
77 
78  // Number of Software Generated Interrupts
79  static const int SGI_MAX = 16;
80  // Number of Private Peripheral Interrupts
81  static const int PPI_MAX = 16;
82 
83  // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
84  enum IntStatus
85  {
90  };
91 
92  // Interrupt groups, as per SPEC section 4.6
93  enum GroupId
94  {
95  G0S,
96  G1S,
98  };
99 
101  {
104  };
105 
106  protected:
107 
108  void clearInt(uint32_t int_id) override;
109  void clearPPInt(uint32_t int_id, uint32_t cpu) override;
110 
111  inline AddrRangeList
112  getAddrRanges() const override
113  {
114  return addrRanges;
115  }
116 
117  void init() override;
118 
119  PARAMS(Gicv3);
120 
121  Tick read(PacketPtr pkt) override;
122  void reset();
123  void sendInt(uint32_t int_id) override;
124  void sendPPInt(uint32_t int_id, uint32_t cpu) override;
125  void serialize(CheckpointOut & cp) const override;
126  void unserialize(CheckpointIn & cp) override;
127  Tick write(PacketPtr pkt) override;
128  bool supportsVersion(GicVersion version) override;
129 
130  public:
131 
132  Gicv3(const Params &p);
133  void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
134  void deassertAll(uint32_t cpu);
135  bool haveAsserted(uint32_t cpu) const;
136 
137  inline Gicv3CPUInterface *
138  getCPUInterface(int cpu_id) const
139  {
140  assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
141  return cpuInterfaces[cpu_id];
142  }
143 
144  inline Gicv3Distributor *
146  {
147  return distributor;
148  }
149 
150  inline Gicv3Redistributor *
151  getRedistributor(ContextID context_id) const
152  {
153  assert(context_id < redistributors.size() and
154  redistributors[context_id]);
155  return redistributors[context_id];
156  }
157 
159  getRedistributorByAffinity(uint32_t affinity) const;
160 
162  getRedistributorByAddr(Addr address) const;
163 
164  void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
165 };
166 
167 } // namespace gem5
168 
169 #endif //__DEV_ARM_GICV3_H__
gem5::Gicv3::addrRanges
AddrRangeList addrRanges
Definition: gic_v3.hh:68
gem5::Gicv3::G1NS
@ G1NS
Definition: gic_v3.hh:97
gem5::Gicv3::GroupId
GroupId
Definition: gic_v3.hh:93
gem5::Gicv3::INTID_NONSECURE
static const int INTID_NONSECURE
Definition: gic_v3.hh:75
gem5::Gicv3::getRedistributor
Gicv3Redistributor * getRedistributor(ContextID context_id) const
Definition: gic_v3.hh:151
gem5::Gicv3::haveAsserted
bool haveAsserted(uint32_t cpu) const
Definition: gic_v3.cc:237
gem5::Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:138
gem5::Gicv3::PARAMS
PARAMS(Gicv3)
gem5::Gicv3::getDistributor
Gicv3Distributor * getDistributor() const
Definition: gic_v3.hh:145
gem5::Gicv3Redistributor
Definition: gic_v3_redistributor.hh:55
gem5::Gicv3::its
Gicv3Its * its
Definition: gic_v3.hh:65
gem5::CheckpointIn
Definition: serialize.hh:68
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::Gicv3::INT_EDGE_TRIGGERED
@ INT_EDGE_TRIGGERED
Definition: gic_v3.hh:103
base_gic.hh
gem5::Gicv3::IntTriggerType
IntTriggerType
Definition: gic_v3.hh:100
gem5::Gicv3::getRedistributorByAddr
Gicv3Redistributor * getRedistributorByAddr(Addr address) const
Definition: gic_v3.cc:256
gem5::Gicv3::deassertAll
void deassertAll(uint32_t cpu)
Definition: gic_v3.cc:230
gem5::Gicv3::PPI_MAX
static const int PPI_MAX
Definition: gic_v3.hh:81
gem5::Gicv3::clearPPInt
void clearPPInt(uint32_t int_id, uint32_t cpu) override
Definition: gic_v3.cc:199
gem5::Gicv3::Gicv3
Gicv3(const Params &p)
Definition: gic_v3.cc:57
std::vector
STL vector class.
Definition: stl.hh:37
gem5::Gicv3::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic_v3.cc:139
gem5::Gicv3::distRange
AddrRange distRange
Definition: gic_v3.hh:66
gem5::Gicv3::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic_v3.cc:102
gem5::Gicv3::redistRange
AddrRange redistRange
Definition: gic_v3.hh:67
gem5::Gicv3::sendPPInt
void sendPPInt(uint32_t int_id, uint32_t cpu) override
Interface call for private peripheral interrupts.
Definition: gic_v3.cc:190
gem5::Gicv3::postInt
void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:208
gem5::Gicv3::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3.cc:288
gem5::Gicv3::reset
void reset()
gem5::Gicv3::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3.cc:272
gem5::BaseGic
Definition: base_gic.hh:72
gem5::Gicv3::INT_LEVEL_SENSITIVE
@ INT_LEVEL_SENSITIVE
Definition: gic_v3.hh:102
interrupts.hh
gem5::Gicv3::INT_PENDING
@ INT_PENDING
Definition: gic_v3.hh:87
gem5::Gicv3::INT_ACTIVE
@ INT_ACTIVE
Definition: gic_v3.hh:88
gem5::Gicv3::cpuInterfaces
std::vector< Gicv3CPUInterface * > cpuInterfaces
Definition: gic_v3.hh:64
gem5::Gicv3::INT_INACTIVE
@ INT_INACTIVE
Definition: gic_v3.hh:86
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Gicv3::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: gic_v3.cc:63
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Gicv3::INTID_SPURIOUS
static const int INTID_SPURIOUS
Definition: gic_v3.hh:76
gem5::Gicv3::distributor
Gicv3Distributor * distributor
Definition: gic_v3.hh:62
gem5::Gicv3::redistributors
std::vector< Gicv3Redistributor * > redistributors
Definition: gic_v3.hh:63
gem5::ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:58
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
gem5::Gicv3::sendInt
void sendInt(uint32_t int_id) override
Post an interrupt from a device that is connected to the GIC.
Definition: gic_v3.cc:176
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:76
gem5::Gicv3::G0S
@ G0S
Definition: gic_v3.hh:95
gem5::Gicv3
Definition: gic_v3.hh:56
gem5::Gicv3Distributor
Definition: gic_v3_distributor.hh:51
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:53
gem5::Gicv3Its
GICv3 ITS module.
Definition: gic_v3_its.hh:83
gem5::Gicv3::IntStatus
IntStatus
Definition: gic_v3.hh:84
gem5::Gicv3::getRedistributorByAffinity
Gicv3Redistributor * getRedistributorByAffinity(uint32_t affinity) const
Definition: gic_v3.cc:244
gem5::Gicv3::SGI_MAX
static const int SGI_MAX
Definition: gic_v3.hh:79
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::Gicv3::INTID_SECURE
static const int INTID_SECURE
Definition: gic_v3.hh:74
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3::G1S
@ G1S
Definition: gic_v3.hh:96
gem5::Gicv3::INT_ACTIVE_PENDING
@ INT_ACTIVE_PENDING
Definition: gic_v3.hh:89
gem5::Gicv3::deassertInt
void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:223
gem5::Gicv3::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: gic_v3.hh:112
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list< AddrRange >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Gicv3::redistSize
uint64_t redistSize
Definition: gic_v3.hh:69
gem5::Gicv3::clearInt
void clearInt(uint32_t int_id) override
Clear an interrupt from a device that is connected to the GIC.
Definition: gic_v3.cc:183
gem5::Gicv3::supportsVersion
bool supportsVersion(GicVersion version) override
Check if version supported.
Definition: gic_v3.cc:216

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