gem5  v22.0.0.2
gic_v3.hh
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40 
41 #ifndef __DEV_ARM_GICV3_H__
42 #define __DEV_ARM_GICV3_H__
43 
44 #include "arch/arm/interrupts.hh"
45 #include "arch/arm/types.hh"
46 #include "dev/arm/base_gic.hh"
47 #include "params/Gicv3.hh"
48 
49 namespace gem5
50 {
51 
52 class Gicv3CPUInterface;
53 class Gicv3Distributor;
54 class Gicv3Redistributor;
55 class Gicv3Its;
56 
58 {
59  public:
60  virtual uint32_t readDistributor(Addr daddr) = 0;
61  virtual uint32_t readRedistributor(const ArmISA::Affinity &aff,
62  Addr daddr) = 0;
63  virtual RegVal readCpu(const ArmISA::Affinity &aff,
64  ArmISA::MiscRegIndex misc_reg) = 0;
65 
66  virtual void writeDistributor(Addr daddr, uint32_t data) = 0;
67  virtual void writeRedistributor(const ArmISA::Affinity &aff,
68  Addr daddr, uint32_t data) = 0;
69  virtual void writeCpu(const ArmISA::Affinity &aff,
70  ArmISA::MiscRegIndex misc_reg, RegVal data) = 0;
71 
72  protected:
73  static void copyDistRegister(Gicv3Registers* from,
75  Addr daddr);
76  static void copyRedistRegister(Gicv3Registers* from,
78  const ArmISA::Affinity &aff, Addr daddr);
79  static void copyCpuRegister(Gicv3Registers* from,
81  const ArmISA::Affinity &aff,
82  ArmISA::MiscRegIndex misc_reg);
84  const ArmISA::Affinity &aff, Addr daddr);
85  static void copyRedistRange(Gicv3Registers* from,
87  const ArmISA::Affinity &aff,
88  Addr daddr, size_t size);
89  static void copyDistRange(Gicv3Registers* from,
91  Addr daddr, size_t size);
92  static void clearDistRange(Gicv3Registers* to, Addr daddr, size_t size);
93 };
94 
95 class Gicv3 : public BaseGic, public Gicv3Registers
96 {
97  protected:
98  friend class Gicv3CPUInterface;
99  friend class Gicv3Redistributor;
100  friend class Gicv3Distributor;
101 
109  uint64_t redistSize;
110 
111  public:
112 
113  // Special interrupt IDs, as per SPEC 2.2.1 section
114  static const int INTID_SECURE = 1020;
115  static const int INTID_NONSECURE = 1021;
116  static const int INTID_SPURIOUS = 1023;
117 
118  // Number of Software Generated Interrupts
119  static const int SGI_MAX = 16;
120  // Number of Private Peripheral Interrupts
121  static const int PPI_MAX = 16;
122 
123  // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
125  {
130  };
131 
132  // Interrupt groups, as per SPEC section 4.6
133  enum GroupId
134  {
138  };
139 
141  {
144  };
145 
146  protected:
147 
148  void clearInt(uint32_t int_id) override;
149  void clearPPInt(uint32_t int_id, uint32_t cpu) override;
150 
151  inline AddrRangeList
152  getAddrRanges() const override
153  {
154  return addrRanges;
155  }
156 
157  void init() override;
158 
159  PARAMS(Gicv3);
160 
161  Tick read(PacketPtr pkt) override;
162  void reset();
163  void sendInt(uint32_t int_id) override;
164  void sendPPInt(uint32_t int_id, uint32_t cpu) override;
165  void serialize(CheckpointOut & cp) const override;
166  void unserialize(CheckpointIn & cp) override;
167  Tick write(PacketPtr pkt) override;
168  bool supportsVersion(GicVersion version) override;
169 
170  public:
171 
172  Gicv3(const Params &p);
173  void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
174  void deassertAll(uint32_t cpu);
175  bool haveAsserted(uint32_t cpu) const;
176 
177  inline Gicv3CPUInterface *
178  getCPUInterface(int cpu_id) const
179  {
180  assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
181  return cpuInterfaces[cpu_id];
182  }
183 
184  inline Gicv3Distributor *
186  {
187  return distributor;
188  }
189 
190  inline Gicv3Redistributor *
191  getRedistributor(ContextID context_id) const
192  {
193  assert(context_id < redistributors.size() and
194  redistributors[context_id]);
195  return redistributors[context_id];
196  }
197 
199  getCPUInterfaceByAffinity(const ArmISA::Affinity &aff) const;
200 
202  getRedistributorByAffinity(const ArmISA::Affinity &aff) const;
203 
205  getRedistributorByAddr(Addr address) const;
206 
207  void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
208 
209  protected: // GIC state transfer
211 
212  public: // Gicv3Registers
213  uint32_t readDistributor(Addr daddr) override;
214  uint32_t readRedistributor(const ArmISA::Affinity &aff,
215  Addr daddr) override;
216  RegVal readCpu(const ArmISA::Affinity &aff,
217  ArmISA::MiscRegIndex misc_reg) override;
218 
219  void writeDistributor(Addr daddr, uint32_t data) override;
220  void writeRedistributor(const ArmISA::Affinity &aff,
221  Addr daddr, uint32_t data) override;
222  void writeCpu(const ArmISA::Affinity &aff,
223  ArmISA::MiscRegIndex misc_reg, RegVal data) override;
224 };
225 
226 } // namespace gem5
227 
228 #endif //__DEV_ARM_GICV3_H__
gem5::Gicv3::addrRanges
AddrRangeList addrRanges
Definition: gic_v3.hh:108
gem5::Gicv3::writeRedistributor
void writeRedistributor(const ArmISA::Affinity &aff, Addr daddr, uint32_t data) override
Definition: gic_v3.cc:380
gem5::Gicv3::G1NS
@ G1NS
Definition: gic_v3.hh:137
gem5::Gicv3::GroupId
GroupId
Definition: gic_v3.hh:133
gem5::Gicv3::INTID_NONSECURE
static const int INTID_NONSECURE
Definition: gic_v3.hh:115
gem5::Gicv3Registers::writeDistributor
virtual void writeDistributor(Addr daddr, uint32_t data)=0
gem5::Gicv3::getRedistributor
Gicv3Redistributor * getRedistributor(ContextID context_id) const
Definition: gic_v3.hh:191
gem5::Gicv3Registers::copyDistRange
static void copyDistRange(Gicv3Registers *from, Gicv3Registers *to, Addr daddr, size_t size)
Definition: gic_v3.cc:115
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::Gicv3Registers
Definition: gic_v3.hh:57
gem5::Gicv3::haveAsserted
bool haveAsserted(uint32_t cpu) const
Definition: gic_v3.cc:311
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:178
gem5::Gicv3::PARAMS
PARAMS(Gicv3)
gem5::Gicv3Registers::copyRedistRange
static void copyRedistRange(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr, size_t size)
Definition: gic_v3.cc:105
gem5::Gicv3::getDistributor
Gicv3Distributor * getDistributor() const
Definition: gic_v3.hh:185
gem5::Gicv3Redistributor
Definition: gic_v3_redistributor.hh:55
gem5::Gicv3::its
Gicv3Its * its
Definition: gic_v3.hh:105
gem5::CheckpointIn
Definition: serialize.hh:68
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::Gicv3::INT_EDGE_TRIGGERED
@ INT_EDGE_TRIGGERED
Definition: gic_v3.hh:143
base_gic.hh
gem5::Gicv3::IntTriggerType
IntTriggerType
Definition: gic_v3.hh:140
gem5::Gicv3::getRedistributorByAddr
Gicv3Redistributor * getRedistributorByAddr(Addr address) const
Definition: gic_v3.cc:336
gem5::Gicv3::deassertAll
void deassertAll(uint32_t cpu)
Definition: gic_v3.cc:304
gem5::Gicv3::PPI_MAX
static const int PPI_MAX
Definition: gic_v3.hh:121
gem5::Gicv3::clearPPInt
void clearPPInt(uint32_t int_id, uint32_t cpu) override
Definition: gic_v3.cc:273
gem5::Gicv3::Gicv3
Gicv3(const Params &p)
Definition: gic_v3.cc:131
std::vector
STL vector class.
Definition: stl.hh:37
gem5::Gicv3::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic_v3.cc:213
gem5::Gicv3::distRange
AddrRange distRange
Definition: gic_v3.hh:106
gem5::Gicv3::getRedistributorByAffinity
Gicv3Redistributor * getRedistributorByAffinity(const ArmISA::Affinity &aff) const
Definition: gic_v3.cc:324
gem5::Gicv3Registers::readRedistributor
virtual uint32_t readRedistributor(const ArmISA::Affinity &aff, Addr daddr)=0
gem5::Gicv3::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic_v3.cc:176
types.hh
gem5::Gicv3Registers::copyRedistRegister
static void copyRedistRegister(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr)
Definition: gic_v3.cc:68
gem5::Gicv3::redistRange
AddrRange redistRange
Definition: gic_v3.hh:107
gem5::Gicv3::writeCpu
void writeCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg, RegVal data) override
Definition: gic_v3.cc:388
gem5::Gicv3Registers::writeCpu
virtual void writeCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg, RegVal data)=0
gem5::Gicv3::sendPPInt
void sendPPInt(uint32_t int_id, uint32_t cpu) override
Interface call for private peripheral interrupts.
Definition: gic_v3.cc:264
gem5::Gicv3::readDistributor
uint32_t readDistributor(Addr daddr) override
Definition: gic_v3.cc:352
gem5::Gicv3::postInt
void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:282
gem5::Gicv3::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3.cc:425
gem5::Gicv3::reset
void reset()
gem5::PowerISA::to
Bitfield< 25, 21 > to
Definition: types.hh:96
gem5::Gicv3::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3.cc:409
gem5::BaseGic
Definition: base_gic.hh:72
gem5::Gicv3::INT_LEVEL_SENSITIVE
@ INT_LEVEL_SENSITIVE
Definition: gic_v3.hh:142
interrupts.hh
gem5::Gicv3::INT_PENDING
@ INT_PENDING
Definition: gic_v3.hh:127
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Gicv3::INT_ACTIVE
@ INT_ACTIVE
Definition: gic_v3.hh:128
gem5::Gicv3::cpuInterfaces
std::vector< Gicv3CPUInterface * > cpuInterfaces
Definition: gic_v3.hh:104
gem5::Gicv3::INT_INACTIVE
@ INT_INACTIVE
Definition: gic_v3.hh:126
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Gicv3::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: gic_v3.cc:137
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Gicv3Registers::writeRedistributor
virtual void writeRedistributor(const ArmISA::Affinity &aff, Addr daddr, uint32_t data)=0
gem5::Gicv3::INTID_SPURIOUS
static const int INTID_SPURIOUS
Definition: gic_v3.hh:116
gem5::Gicv3::distributor
Gicv3Distributor * distributor
Definition: gic_v3.hh:102
gem5::Gicv3Registers::readCpu
virtual RegVal readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg)=0
gem5::Gicv3::redistributors
std::vector< Gicv3Redistributor * > redistributors
Definition: gic_v3.hh:103
gem5::ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:59
gem5::Gicv3Registers::copyCpuRegister
static void copyCpuRegister(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg)
Definition: gic_v3.cc:82
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
gem5::Gicv3::sendInt
void sendInt(uint32_t int_id) override
Post an interrupt from a device that is connected to the GIC.
Definition: gic_v3.cc:250
gem5::Gicv3::readCpu
RegVal readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg) override
Definition: gic_v3.cc:366
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:76
gem5::Gicv3::getCPUInterfaceByAffinity
Gicv3CPUInterface * getCPUInterfaceByAffinity(const ArmISA::Affinity &aff) const
Definition: gic_v3.cc:318
gem5::Gicv3::G0S
@ G0S
Definition: gic_v3.hh:135
gem5::Gicv3
Definition: gic_v3.hh:95
gem5::Gicv3Distributor
Definition: gic_v3_distributor.hh:51
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:58
gem5::Gicv3Its
GICv3 ITS module.
Definition: gic_v3_its.hh:83
gem5::Gicv3::IntStatus
IntStatus
Definition: gic_v3.hh:124
gem5::Gicv3::SGI_MAX
static const int SGI_MAX
Definition: gic_v3.hh:119
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::Gicv3::copyGicState
void copyGicState(Gicv3Registers *from, Gicv3Registers *to)
Definition: gic_v3.cc:397
gem5::Gicv3Registers::copyDistRegister
static void copyDistRegister(Gicv3Registers *from, Gicv3Registers *to, Addr daddr)
Definition: gic_v3.cc:58
gem5::Gicv3::INTID_SECURE
static const int INTID_SECURE
Definition: gic_v3.hh:114
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3::writeDistributor
void writeDistributor(Addr daddr, uint32_t data) override
Definition: gic_v3.cc:374
gem5::Gicv3::G1S
@ G1S
Definition: gic_v3.hh:136
gem5::Gicv3::readRedistributor
uint32_t readRedistributor(const ArmISA::Affinity &aff, Addr daddr) override
Definition: gic_v3.cc:358
gem5::Gicv3::INT_ACTIVE_PENDING
@ INT_ACTIVE_PENDING
Definition: gic_v3.hh:129
gem5::Gicv3::deassertInt
void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:297
gem5::Gicv3::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: gic_v3.hh:152
gem5::Gicv3Registers::clearRedistRegister
static void clearRedistRegister(Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr)
Definition: gic_v3.cc:98
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
std::list< AddrRange >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gicv3::redistSize
uint64_t redistSize
Definition: gic_v3.hh:109
gem5::Gicv3Registers::readDistributor
virtual uint32_t readDistributor(Addr daddr)=0
gem5::Gicv3::clearInt
void clearInt(uint32_t int_id) override
Clear an interrupt from a device that is connected to the GIC.
Definition: gic_v3.cc:257
gem5::Gicv3::supportsVersion
bool supportsVersion(GicVersion version) override
Check if version supported.
Definition: gic_v3.cc:290
gem5::Gicv3Registers::clearDistRange
static void clearDistRange(Gicv3Registers *to, Addr daddr, size_t size)
Definition: gic_v3.cc:124

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