gem5  v21.1.0.2
gic.cc
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37 
38 #include "arch/arm/kvm/gic.hh"
39 
40 #include <linux/kvm.h>
41 
42 #include "arch/arm/kvm/base_cpu.hh"
43 #include "debug/GIC.hh"
44 #include "debug/Interrupt.hh"
45 #include "params/MuxingKvmGic.hh"
46 
47 namespace gem5
48 {
49 
50 KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
51  unsigned it_lines)
52  : cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
53  distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE)),
54  vm(_vm),
55  kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2))
56 {
57  // Tell the VM that we will emulate the GIC in the kernel. This
58  // disables IRQ and FIQ handling in the KVM CPU model.
60 
61  kdev.setAttr<uint64_t>(
62  KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
63  kdev.setAttr<uint64_t>(
64  KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr);
65 
66  kdev.setAttr<uint32_t>(KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, it_lines);
67 }
68 
70 {
71 }
72 
73 void
75 {
76  setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true);
77 }
78 
79 void
81 {
82  setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false);
83 }
84 
85 void
86 KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi)
87 {
88  setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
89 }
90 
91 void
92 KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi)
93 {
94  setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
95 }
96 
97 void
98 KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
99  bool high)
100 {
101  assert(type <= KVM_ARM_IRQ_TYPE_MASK);
102  assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
103  assert(irq <= KVM_ARM_IRQ_NUM_MASK);
104  const uint32_t line(
105  (type << KVM_ARM_IRQ_TYPE_SHIFT) |
106  (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
107  (irq << KVM_ARM_IRQ_NUM_SHIFT));
108 
109  vm.setIRQLine(line, high);
110 }
111 
112 uint32_t
113 KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
114 {
115  uint64_t reg;
116 
117  assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
118  const uint64_t attr(
119  ((uint64_t)vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
120  (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
121 
122  kdev.getAttrPtr(group, attr, &reg);
123  return (uint32_t) reg;
124 }
125 
126 void
127 KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
128  unsigned value)
129 {
130  uint64_t reg = value;
131 
132  assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
133  const uint64_t attr(
134  ((uint64_t)vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
135  (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
136 
137  kdev.setAttrPtr(group, attr, &reg);
138 }
139 
140 uint32_t
142 {
143  auto vcpu = vm.contextIdToVCpuId(ctx);
144  return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
145 }
146 
147 uint32_t
149 {
150  auto vcpu = vm.contextIdToVCpuId(ctx);
151  return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
152 }
153 
154 void
156 {
157  auto vcpu = vm.contextIdToVCpuId(ctx);
158  setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
159 }
160 
161 void
163 {
164  auto vcpu = vm.contextIdToVCpuId(ctx);
165  setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
166 }
167 
168 
169 
170 MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams &p)
171  : GicV2(p),
172  system(*p.system),
173  kernelGic(nullptr),
174  usingKvm(false)
175 {
176  auto vm = system.getKvmVM();
177  if (vm && !p.simulate_gic) {
178  kernelGic = new KvmKernelGicV2(*vm, p.cpu_addr, p.dist_addr,
179  p.it_lines);
180  }
181 }
182 
184 {
185 }
186 
187 void
189 {
190  GicV2::startup();
191  usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
192  if (usingKvm)
193  fromGicV2ToKvm();
194 }
195 
198 {
199  if (usingKvm)
200  fromKvmToGicV2();
201  return GicV2::drain();
202 }
203 
204 void
206 {
208  bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
209  if (use_kvm != usingKvm) {
210  // Should only occur due to CPU switches
211  if (use_kvm) // from simulation to KVM emulation
212  fromGicV2ToKvm();
213  // otherwise, drain() already sync'd the state back to the GicV2
214 
215  usingKvm = use_kvm;
216  }
217 }
218 
219 Tick
221 {
222  if (!usingKvm)
223  return GicV2::read(pkt);
224 
225  panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
226 }
227 
228 Tick
230 {
231  if (!usingKvm)
232  return GicV2::write(pkt);
233 
234  panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
235 }
236 
237 void
239 {
240  if (!usingKvm)
241  return GicV2::sendInt(num);
242 
243  DPRINTF(Interrupt, "Set SPI %d\n", num);
244  kernelGic->setSPI(num);
245 }
246 
247 void
249 {
250  if (!usingKvm)
251  return GicV2::clearInt(num);
252 
253  DPRINTF(Interrupt, "Clear SPI %d\n", num);
254  kernelGic->clearSPI(num);
255 }
256 
257 void
258 MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
259 {
260  if (!usingKvm)
261  return GicV2::sendPPInt(num, cpu);
262  DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
263  kernelGic->setPPI(cpu, num);
264 }
265 
266 void
267 MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
268 {
269  if (!usingKvm)
270  return GicV2::clearPPInt(num, cpu);
271 
272  DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
273  kernelGic->clearPPI(cpu, num);
274 }
275 
276 void
278 {
279  // During Kvm->GicV2 state transfer, writes to the GicV2 will call
280  // updateIntState() which can post an interrupt. Since we're only
281  // using the GicV2 model for holding state in this circumstance, we
282  // short-circuit this behavior, as the GicV2 is not actually active.
283  if (!usingKvm)
284  return GicV2::updateIntState(hint);
285 }
286 
287 void
289  ContextID ctx, Addr daddr)
290 {
291  auto val = from->readDistributor(ctx, daddr);
292  DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
293  to->writeDistributor(ctx, daddr, val);
294 }
295 
296 void
298  ContextID ctx, Addr daddr)
299 {
300  auto val = from->readCpu(ctx, daddr);
301  DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
302  to->writeCpu(ctx, daddr, val);
303 }
304 
305 void
307  Addr daddr, size_t size)
308 {
309  for (int ctx = 0; ctx < system.threads.size(); ++ctx)
310  for (auto a = daddr; a < daddr + size; a += 4)
311  copyDistRegister(from, to, ctx, a);
312 }
313 
314 void
316  Addr daddr, size_t size)
317 {
318  for (int ctx = 0; ctx < system.threads.size(); ++ctx)
319  for (auto a = daddr; a < daddr + size; a += 4)
320  to->writeDistributor(ctx, a, 0xFFFFFFFF);
321 }
322 
323 void
325  Addr daddr, size_t size)
326 {
327  for (auto a = daddr; a < daddr + size; a += 4)
328  copyDistRegister(from, to, 0, a);
329 }
330 
331 void
333  Addr daddr, size_t size)
334 {
335  for (auto a = daddr; a < daddr + size; a += 4)
336  to->writeDistributor(0, a, 0xFFFFFFFF);
337 }
338 
339 void
341 {
342  Addr set, clear;
343  size_t size;
344 
346  // Copy CPU Interface Control Register (CTLR),
347  // Interrupt Priority Mask Register (PMR), and
348  // Binary Point Register (BPR)
349  for (int ctx = 0; ctx < system.threads.size(); ++ctx) {
350  copyCpuRegister(from, to, ctx, GICC_CTLR);
351  copyCpuRegister(from, to, ctx, GICC_PMR);
352  copyCpuRegister(from, to, ctx, GICC_BPR);
353  }
354 
355 
357  // Copy Distributor Control Register (CTLR)
358  copyDistRegister(from, to, 0, GICD_CTLR);
359 
360  // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
362  clear = GicV2::GICD_ICENABLER.start();
363  size = GicV2::itLines / 8;
364  clearBankedDistRange(to, clear, 4);
365  copyBankedDistRange(from, to, set, 4);
366 
367  set += 4, clear += 4, size -= 4;
368  clearDistRange(to, clear, size);
369  copyDistRange(from, to, set, size);
370 
371  // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
372  set = GicV2::GICD_ISPENDR.start();
373  clear = GicV2::GICD_ICPENDR.start();
374  size = GicV2::itLines / 8;
375  clearBankedDistRange(to, clear, 4);
376  copyBankedDistRange(from, to, set, 4);
377 
378  set += 4, clear += 4, size -= 4;
379  clearDistRange(to, clear, size);
380  copyDistRange(from, to, set, size);
381 
382  // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
384  clear = GicV2::GICD_ICACTIVER.start();
385  size = GicV2::itLines / 8;
386  clearBankedDistRange(to, clear, 4);
387  copyBankedDistRange(from, to, set, 4);
388 
389  set += 4, clear += 4, size -= 4;
390  clearDistRange(to, clear, size);
391  copyDistRange(from, to, set, size);
392 
393  // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
395  copyBankedDistRange(from, to, set, 32);
396 
397  set += 32;
398  size = GicV2::itLines - 32;
399  copyDistRange(from, to, set, size);
400 
401  // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
402  set = GicV2::GICD_ITARGETSR.start() + 32;
403  size = GicV2::itLines - 32;
404  copyDistRange(from, to, set, size);
405 
406  // Copy interrupt configuration registers (ICFGRn)
407  set = GicV2::GICD_ICFGR.start();
408  size = GicV2::itLines / 4;
409  copyDistRange(from, to, set, size);
410 }
411 
412 void
414 {
415  copyGicState(static_cast<GicV2*>(this), kernelGic);
416 }
417 
418 void
420 {
421  copyGicState(kernelGic, static_cast<GicV2*>(this));
422 
423  // the values read for the Interrupt Priority Mask Register (PMR)
424  // have been shifted by three bits due to its having been emulated by
425  // a VGIC with only 5 PMR bits in its VMCR register. Presently the
426  // Linux kernel does not repair this inaccuracy, so we correct it here.
427  for (int cpu = 0; cpu < system.threads.size(); ++cpu) {
428  cpuPriority[cpu] <<= 3;
429  assert((cpuPriority[cpu] & ~0xff) == 0);
430  }
431 }
432 
433 } // namespace gem5
gem5::GicV2::clearInt
void clearInt(ContextID ctx, uint32_t int_num)
Clears a cpu IRQ or FIQ signal.
Definition: gic_v2.cc:923
gem5::MuxingKvmGic::system
System & system
System this interrupt controller belongs to.
Definition: gic.hh:197
gem5::MuxingKvmGic::fromGicV2ToKvm
void fromGicV2ToKvm()
Multiplexing implementation.
Definition: gic.cc:413
gem5::AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:317
gem5::GicV2::GICD_IPRIORITYR
static const AddrRange GICD_IPRIORITYR
Definition: gic_v2.hh:91
gem5::System::Threads::size
int size() const
Definition: system.hh:216
gem5::MuxingKvmGic::MuxingKvmGic
MuxingKvmGic(const MuxingKvmGicParams &p)
Definition: gic.cc:170
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::KvmKernelGicV2::clearSPI
void clearSPI(unsigned spi)
Clear a shared peripheral interrupt.
Definition: gic.cc:80
gem5::GicV2::GICD_CTLR
@ GICD_CTLR
Definition: gic_v2.hh:68
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:661
gem5::KvmKernelGicV2::setPPI
void setPPI(unsigned vcpu, unsigned ppi)
Raise a private peripheral interrupt.
Definition: gic.cc:86
gem5::GicV2::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: gic_v2.cc:991
gem5::GicV2::GICC_CTLR
@ GICC_CTLR
Definition: gic_v2.hh:98
gem5::ArmISA::attr
attr
Definition: misc_types.hh:655
gem5::GicV2::GICD_ISPENDR
static const AddrRange GICD_ISPENDR
Definition: gic_v2.hh:87
gem5::MuxingKvmGic::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: gic.cc:205
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::MuxingKvmGic::clearPPInt
void clearPPInt(uint32_t num, uint32_t cpu) override
Definition: gic.cc:267
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
base_cpu.hh
gem5::GicV2::GICD_ICPENDR
static const AddrRange GICD_ICPENDR
Definition: gic_v2.hh:88
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::BaseGicRegisters::readCpu
virtual uint32_t readCpu(ContextID ctx, Addr daddr)=0
gem5::KvmKernelGicV2::getGicReg
uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset)
Get value of GIC register "from" a cpu.
Definition: gic.cc:113
gem5::KvmDevice::setAttr
void setAttr(uint32_t group, uint64_t attr, const T &data) const
Get the value of an attribute.
Definition: device.hh:95
gem5::BaseGicRegisters
Definition: base_gic.hh:127
gem5::KvmVM
KVM VM container.
Definition: vm.hh:297
gem5::MuxingKvmGic::sendPPInt
void sendPPInt(uint32_t num, uint32_t cpu) override
Interface call for private peripheral interrupts.
Definition: gic.cc:258
gem5::ArmISA::irq
Bitfield< 1 > irq
Definition: misc_types.hh:330
gem5::KvmKernelGicV2::setIntState
void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high)
Update the kernel's VGIC interrupt state.
Definition: gic.cc:98
gem5::PowerISA::to
Bitfield< 25, 21 > to
Definition: types.hh:96
gem5::MuxingKvmGic::~MuxingKvmGic
~MuxingKvmGic()
Definition: gic.cc:183
gem5::GicV2::sendInt
void sendInt(uint32_t number) override
Post an interrupt from a device that is connected to the GIC.
Definition: gic_v2.cc:866
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::KvmDevice::setAttrPtr
void setAttrPtr(uint32_t group, uint64_t attr, const void *data) const
Definition: device.cc:84
gem5::high
high
Definition: intmath.hh:176
gem5::KvmKernelGicV2::kdev
KvmDevice kdev
Kernel interface to the GIC.
Definition: gic.hh:165
gem5::MuxingKvmGic::clearDistRange
void clearDistRange(BaseGicRegisters *to, Addr daddr, size_t size)
Definition: gic.cc:332
gem5::System::getKvmVM
KvmVM * getKvmVM()
Get a pointer to the Kernel Virtual Machine (KVM) SimObject, if present.
Definition: system.hh:342
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gic.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::GicV2
Definition: gic_v2.hh:62
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::GicV2::GICD_ISENABLER
static const AddrRange GICD_ISENABLER
Definition: gic_v2.hh:85
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::GicV2::GICC_PMR
@ GICC_PMR
Definition: gic_v2.hh:99
gem5::KvmKernelGicV2::writeDistributor
void writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic.cc:155
gem5::KvmKernelGicV2::setSPI
void setSPI(unsigned spi)
Raise a shared peripheral interrupt.
Definition: gic.cc:74
gem5::GicV2::updateIntState
virtual void updateIntState(int hint)
See if some processor interrupt flags need to be enabled/disabled.
Definition: gic_v2.cc:739
gem5::GicV2::write
Tick write(PacketPtr pkt) override
A PIO read to the device, immediately split up into writeDistributor() or writeCpu()
Definition: gic_v2.cc:129
gem5::KvmKernelGicV2::~KvmKernelGicV2
virtual ~KvmKernelGicV2()
Definition: gic.cc:69
gem5::KvmVM::setIRQLine
void setIRQLine(uint32_t irq, bool high)
Set the status of an IRQ line using KVM_IRQ_LINE.
Definition: vm.cc:514
gem5::MuxingKvmGic::clearInt
void clearInt(uint32_t num) override
Clear an interrupt from a device that is connected to the GIC.
Definition: gic.cc:248
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::KvmVM::enableKernelIRQChip
void enableKernelIRQChip()
Tell the VM and VCPUs to use an in-kernel IRQ chip for interrupt delivery.
Definition: vm.hh:368
gem5::GicV2::GICD_ICFGR
static const AddrRange GICD_ICFGR
Definition: gic_v2.hh:93
gem5::GicV2::GICD_ICENABLER
static const AddrRange GICD_ICENABLER
Definition: gic_v2.hh:86
gem5::GicV2::GICD_ISACTIVER
static const AddrRange GICD_ISACTIVER
Definition: gic_v2.hh:89
gem5::GicV2::read
Tick read(PacketPtr pkt) override
A PIO read to the device, immediately split up into readDistributor() or readCpu()
Definition: gic_v2.cc:115
gem5::KvmKernelGicV2::setGicReg
void setGicReg(unsigned group, unsigned vcpu, unsigned offset, unsigned value)
Set value of GIC register "from" a cpu.
Definition: gic.cc:127
gem5::GicV2::GICC_BPR
@ GICC_BPR
Definition: gic_v2.hh:100
gem5::KvmKernelGicV2::readDistributor
uint32_t readDistributor(ContextID ctx, Addr daddr) override
BaseGicRegisters interface.
Definition: gic.cc:141
gem5::GicV2::cpuPriority
uint8_t cpuPriority[CPU_MAX]
CPU priority.
Definition: gic_v2.hh:416
gem5::KvmVM::contextIdToVCpuId
long contextIdToVCpuId(ContextID ctx) const
Get the VCPUID for a given context.
Definition: vm.cc:552
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MuxingKvmGic::sendInt
void sendInt(uint32_t num) override
Post an interrupt from a device that is connected to the GIC.
Definition: gic.cc:238
gem5::BaseGicRegisters::readDistributor
virtual uint32_t readDistributor(ContextID ctx, Addr daddr)=0
gem5::ArmISA::vm
Bitfield< 0 > vm
Definition: misc_types.hh:284
gem5::MuxingKvmGic::copyDistRegister
void copyDistRegister(BaseGicRegisters *from, BaseGicRegisters *to, ContextID ctx, Addr daddr)
Definition: gic.cc:288
gem5::MuxingKvmGic::updateIntState
void updateIntState(int hint) override
See if some processor interrupt flags need to be enabled/disabled.
Definition: gic.cc:277
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::GicV2::clearPPInt
void clearPPInt(uint32_t num, uint32_t cpu) override
Definition: gic_v2.cc:908
gem5::KvmKernelGicV2::readCpu
uint32_t readCpu(ContextID ctx, Addr daddr) override
Definition: gic.cc:148
gem5::GicV2::itLines
uint32_t itLines
Number of itLines enabled.
Definition: gic_v2.hh:180
gem5::GicV2::GICD_ITARGETSR
static const AddrRange GICD_ITARGETSR
Definition: gic_v2.hh:92
gem5::MuxingKvmGic::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic.cc:220
gem5::MuxingKvmGic::kernelGic
KvmKernelGicV2 * kernelGic
Kernel GIC device.
Definition: gic.hh:200
gem5::KvmKernelGicV2::vm
KvmVM & vm
KVM VM in the parent system.
Definition: gic.hh:162
gem5::MuxingKvmGic::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic.cc:229
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::MuxingKvmGic::fromKvmToGicV2
void fromKvmToGicV2()
Definition: gic.cc:419
gem5::SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:99
gem5::GicV2::GICD_ICACTIVER
static const AddrRange GICD_ICACTIVER
Definition: gic_v2.hh:90
gem5::MuxingKvmGic::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: gic.cc:197
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::System::validKvmEnvironment
bool validKvmEnvironment() const
Verify gem5 configuration will support KVM emulation.
Definition: system.cc:337
gem5::MuxingKvmGic::usingKvm
bool usingKvm
Definition: gic.hh:203
gem5::KvmKernelGicV2::KvmKernelGicV2
KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr, unsigned it_lines)
Instantiate a KVM in-kernel GIC model.
Definition: gic.cc:50
gem5::KvmKernelGicV2::clearPPI
void clearPPI(unsigned vcpu, unsigned ppi)
Clear a private peripheral interrupt.
Definition: gic.cc:92
gem5::MuxingKvmGic::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: gic.cc:188
gem5::KvmDevice::getAttrPtr
void getAttrPtr(uint32_t group, uint64_t attr, void *data) const
Definition: device.cc:63
gem5::MuxingKvmGic::copyCpuRegister
void copyCpuRegister(BaseGicRegisters *from, BaseGicRegisters *to, ContextID ctx, Addr daddr)
Definition: gic.cc:297
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::KvmKernelGicV2::writeCpu
void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic.cc:162
gem5::GicV2::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: gic_v2.cc:980
gem5::MuxingKvmGic::copyBankedDistRange
void copyBankedDistRange(BaseGicRegisters *from, BaseGicRegisters *to, Addr daddr, size_t size)
Definition: gic.cc:306
gem5::MuxingKvmGic::clearBankedDistRange
void clearBankedDistRange(BaseGicRegisters *to, Addr daddr, size_t size)
Definition: gic.cc:315
gem5::GicV2::sendPPInt
void sendPPInt(uint32_t num, uint32_t cpu) override
Interface call for private peripheral interrupts.
Definition: gic_v2.cc:880
gem5::ArmISA::Interrupt
Definition: faults.hh:557
gem5::MuxingKvmGic::copyDistRange
void copyDistRange(BaseGicRegisters *from, BaseGicRegisters *to, Addr daddr, size_t size)
Definition: gic.cc:324
gem5::KvmKernelGicV2
KVM in-kernel GIC abstraction.
Definition: gic.hh:57
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::MuxingKvmGic::copyGicState
void copyGicState(BaseGicRegisters *from, BaseGicRegisters *to)
Definition: gic.cc:340

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