gem5  v22.0.0.2
gic.cc
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37 
38 #include "arch/arm/kvm/gic.hh"
39 
40 #include <linux/kvm.h>
41 
42 #include "arch/arm/kvm/base_cpu.hh"
43 #include "arch/arm/regs/misc.hh"
44 #include "debug/GIC.hh"
45 #include "debug/Interrupt.hh"
46 #include "params/MuxingKvmGicV2.hh"
47 
48 namespace gem5
49 {
50 
51 KvmKernelGic::KvmKernelGic(KvmVM &_vm, uint32_t dev, unsigned it_lines)
52  : vm(_vm),
53  kdev(vm.createDevice(dev))
54 {
55  // Tell the VM that we will emulate the GIC in the kernel. This
56  // disables IRQ and FIQ handling in the KVM CPU model.
58 
59  kdev.setAttr<uint32_t>(KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, it_lines);
60 }
61 
63 {
64 }
65 
66 void
67 KvmKernelGic::setSPI(unsigned spi)
68 {
69  setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true);
70 }
71 
72 void
74 {
75  setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false);
76 }
77 
78 void
79 KvmKernelGic::setPPI(unsigned vcpu, unsigned ppi)
80 {
81  setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
82 }
83 
84 void
85 KvmKernelGic::clearPPI(unsigned vcpu, unsigned ppi)
86 {
87  setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
88 }
89 
90 void
91 KvmKernelGic::setIntState(unsigned type, unsigned vcpu, unsigned irq,
92  bool high)
93 {
94  const unsigned vcpu_index = vcpu & 0xff;
95  const unsigned vcpu2_index = (vcpu >> 8) & 0xff;
96 
97  static const bool vcpu2_enabled = vm.kvm->capIRQLineLayout2();
98  uint32_t kvm_vcpu = (vcpu_index << KVM_ARM_IRQ_VCPU_SHIFT);
99  if (vcpu2_enabled)
100  kvm_vcpu |= vcpu2_index << KVM_ARM_IRQ_VCPU2_SHIFT;
101 
102  panic_if((!vcpu2_enabled && vcpu2_index) || kvm_vcpu > 0xffff,
103  "VCPU out of range");
104 
105  assert(type <= KVM_ARM_IRQ_TYPE_MASK);
106  assert(irq <= KVM_ARM_IRQ_NUM_MASK);
107  const uint32_t line(
108  kvm_vcpu |
109  (type << KVM_ARM_IRQ_TYPE_SHIFT) |
110  (irq << KVM_ARM_IRQ_NUM_SHIFT));
111 
112  vm.setIRQLine(line, high);
113 }
114 
116  const MuxingKvmGicV2Params &p)
117  : KvmKernelGic(_vm, KVM_DEV_TYPE_ARM_VGIC_V2, p.it_lines),
118  cpuRange(RangeSize(p.cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
119  distRange(RangeSize(p.dist_addr, KVM_VGIC_V2_DIST_SIZE))
120 {
121  kdev.setAttr<uint64_t>(
122  KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, p.dist_addr);
123  kdev.setAttr<uint64_t>(
124  KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, p.cpu_addr);
125 }
126 
127 uint32_t
128 KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
129 {
130  uint64_t reg;
131 
132  assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
133  const uint64_t attr(
134  ((uint64_t)vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
135  (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
136 
137  kdev.getAttrPtr(group, attr, &reg);
138  return (uint32_t) reg;
139 }
140 
141 void
142 KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
143  unsigned value)
144 {
145  uint64_t reg = value;
146 
147  assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
148  const uint64_t attr(
149  ((uint64_t)vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
150  (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
151 
152  kdev.setAttrPtr(group, attr, &reg);
153 }
154 
155 uint32_t
157 {
158  auto vcpu = vm.contextIdToVCpuId(ctx);
159  return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
160 }
161 
162 uint32_t
164 {
165  auto vcpu = vm.contextIdToVCpuId(ctx);
166  return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
167 }
168 
169 void
171 {
172  auto vcpu = vm.contextIdToVCpuId(ctx);
173  setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
174 }
175 
176 void
178 {
179  auto vcpu = vm.contextIdToVCpuId(ctx);
180  setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
181 }
182 
183 #ifndef SZ_64K
184 #define SZ_64K 0x00000040
185 #endif
186 
188  const MuxingKvmGicV3Params &p)
189  : KvmKernelGic(_vm, KVM_DEV_TYPE_ARM_VGIC_V3, p.it_lines),
190  redistRange(RangeSize(p.redist_addr, KVM_VGIC_V3_REDIST_SIZE)),
191  distRange(RangeSize(p.dist_addr, KVM_VGIC_V3_DIST_SIZE))
192 {
193  kdev.setAttr<uint64_t>(
194  KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_DIST, p.dist_addr);
195  kdev.setAttr<uint64_t>(
196  KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_REDIST, p.redist_addr);
197 }
198 
199 void
201 {
202  kdev.setAttr<uint64_t>(
203  KVM_DEV_ARM_VGIC_GRP_CTRL, KVM_DEV_ARM_VGIC_CTRL_INIT, 0);
204 }
205 
206 template <typename Ret>
207 Ret
208 KvmKernelGicV3::getGicReg(unsigned group, unsigned mpidr, unsigned offset)
209 {
210  Ret reg;
211 
212  assert(mpidr <= KVM_DEV_ARM_VGIC_V3_MPIDR_MASK);
213  const uint64_t attr(
214  ((uint64_t)mpidr << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) |
215  (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
216 
217  kdev.getAttrPtr(group, attr, &reg);
218  return reg;
219 }
220 
221 template <typename Arg>
222 void
223 KvmKernelGicV3::setGicReg(unsigned group, unsigned mpidr, unsigned offset,
224  Arg value)
225 {
226  Arg reg = value;
227 
228  assert(mpidr <= KVM_DEV_ARM_VGIC_V3_MPIDR_MASK);
229  const uint64_t attr(
230  ((uint64_t)mpidr << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) |
231  (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
232 
233  kdev.setAttrPtr(group, attr, &reg);
234 }
235 
236 uint32_t
238 {
239  return getGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 0, daddr);
240 }
241 
242 uint32_t
243 KvmKernelGicV3::readRedistributor(const ArmISA::Affinity &aff, Addr daddr)
244 {
245  return getGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, aff, daddr);
246 }
247 
248 RegVal
249 KvmKernelGicV3::readCpu(const ArmISA::Affinity &aff,
250  ArmISA::MiscRegIndex misc_reg)
251 {
252  auto sys_reg = ArmISA::encodeAArch64SysReg(misc_reg).packed();
253  return getGicReg<RegVal>(KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, aff, sys_reg);
254 }
255 
256 void
258 {
259  setGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 0, daddr, data);
260 }
261 
262 void
263 KvmKernelGicV3::writeRedistributor(const ArmISA::Affinity &aff, Addr daddr,
264  uint32_t data)
265 {
266  setGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, aff, daddr, data);
267 }
268 
269 void
270 KvmKernelGicV3::writeCpu(const ArmISA::Affinity &aff,
271  ArmISA::MiscRegIndex misc_reg,
272  RegVal data)
273 {
274  auto sys_reg = ArmISA::encodeAArch64SysReg(misc_reg).packed();
275  setGicReg<RegVal>(KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, aff, sys_reg, data);
276 }
277 
278 template <class Types>
280  : SimGic(p),
281  system(*p.system),
282  kernelGic(nullptr),
283  usingKvm(false)
284 {
285  auto vm = system.getKvmVM();
286  if (vm && !p.simulate_gic) {
287  kernelGic = new KvmGic(*vm, p);
288  }
289 }
290 
291 template <class Types>
292 void
294 {
295  SimGic::startup();
296 
297  if (kernelGic) {
298  kernelGic->init();
299 
300  KvmVM *vm = system.getKvmVM();
301  if (vm && vm->validEnvironment()) {
302  usingKvm = true;
303  fromGicToKvm();
304  }
305  }
306 }
307 
308 template <class Types>
311 {
312  if (usingKvm)
313  fromKvmToGic();
314  return SimGic::drain();
315 }
316 
317 template <class Types>
318 void
320 {
321  SimGic::drainResume();
322 
323  KvmVM *vm = system.getKvmVM();
324  bool use_kvm = kernelGic && vm && vm->validEnvironment();
325  if (use_kvm != usingKvm) {
326  // Should only occur due to CPU switches
327  if (use_kvm) // from simulation to KVM emulation
328  fromGicToKvm();
329  // otherwise, drain() already sync'd the state back to the GicV2
330 
331  usingKvm = use_kvm;
332  }
333 }
334 
335 template <class Types>
336 Tick
338 {
339  if (!usingKvm)
340  return SimGic::read(pkt);
341 
342  panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
343 }
344 
345 template <class Types>
346 Tick
348 {
349  if (!usingKvm)
350  return SimGic::write(pkt);
351 
352  panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
353 }
354 
355 template <class Types>
356 void
358 {
359  if (!usingKvm)
360  return SimGic::sendInt(num);
361 
362  DPRINTF(Interrupt, "Set SPI %d\n", num);
363  kernelGic->setSPI(num);
364 }
365 
366 template <class Types>
367 void
369 {
370  if (!usingKvm)
371  return SimGic::clearInt(num);
372 
373  DPRINTF(Interrupt, "Clear SPI %d\n", num);
374  kernelGic->clearSPI(num);
375 }
376 
377 template <class Types>
378 void
379 MuxingKvmGic<Types>::sendPPInt(uint32_t num, uint32_t cpu)
380 {
381  if (!usingKvm)
382  return SimGic::sendPPInt(num, cpu);
383  DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
384  kernelGic->setPPI(cpu, num);
385 }
386 
387 template <class Types>
388 void
389 MuxingKvmGic<Types>::clearPPInt(uint32_t num, uint32_t cpu)
390 {
391  if (!usingKvm)
392  return SimGic::clearPPInt(num, cpu);
393 
394  DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
395  kernelGic->clearPPI(cpu, num);
396 }
397 
398 template <class Types>
399 bool
401 {
402  // During Kvm->Gic state transfer, writes to the Gic will call
403  // updateIntState() which can post an interrupt. Since we're only
404  // using the Gic model for holding state in this circumstance, we
405  // short-circuit this behavior, as the GicV2 is not actually active.
406  return usingKvm;
407 }
408 
409 template <class Types>
410 void
412 {
413  this->copyGicState(static_cast<SimGic*>(this),
414  static_cast<KvmGic*>(kernelGic));
415 }
416 
417 template <class Types>
418 void
420 {
421  this->copyGicState(static_cast<KvmGic*>(kernelGic),
422  static_cast<SimGic*>(this));
423 
424  // the values read for the Interrupt Priority Mask Register (PMR)
425  // have been shifted by three bits due to its having been emulated by
426  // a VGIC with only 5 PMR bits in its VMCR register. Presently the
427  // Linux kernel does not repair this inaccuracy, so we correct it here.
428  if constexpr(std::is_same<SimGic, GicV2>::value) {
429  for (int cpu = 0; cpu < system.threads.size(); ++cpu) {
430  this->cpuPriority[cpu] <<= 3;
431  assert((this->cpuPriority[cpu] & ~0xff) == 0);
432  }
433  }
434 }
435 
436 template class MuxingKvmGic<GicV2Types>;
437 template class MuxingKvmGic<GicV3Types>;
438 
439 } // namespace gem5
gem5::KvmKernelGic::KvmKernelGic
KvmKernelGic(KvmVM &vm, uint32_t dev, unsigned it_lines)
Instantiate a KVM in-kernel GIC model.
Definition: gic.cc:51
gem5::MuxingKvmGic::KvmGic
typename Types::KvmGic KvmGic
Definition: gic.hh:269
gem5::KvmKernelGicV3::readRedistributor
uint32_t readRedistributor(const ArmISA::Affinity &aff, Addr daddr) override
Definition: gic.cc:243
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MuxingKvmGic::SimGic
typename Types::SimGic SimGic
Definition: gic.hh:268
gem5::MuxingKvmGic::fromKvmToGic
void fromKvmToGic()
Definition: gic.cc:419
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::KvmKernelGic::setIntState
void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high)
Update the kernel's VGIC interrupt state.
Definition: gic.cc:91
gem5::MuxingKvmGic::clearPPInt
void clearPPInt(uint32_t num, uint32_t cpu) override
Definition: gic.cc:389
gem5::KvmKernelGic::vm
KvmVM & vm
KVM VM in the parent system.
Definition: gic.hh:134
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:815
gem5::KvmKernelGic
KVM in-kernel GIC abstraction.
Definition: gic.hh:61
gem5::KvmKernelGic::setPPI
void setPPI(unsigned vcpu, unsigned ppi)
Raise a private peripheral interrupt.
Definition: gic.cc:79
gem5::ArmISA::attr
attr
Definition: misc_types.hh:656
gem5::MuxingKvmGic::blockIntUpdate
bool blockIntUpdate() const override
Definition: gic.cc:400
base_cpu.hh
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::KvmKernelGic::kdev
KvmDevice kdev
Kernel interface to the GIC.
Definition: gic.hh:137
gem5::MuxingKvmGic
Definition: gic.hh:266
gem5::ArmISA::MiscRegNum64::packed
uint32_t packed() const
Definition: misc.hh:1238
gem5::MuxingKvmGic::read
Tick read(PacketPtr pkt) override
Definition: gic.cc:337
gem5::MuxingKvmGic::clearInt
void clearInt(uint32_t num) override
Definition: gic.cc:368
gem5::System::getKvmVM
KvmVM * getKvmVM() const
Get a pointer to the Kernel Virtual Machine (KVM) SimObject, if present.
Definition: system.hh:337
gem5::KvmKernelGicV3::readDistributor
uint32_t readDistributor(Addr daddr) override
Definition: gic.cc:237
gem5::KvmKernelGicV2::getGicReg
uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset)
Get value of GIC register "from" a cpu.
Definition: gic.cc:128
gem5::KvmKernelGicV3::init
void init() override
Definition: gic.cc:200
gem5::KvmDevice::setAttr
void setAttr(uint32_t group, uint64_t attr, const T &data) const
Get the value of an attribute.
Definition: device.hh:95
gem5::KvmVM
KVM VM container.
Definition: vm.hh:301
gem5::MuxingKvmGic::write
Tick write(PacketPtr pkt) override
Definition: gic.cc:347
gem5::KvmKernelGic::clearPPI
void clearPPI(unsigned vcpu, unsigned ppi)
Clear a private peripheral interrupt.
Definition: gic.cc:85
gem5::ArmISA::irq
Bitfield< 1 > irq
Definition: misc_types.hh:331
gem5::KvmKernelGicV3::writeCpu
void writeCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg, RegVal data) override
Definition: gic.cc:270
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::KvmKernelGic::clearSPI
void clearSPI(unsigned spi)
Clear a shared peripheral interrupt.
Definition: gic.cc:73
gem5::KvmDevice::setAttrPtr
void setAttrPtr(uint32_t group, uint64_t attr, const void *data) const
Definition: device.cc:84
gem5::high
high
Definition: intmath.hh:176
gem5::KvmKernelGicV2::KvmKernelGicV2
KvmKernelGicV2(KvmVM &vm, const MuxingKvmGicV2Params &params)
Instantiate a KVM in-kernel GICv2 model.
Definition: gic.cc:115
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::KvmKernelGicV3::writeRedistributor
void writeRedistributor(const ArmISA::Affinity &aff, Addr daddr, uint32_t data) override
Definition: gic.cc:263
gem5::MuxingKvmGic::fromGicToKvm
void fromGicToKvm()
Multiplexing implementation.
Definition: gic.cc:411
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gic.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::KvmKernelGicV2::writeDistributor
void writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic.cc:170
gem5::KvmKernelGic::setSPI
void setSPI(unsigned spi)
Raise a shared peripheral interrupt.
Definition: gic.cc:67
gem5::KvmVM::setIRQLine
void setIRQLine(uint32_t irq, bool high)
Set the status of an IRQ line using KVM_IRQ_LINE.
Definition: vm.cc:525
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::KvmVM::enableKernelIRQChip
void enableKernelIRQChip()
Tell the VM and VCPUs to use an in-kernel IRQ chip for interrupt delivery.
Definition: vm.hh:372
gem5::KvmKernelGicV3::writeDistributor
void writeDistributor(Addr daddr, uint32_t data) override
Definition: gic.cc:257
gem5::MuxingKvmGic::MuxingKvmGic
MuxingKvmGic(const Params &p)
Definition: gic.cc:279
gem5::KvmKernelGicV2::setGicReg
void setGicReg(unsigned group, unsigned vcpu, unsigned offset, unsigned value)
Set value of GIC register "from" a cpu.
Definition: gic.cc:142
gem5::KvmKernelGicV3::getGicReg
Ret getGicReg(unsigned group, unsigned mpidr, unsigned offset)
Get value of GIC register "from" a cpu.
Definition: gic.cc:208
gem5::KvmKernelGicV2::readDistributor
uint32_t readDistributor(ContextID ctx, Addr daddr) override
Definition: gic.cc:156
gem5::KvmVM::contextIdToVCpuId
long contextIdToVCpuId(ContextID ctx) const
Get the VCPUID for a given context.
Definition: vm.cc:566
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::encodeAArch64SysReg
MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg)
Definition: misc.cc:1314
gem5::KvmKernelGic::~KvmKernelGic
virtual ~KvmKernelGic()
Definition: gic.cc:62
gem5::ArmISA::vm
Bitfield< 0 > vm
Definition: misc_types.hh:285
gem5::KvmVM::kvm
Kvm * kvm
Global KVM interface.
Definition: vm.hh:421
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::KvmKernelGicV2::readCpu
uint32_t readCpu(ContextID ctx, Addr daddr) override
Definition: gic.cc:163
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::MuxingKvmGic::kernelGic
KvmKernelGic * kernelGic
Kernel GIC device.
Definition: gic.hh:298
misc.hh
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::MuxingKvmGic::Params
typename Types::Params Params
Definition: gic.hh:270
gem5::MuxingKvmGic::sendInt
void sendInt(uint32_t num) override
Definition: gic.cc:357
gem5::MuxingKvmGic::drain
DrainState drain() override
Definition: gic.cc:310
gem5::KvmKernelGicV3::setGicReg
void setGicReg(unsigned group, unsigned mpidr, unsigned offset, Arg value)
Set value of GIC register "from" a cpu.
Definition: gic.cc:223
gem5::KvmDevice::getAttrPtr
void getAttrPtr(uint32_t group, uint64_t attr, void *data) const
Definition: device.cc:63
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::KvmKernelGicV2::writeCpu
void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic.cc:177
gem5::MuxingKvmGic::drainResume
void drainResume() override
Definition: gic.cc:319
gem5::ArmISA::Interrupt
Definition: faults.hh:594
gem5::KvmKernelGicV3::readCpu
RegVal readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg) override
Definition: gic.cc:249
gem5::KvmKernelGicV3::KvmKernelGicV3
KvmKernelGicV3(KvmVM &vm, const MuxingKvmGicV3Params &params)
Instantiate a KVM in-kernel GICv3 model.
Definition: gic.cc:187
gem5::MuxingKvmGic::sendPPInt
void sendPPInt(uint32_t num, uint32_t cpu) override
Definition: gic.cc:379
gem5::MuxingKvmGic::startup
void startup() override
Definition: gic.cc:293
gem5::MuxingKvmGic::system
System & system
System this interrupt controller belongs to.
Definition: gic.hh:295
gem5::Kvm::capIRQLineLayout2
bool capIRQLineLayout2() const
Support for ARM IRQ line layout 2.
Definition: vm.cc:208
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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