gem5  v21.1.0.2
mem_dep_unit.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "cpu/o3/mem_dep_unit.hh"
30 
31 #include <map>
32 #include <memory>
33 #include <vector>
34 
35 #include "base/compiler.hh"
36 #include "base/debug.hh"
37 #include "cpu/o3/dyn_inst.hh"
38 #include "cpu/o3/inst_queue.hh"
39 #include "cpu/o3/limits.hh"
40 #include "debug/MemDepUnit.hh"
41 #include "params/O3CPU.hh"
42 
43 namespace gem5
44 {
45 
46 namespace o3
47 {
48 
49 #ifdef DEBUG
50 int MemDepUnit::MemDepEntry::memdep_count = 0;
51 int MemDepUnit::MemDepEntry::memdep_insert = 0;
52 int MemDepUnit::MemDepEntry::memdep_erase = 0;
53 #endif
54 
55 MemDepUnit::MemDepUnit() : iqPtr(NULL), stats(nullptr) {}
56 
57 MemDepUnit::MemDepUnit(const O3CPUParams &params)
58  : _name(params.name + ".memdepunit"),
59  depPred(params.store_set_clear_period, params.SSITSize,
60  params.LFSTSize),
61  iqPtr(NULL),
62  stats(nullptr)
63 {
64  DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
65 }
66 
68 {
69  for (ThreadID tid = 0; tid < MaxThreads; tid++) {
70 
71  ListIt inst_list_it = instList[tid].begin();
72 
73  MemDepHashIt hash_it;
74 
75  while (!instList[tid].empty()) {
76  hash_it = memDepHash.find((*inst_list_it)->seqNum);
77 
78  assert(hash_it != memDepHash.end());
79 
80  memDepHash.erase(hash_it);
81 
82  instList[tid].erase(inst_list_it++);
83  }
84  }
85 
86 #ifdef DEBUG
87  assert(MemDepEntry::memdep_count == 0);
88 #endif
89 }
90 
91 void
92 MemDepUnit::init(const O3CPUParams &params, ThreadID tid, CPU *cpu)
93 {
94  DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
95 
96  _name = csprintf("%s.memDep%d", params.name, tid);
97  id = tid;
98 
99  depPred.init(params.store_set_clear_period, params.SSITSize,
100  params.LFSTSize);
101 
102  std::string stats_group_name = csprintf("MemDepUnit__%i", tid);
103  cpu->addStatGroup(stats_group_name.c_str(), &stats);
104 }
105 
107  : statistics::Group(parent),
108  ADD_STAT(insertedLoads, statistics::units::Count::get(),
109  "Number of loads inserted to the mem dependence unit."),
110  ADD_STAT(insertedStores, statistics::units::Count::get(),
111  "Number of stores inserted to the mem dependence unit."),
112  ADD_STAT(conflictingLoads, statistics::units::Count::get(),
113  "Number of conflicting loads."),
114  ADD_STAT(conflictingStores, statistics::units::Count::get(),
115  "Number of conflicting stores.")
116 {
117 }
118 
119 bool
121 {
122  bool drained = instsToReplay.empty()
123  && memDepHash.empty()
124  && instsToReplay.empty();
125  for (int i = 0; i < MaxThreads; ++i)
126  drained = drained && instList[i].empty();
127 
128  return drained;
129 }
130 
131 void
133 {
134  assert(instsToReplay.empty());
135  assert(memDepHash.empty());
136  for (int i = 0; i < MaxThreads; ++i)
137  assert(instList[i].empty());
138  assert(instsToReplay.empty());
139  assert(memDepHash.empty());
140 }
141 
142 void
144 {
145  // Be sure to reset all state.
146  loadBarrierSNs.clear();
147  storeBarrierSNs.clear();
148  depPred.clear();
149 }
150 
151 void
153 {
154  iqPtr = iq_ptr;
155 }
156 
157 void
159 {
160  InstSeqNum barr_sn = barr_inst->seqNum;
161 
162  if (barr_inst->isReadBarrier() || barr_inst->isHtmCmd())
163  loadBarrierSNs.insert(barr_sn);
164  if (barr_inst->isWriteBarrier() || barr_inst->isHtmCmd())
165  storeBarrierSNs.insert(barr_sn);
166 
167  if (debug::MemDepUnit) {
168  const char *barrier_type = nullptr;
169  if (barr_inst->isReadBarrier() && barr_inst->isWriteBarrier())
170  barrier_type = "memory";
171  else if (barr_inst->isReadBarrier())
172  barrier_type = "read";
173  else if (barr_inst->isWriteBarrier())
174  barrier_type = "write";
175 
176  if (barrier_type) {
177  DPRINTF(MemDepUnit, "Inserted a %s barrier %s SN:%lli\n",
178  barrier_type, barr_inst->pcState(), barr_sn);
179  }
180 
181  if (loadBarrierSNs.size() || storeBarrierSNs.size()) {
182  DPRINTF(MemDepUnit, "Outstanding load barriers = %d; "
183  "store barriers = %d\n",
184  loadBarrierSNs.size(), storeBarrierSNs.size());
185  }
186  }
187 }
188 
189 void
191 {
192  ThreadID tid = inst->threadNumber;
193 
194  MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
195 
196  // Add the MemDepEntry to the hash.
197  memDepHash.insert(
198  std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
199 #ifdef DEBUG
200  MemDepEntry::memdep_insert++;
201 #endif
202 
203  instList[tid].push_back(inst);
204 
205  inst_entry->listIt = --(instList[tid].end());
206 
207  // Check any barriers and the dependence predictor for any
208  // producing memrefs/stores.
209  std::vector<InstSeqNum> producing_stores;
210  if ((inst->isLoad() || inst->isAtomic()) && hasLoadBarrier()) {
211  DPRINTF(MemDepUnit, "%d load barriers in flight\n",
212  loadBarrierSNs.size());
213  producing_stores.insert(std::end(producing_stores),
214  std::begin(loadBarrierSNs),
215  std::end(loadBarrierSNs));
216  } else if ((inst->isStore() || inst->isAtomic()) && hasStoreBarrier()) {
217  DPRINTF(MemDepUnit, "%d store barriers in flight\n",
218  storeBarrierSNs.size());
219  producing_stores.insert(std::end(producing_stores),
220  std::begin(storeBarrierSNs),
221  std::end(storeBarrierSNs));
222  } else {
223  InstSeqNum dep = depPred.checkInst(inst->instAddr());
224  if (dep != 0)
225  producing_stores.push_back(dep);
226  }
227 
228  std::vector<MemDepEntryPtr> store_entries;
229 
230  // If there is a producing store, try to find the entry.
231  for (auto producing_store : producing_stores) {
232  DPRINTF(MemDepUnit, "Searching for producer [sn:%lli]\n",
233  producing_store);
234  MemDepHashIt hash_it = memDepHash.find(producing_store);
235 
236  if (hash_it != memDepHash.end()) {
237  store_entries.push_back((*hash_it).second);
238  DPRINTF(MemDepUnit, "Producer found\n");
239  }
240  }
241 
242  // If no store entry, then instruction can issue as soon as the registers
243  // are ready.
244  if (store_entries.empty()) {
245  DPRINTF(MemDepUnit, "No dependency for inst PC "
246  "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
247 
248  assert(inst_entry->memDeps == 0);
249 
250  if (inst->readyToIssue()) {
251  inst_entry->regsReady = true;
252 
253  moveToReady(inst_entry);
254  }
255  } else {
256  // Otherwise make the instruction dependent on the store/barrier.
257  DPRINTF(MemDepUnit, "Adding to dependency list\n");
258  for (GEM5_VAR_USED auto producing_store : producing_stores)
259  DPRINTF(MemDepUnit, "\tinst PC %s is dependent on [sn:%lli].\n",
260  inst->pcState(), producing_store);
261 
262  if (inst->readyToIssue()) {
263  inst_entry->regsReady = true;
264  }
265 
266  // Clear the bit saying this instruction can issue.
267  inst->clearCanIssue();
268 
269  // Add this instruction to the list of dependents.
270  for (auto store_entry : store_entries)
271  store_entry->dependInsts.push_back(inst_entry);
272 
273  inst_entry->memDeps = store_entries.size();
274 
275  if (inst->isLoad()) {
277  } else {
279  }
280  }
281 
282  // for load-acquire store-release that could also be a barrier
283  insertBarrierSN(inst);
284 
285  if (inst->isStore() || inst->isAtomic()) {
286  DPRINTF(MemDepUnit, "Inserting store/atomic PC %s [sn:%lli].\n",
287  inst->pcState(), inst->seqNum);
288 
289  depPred.insertStore(inst->instAddr(), inst->seqNum,
290  inst->threadNumber);
291 
293  } else if (inst->isLoad()) {
295  } else {
296  panic("Unknown type! (most likely a barrier).");
297  }
298 }
299 
300 void
302 {
303  insertBarrier(inst);
304 
305  // Might want to turn this part into an inline function or something.
306  // It's shared between both insert functions.
307  if (inst->isStore() || inst->isAtomic()) {
308  DPRINTF(MemDepUnit, "Inserting store/atomic PC %s [sn:%lli].\n",
309  inst->pcState(), inst->seqNum);
310 
311  depPred.insertStore(inst->instAddr(), inst->seqNum,
312  inst->threadNumber);
313 
315  } else if (inst->isLoad()) {
317  } else {
318  panic("Unknown type! (most likely a barrier).");
319  }
320 }
321 
322 void
324 {
325  ThreadID tid = barr_inst->threadNumber;
326 
327  MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(barr_inst);
328 
329  // Add the MemDepEntry to the hash.
330  memDepHash.insert(
331  std::pair<InstSeqNum, MemDepEntryPtr>(barr_inst->seqNum, inst_entry));
332 #ifdef DEBUG
333  MemDepEntry::memdep_insert++;
334 #endif
335 
336  // Add the instruction to the instruction list.
337  instList[tid].push_back(barr_inst);
338 
339  inst_entry->listIt = --(instList[tid].end());
340 
341  insertBarrierSN(barr_inst);
342 }
343 
344 void
346 {
347  DPRINTF(MemDepUnit, "Marking registers as ready for "
348  "instruction PC %s [sn:%lli].\n",
349  inst->pcState(), inst->seqNum);
350 
351  MemDepEntryPtr inst_entry = findInHash(inst);
352 
353  inst_entry->regsReady = true;
354 
355  if (inst_entry->memDeps == 0) {
356  DPRINTF(MemDepUnit, "Instruction has its memory "
357  "dependencies resolved, adding it to the ready list.\n");
358 
359  moveToReady(inst_entry);
360  } else {
361  DPRINTF(MemDepUnit, "Instruction still waiting on "
362  "memory dependency.\n");
363  }
364 }
365 
366 void
368 {
369  DPRINTF(MemDepUnit, "Marking non speculative "
370  "instruction PC %s as ready [sn:%lli].\n",
371  inst->pcState(), inst->seqNum);
372 
373  MemDepEntryPtr inst_entry = findInHash(inst);
374 
375  moveToReady(inst_entry);
376 }
377 
378 void
380 {
381  instsToReplay.push_back(inst);
382 }
383 
384 void
386 {
387  DynInstPtr temp_inst;
388 
389  // For now this replay function replays all waiting memory ops.
390  while (!instsToReplay.empty()) {
391  temp_inst = instsToReplay.front();
392 
393  MemDepEntryPtr inst_entry = findInHash(temp_inst);
394 
395  DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
396  temp_inst->pcState(), temp_inst->seqNum);
397 
398  moveToReady(inst_entry);
399 
400  instsToReplay.pop_front();
401  }
402 }
403 
404 void
406 {
407  DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
408  inst->pcState(), inst->seqNum);
409 
410  ThreadID tid = inst->threadNumber;
411 
412  // Remove the instruction from the hash and the list.
413  MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
414 
415  assert(hash_it != memDepHash.end());
416 
417  instList[tid].erase((*hash_it).second->listIt);
418 
419  (*hash_it).second = NULL;
420 
421  memDepHash.erase(hash_it);
422 #ifdef DEBUG
423  MemDepEntry::memdep_erase++;
424 #endif
425 }
426 
427 void
429 {
430  wakeDependents(inst);
431  completed(inst);
432  InstSeqNum barr_sn = inst->seqNum;
433 
434  if (inst->isWriteBarrier() || inst->isHtmCmd()) {
435  assert(hasStoreBarrier());
436  storeBarrierSNs.erase(barr_sn);
437  }
438  if (inst->isReadBarrier() || inst->isHtmCmd()) {
439  assert(hasLoadBarrier());
440  loadBarrierSNs.erase(barr_sn);
441  }
442  if (debug::MemDepUnit) {
443  const char *barrier_type = nullptr;
444  if (inst->isWriteBarrier() && inst->isReadBarrier())
445  barrier_type = "Memory";
446  else if (inst->isWriteBarrier())
447  barrier_type = "Write";
448  else if (inst->isReadBarrier())
449  barrier_type = "Read";
450 
451  if (barrier_type) {
452  DPRINTF(MemDepUnit, "%s barrier completed: %s SN:%lli\n",
453  barrier_type, inst->pcState(), inst->seqNum);
454  }
455  }
456 }
457 
458 void
460 {
461  // Only stores, atomics and barriers have dependents.
462  if (!inst->isStore() && !inst->isAtomic() && !inst->isReadBarrier() &&
463  !inst->isWriteBarrier() && !inst->isHtmCmd()) {
464  return;
465  }
466 
467  MemDepEntryPtr inst_entry = findInHash(inst);
468 
469  for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
470  MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
471 
472  if (!woken_inst->inst) {
473  // Potentially removed mem dep entries could be on this list
474  continue;
475  }
476 
477  DPRINTF(MemDepUnit, "Waking up a dependent inst, "
478  "[sn:%lli].\n",
479  woken_inst->inst->seqNum);
480 
481  assert(woken_inst->memDeps > 0);
482  woken_inst->memDeps -= 1;
483 
484  if ((woken_inst->memDeps == 0) &&
485  woken_inst->regsReady &&
486  !woken_inst->squashed) {
487  moveToReady(woken_inst);
488  }
489  }
490 
491  inst_entry->dependInsts.clear();
492 }
493 
495  inst(new_inst)
496 {
497 #ifdef DEBUG
498  ++memdep_count;
499 
501  "Memory dependency entry created. memdep_count=%i %s\n",
502  memdep_count, inst->pcState());
503 #endif
504 }
505 
507 {
508  for (int i = 0; i < dependInsts.size(); ++i) {
509  dependInsts[i] = NULL;
510  }
511 #ifdef DEBUG
512  --memdep_count;
513 
515  "Memory dependency entry deleted. memdep_count=%i %s\n",
516  memdep_count, inst->pcState());
517 #endif
518 }
519 
520 void
521 MemDepUnit::squash(const InstSeqNum &squashed_num, ThreadID tid)
522 {
523  if (!instsToReplay.empty()) {
524  ListIt replay_it = instsToReplay.begin();
525  while (replay_it != instsToReplay.end()) {
526  if ((*replay_it)->threadNumber == tid &&
527  (*replay_it)->seqNum > squashed_num) {
528  instsToReplay.erase(replay_it++);
529  } else {
530  ++replay_it;
531  }
532  }
533  }
534 
535  ListIt squash_it = instList[tid].end();
536  --squash_it;
537 
538  MemDepHashIt hash_it;
539 
540  while (!instList[tid].empty() &&
541  (*squash_it)->seqNum > squashed_num) {
542 
543  DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
544  (*squash_it)->seqNum);
545 
546  loadBarrierSNs.erase((*squash_it)->seqNum);
547 
548  storeBarrierSNs.erase((*squash_it)->seqNum);
549 
550  hash_it = memDepHash.find((*squash_it)->seqNum);
551 
552  assert(hash_it != memDepHash.end());
553 
554  (*hash_it).second->squashed = true;
555 
556  (*hash_it).second = NULL;
557 
558  memDepHash.erase(hash_it);
559 #ifdef DEBUG
560  MemDepEntry::memdep_erase++;
561 #endif
562 
563  instList[tid].erase(squash_it--);
564  }
565 
566  // Tell the dependency predictor to squash as well.
567  depPred.squash(squashed_num, tid);
568 }
569 
570 void
572  const DynInstPtr &violating_load)
573 {
574  DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
575  " load: %#x, store: %#x\n", violating_load->instAddr(),
576  store_inst->instAddr());
577  // Tell the memory dependence unit of the violation.
578  depPred.violation(store_inst->instAddr(), violating_load->instAddr());
579 }
580 
581 void
583 {
584  DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
585  inst->instAddr(), inst->seqNum);
586 
587  depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
588 }
589 
592 {
593  MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
594 
595  assert(hash_it != memDepHash.end());
596 
597  return (*hash_it).second;
598 }
599 
600 void
602 {
603  DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
604  "to the ready list.\n", woken_inst_entry->inst->seqNum);
605 
606  assert(!woken_inst_entry->squashed);
607 
608  iqPtr->addReadyMemInst(woken_inst_entry->inst);
609 }
610 
611 
612 void
614 {
615  for (ThreadID tid = 0; tid < MaxThreads; tid++) {
616  cprintf("Instruction list %i size: %i\n",
617  tid, instList[tid].size());
618 
619  ListIt inst_list_it = instList[tid].begin();
620  int num = 0;
621 
622  while (inst_list_it != instList[tid].end()) {
623  cprintf("Instruction:%i\nPC: %s\n[sn:%llu]\n[tid:%i]\nIssued:%i\n"
624  "Squashed:%i\n\n",
625  num, (*inst_list_it)->pcState(),
626  (*inst_list_it)->seqNum,
627  (*inst_list_it)->threadNumber,
628  (*inst_list_it)->isIssued(),
629  (*inst_list_it)->isSquashed());
630  inst_list_it++;
631  ++num;
632  }
633  }
634 
635  cprintf("Memory dependence hash size: %i\n", memDepHash.size());
636 
637 #ifdef DEBUG
638  cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
639 #endif
640 }
641 
642 } // namespace o3
643 } // namespace gem5
gem5::o3::MemDepUnit::insertBarrierSN
void insertBarrierSN(const DynInstPtr &barr_inst)
Inserts the SN of a barrier inst.
Definition: mem_dep_unit.cc:158
gem5::o3::MemDepUnit::hasStoreBarrier
bool hasStoreBarrier() const
Is there an outstanding store barrier that loads must wait on.
Definition: mem_dep_unit.hh:256
gem5::o3::StoreSet::issued
void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
Records this PC/sequence number as issued.
Definition: store_set.cc:278
gem5::o3::MemDepUnit::MemDepEntry::~MemDepEntry
~MemDepEntry()
Frees any pointers.
Definition: mem_dep_unit.cc:506
gem5::o3::MemDepUnit::iqPtr
InstructionQueue * iqPtr
Pointer to the IQ.
Definition: mem_dep_unit.hh:262
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::o3::StoreSet::init
void init(uint64_t clear_period, int SSIT_size, int LFST_size)
Initializes the store set predictor with the given table sizes.
Definition: store_set.cc:85
gem5::o3::MemDepUnit::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a barrier instruction.
Definition: mem_dep_unit.cc:323
gem5::o3::MemDepUnit::MemDepUnitStats::MemDepUnitStats
MemDepUnitStats(statistics::Group *parent)
Definition: mem_dep_unit.cc:106
gem5::o3::InstructionQueue
A standard instruction queue class.
Definition: inst_queue.hh:98
gem5::o3::MemDepUnit::~MemDepUnit
~MemDepUnit()
Frees up any memory allocated.
Definition: mem_dep_unit.cc:67
gem5::o3::MemDepUnit::completeInst
void completeInst(const DynInstPtr &inst)
Notifies completion of an instruction.
Definition: mem_dep_unit.cc:428
gem5::o3::MemDepUnit::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squashes all instructions up until a given sequence number for a specific thread.
Definition: mem_dep_unit.cc:521
gem5::o3::MemDepUnit::MemDepUnitStats::conflictingStores
statistics::Scalar conflictingStores
Stat for number of conflicting stores that had to wait for a store.
Definition: mem_dep_unit.hh:278
gem5::o3::StoreSet::insertStore
void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid)
Inserts a store into the store set predictor.
Definition: store_set.cc:213
gem5::o3::MemDepUnit::instList
std::list< DynInstPtr > instList[MaxThreads]
A list of all instructions in the memory dependence unit.
Definition: mem_dep_unit.hh:234
std::vector< InstSeqNum >
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
dyn_inst.hh
gem5::o3::MemDepUnit::hasLoadBarrier
bool hasLoadBarrier() const
Is there an outstanding load barrier that loads must wait on.
Definition: mem_dep_unit.hh:253
gem5::o3::MemDepUnit::instsToReplay
std::list< DynInstPtr > instsToReplay
A list of all instructions that are going to be replayed.
Definition: mem_dep_unit.hh:237
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::o3::MemDepUnit
Memory dependency unit class.
Definition: mem_dep_unit.hh:90
gem5::o3::MemDepUnit::MemDepUnitStats::insertedLoads
statistics::Scalar insertedLoads
Stat for number of inserted loads.
Definition: mem_dep_unit.hh:270
gem5::o3::MemDepUnit::storeBarrierSNs
std::unordered_set< InstSeqNum > storeBarrierSNs
Sequence numbers of outstanding store barriers.
Definition: mem_dep_unit.hh:250
gem5::RefCountingPtr< DynInst >
gem5::o3::MemDepUnit::issue
void issue(const DynInstPtr &inst)
Issues the given instruction.
Definition: mem_dep_unit.cc:582
gem5::o3::MemDepUnit::stats
gem5::o3::MemDepUnit::MemDepUnitStats stats
gem5::o3::MemDepUnit::replay
void replay()
Replays all instructions that have been rescheduled by moving them to the ready list.
Definition: mem_dep_unit.cc:385
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::MemDepUnit::setIQ
void setIQ(InstructionQueue *iq_ptr)
Sets the pointer to the IQ.
Definition: mem_dep_unit.cc:152
gem5::o3::MemDepUnit::moveToReady
void moveToReady(MemDepEntryPtr &ready_inst_entry)
Moves an entry to the ready list.
Definition: mem_dep_unit.cc:601
gem5::o3::MemDepUnit::isDrained
bool isDrained() const
Determine if we are drained.
Definition: mem_dep_unit.cc:120
gem5::o3::MemDepUnit::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: mem_dep_unit.hh:172
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::MemDepUnit::loadBarrierSNs
std::unordered_set< InstSeqNum > loadBarrierSNs
Sequence numbers of outstanding load barriers.
Definition: mem_dep_unit.hh:247
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::MemDepUnit::MemDepEntry::inst
DynInstPtr inst
The instruction being tracked.
Definition: mem_dep_unit.hh:195
gem5::o3::MemDepUnit::nonSpecInstReady
void nonSpecInstReady(const DynInstPtr &inst)
Indicate that a non-speculative instruction is ready.
Definition: mem_dep_unit.cc:367
mem_dep_unit.hh
gem5::o3::StoreSet::clear
void clear()
Resets all tables.
Definition: store_set.cc:345
debug.hh
gem5::o3::MemDepUnit::violation
void violation(const DynInstPtr &store_inst, const DynInstPtr &violating_load)
Indicates an ordering violation between a store and a younger load.
Definition: mem_dep_unit.cc:571
gem5::o3::MemDepUnit::MemDepUnitStats::conflictingLoads
statistics::Scalar conflictingLoads
Stat for number of conflicting loads that had to wait for a store.
Definition: mem_dep_unit.hh:275
compiler.hh
gem5::statistics::Group::addStatGroup
void addStatGroup(const char *name, Group *block)
Add a stat block as a child of this block.
Definition: group.cc:117
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::MemDepUnit::MemDepEntryPtr
std::shared_ptr< MemDepEntry > MemDepEntryPtr
Definition: mem_dep_unit.hh:174
name
const std::string & name()
Definition: trace.cc:49
gem5::o3::MemDepUnit::wakeDependents
void wakeDependents(const DynInstPtr &inst)
Wakes any dependents of a memory instruction.
Definition: mem_dep_unit.cc:459
gem5::o3::StoreSet::violation
void violation(Addr store_PC, Addr load_PC)
Records a memory ordering violation between the younger load and the older store.
Definition: store_set.cc:120
gem5::o3::MemDepUnit::findInHash
MemDepEntryPtr & findInHash(const DynInstConstPtr &inst)
Finds the memory dependence entry in the hash map.
Definition: mem_dep_unit.cc:591
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::MemDepUnit::regsReady
void regsReady(const DynInstPtr &inst)
Indicate that an instruction has its registers ready.
Definition: mem_dep_unit.cc:345
gem5::o3::MemDepUnit::dumpLists
void dumpLists()
Debugging function to dump the lists of instructions.
Definition: mem_dep_unit.cc:613
gem5::o3::MemDepUnit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: mem_dep_unit.cc:132
gem5::o3::InstructionQueue::addReadyMemInst
void addReadyMemInst(const DynInstPtr &ready_inst)
Adds a ready memory instruction to the ready list.
Definition: inst_queue.cc:1063
gem5::o3::MemDepUnit::completed
void completed(const DynInstPtr &inst)
Completes a memory instruction.
Definition: mem_dep_unit.cc:405
gem5::o3::MemDepUnit::insertNonSpec
void insertNonSpec(const DynInstPtr &inst)
Inserts a non-speculative memory instruction.
Definition: mem_dep_unit.cc:301
gem5::o3::MemDepUnit::MemDepUnitStats::insertedStores
statistics::Scalar insertedStores
Stat for number of inserted stores.
Definition: mem_dep_unit.hh:272
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::MemDepUnit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: mem_dep_unit.cc:143
inst_queue.hh
gem5::o3::MemDepUnit::memDepHash
MemDepHash memDepHash
A hash map of all memory dependence entries.
Definition: mem_dep_unit.hh:231
gem5::o3::MemDepUnit::MemDepUnit
MemDepUnit()
Empty constructor.
Definition: mem_dep_unit.cc:55
gem5::o3::StoreSet::checkInst
InstSeqNum checkInst(Addr PC)
Checks if the instruction with the given PC is dependent upon any store.
Definition: store_set.cc:243
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
limits.hh
gem5::o3::MemDepUnit::depPred
StoreSet depPred
The memory dependence predictor.
Definition: mem_dep_unit.hh:244
gem5::o3::StoreSet::squash
void squash(InstSeqNum squashed_num, ThreadID tid)
Squashes for a specific thread until the given sequence number.
Definition: store_set.cc:315
gem5::o3::MemDepUnit::init
void init(const O3CPUParams &params, ThreadID tid, CPU *cpu)
Initializes the unit with parameters and a thread id.
Definition: mem_dep_unit.cc:92
gem5::o3::MemDepUnit::MemDepHashIt
MemDepHash::iterator MemDepHashIt
Definition: mem_dep_unit.hh:228
gem5::o3::MemDepUnit::insert
void insert(const DynInstPtr &inst)
Inserts a memory instruction.
Definition: mem_dep_unit.cc:190
gem5::o3::MemDepUnit::MemDepEntry::MemDepEntry
MemDepEntry(const DynInstPtr &new_inst)
Constructs a memory dependence entry.
Definition: mem_dep_unit.cc:494
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::MemDepUnit::_name
std::string _name
Definition: mem_dep_unit.hh:93
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::MemDepUnit::reschedule
void reschedule(const DynInstPtr &inst)
Reschedules an instruction to be re-executed.
Definition: mem_dep_unit.cc:379

Generated on Tue Sep 21 2021 12:25:05 for gem5 by doxygen 1.8.17