gem5  v21.1.0.2
isa.cc
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28 
29 #include "arch/x86/isa.hh"
30 
31 #include "arch/x86/decoder.hh"
32 #include "arch/x86/mmu.hh"
33 #include "arch/x86/regs/ccr.hh"
34 #include "arch/x86/regs/int.hh"
35 #include "arch/x86/regs/misc.hh"
36 #include "base/compiler.hh"
37 #include "cpu/base.hh"
38 #include "cpu/thread_context.hh"
39 #include "params/X86ISA.hh"
40 #include "sim/serialize.hh"
41 
42 namespace gem5
43 {
44 
45 namespace X86ISA
46 {
47 
48 void
49 ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
50  SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
51 {
52  HandyM5Reg m5reg = 0;
53  if (efer.lma) {
54  m5reg.mode = LongMode;
55  if (csAttr.longMode)
56  m5reg.submode = SixtyFourBitMode;
57  else
58  m5reg.submode = CompatabilityMode;
59  } else {
60  m5reg.mode = LegacyMode;
61  if (cr0.pe) {
62  if (rflags.vm)
63  m5reg.submode = Virtual8086Mode;
64  else
65  m5reg.submode = ProtectedMode;
66  } else {
67  m5reg.submode = RealMode;
68  }
69  }
70  m5reg.cpl = csAttr.dpl;
71  m5reg.paging = cr0.pg;
72  m5reg.prot = cr0.pe;
73 
74  // Compute the default and alternate operand size.
75  if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
76  m5reg.defOp = 2;
77  m5reg.altOp = 1;
78  } else {
79  m5reg.defOp = 1;
80  m5reg.altOp = 2;
81  }
82 
83  // Compute the default and alternate address size.
84  if (m5reg.submode == SixtyFourBitMode) {
85  m5reg.defAddr = 3;
86  m5reg.altAddr = 2;
87  } else if (csAttr.defaultSize) {
88  m5reg.defAddr = 2;
89  m5reg.altAddr = 1;
90  } else {
91  m5reg.defAddr = 1;
92  m5reg.altAddr = 2;
93  }
94 
95  // Compute the stack size
96  if (m5reg.submode == SixtyFourBitMode) {
97  m5reg.stack = 3;
98  } else if (ssAttr.defaultSize) {
99  m5reg.stack = 2;
100  } else {
101  m5reg.stack = 1;
102  }
103 
104  regVal[MISCREG_M5_REG] = m5reg;
105  if (tc)
106  tc->getDecoderPtr()->setM5Reg(m5reg);
107 }
108 
109 void
111 {
112  // Blank everything. 0 might not be an appropriate value for some things,
113  // but it is for most.
114  memset(regVal, 0, NUM_MISCREGS * sizeof(RegVal));
115 
116  // If some state should be non-zero after a reset, set those values here.
117  regVal[MISCREG_CR0] = 0x0000000060000010ULL;
118 
119  regVal[MISCREG_MTRRCAP] = 0x0508;
120 
121  regVal[MISCREG_MCG_CAP] = 0x104;
122 
123  regVal[MISCREG_PAT] = 0x0007040600070406ULL;
124 
125  regVal[MISCREG_SYSCFG] = 0x20601;
126 
127  regVal[MISCREG_TOP_MEM] = 0x4000000;
128 
129  regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
130  regVal[MISCREG_DR7] = 1 << 10;
131 
132  LocalApicBase lApicBase = 0;
133  lApicBase.base = 0xFEE00000 >> 12;
134  lApicBase.enable = 1;
135  // The "bsp" bit will be set when this register is read, since then we'll
136  // have a ThreadContext to check the contextId from.
137  regVal[MISCREG_APIC_BASE] = lApicBase;
138 }
139 
140 ISA::ISA(const X86ISAParams &p) : BaseISA(p), vendorString(p.vendor_string)
141 {
142  fatal_if(vendorString.size() != 12,
143  "CPUID vendor string must be 12 characters\n");
144 
145  _regClasses.emplace_back(NumIntRegs, INTREG_T0);
146  _regClasses.emplace_back(NumFloatRegs);
147  _regClasses.emplace_back(1); // Not applicable to X86
148  _regClasses.emplace_back(2); // Not applicable to X86
149  _regClasses.emplace_back(1); // Not applicable to X86
150  _regClasses.emplace_back(NUM_CCREGS);
151  _regClasses.emplace_back(NUM_MISCREGS);
152 
153  clear();
154 }
155 
156 static void
158 {
159  // This function assumes no side effects other than TLB invalidation
160  // need to be considered while copying state. That will likely not be
161  // true in the future.
162  for (int i = 0; i < NUM_MISCREGS; ++i) {
163  if (!isValidMiscReg(i))
164  continue;
165 
167  }
168 
169  // The TSC has to be updated with side-effects if the CPUs in a
170  // CPU switch have different frequencies.
172 
173  dest->getMMUPtr()->flushAll();
174 }
175 
176 void
178 {
179  //copy int regs
180  for (int i = 0; i < NumIntRegs; ++i)
181  tc->setIntRegFlat(i, src->readIntRegFlat(i));
182  //copy float regs
183  for (int i = 0; i < NumFloatRegs; ++i)
185  //copy condition-code regs
186  for (int i = 0; i < NUM_CCREGS; ++i)
187  tc->setCCRegFlat(i, src->readCCRegFlat(i));
188  copyMiscRegs(src, tc);
189  tc->pcState(src->pcState());
190 }
191 
192 RegVal
193 ISA::readMiscRegNoEffect(int miscReg) const
194 {
195  // Make sure we're not dealing with an illegal control register.
196  // Instructions should filter out these indexes, and nothing else should
197  // attempt to read them directly.
198  assert(isValidMiscReg(miscReg));
199 
200  return regVal[miscReg];
201 }
202 
203 RegVal
204 ISA::readMiscReg(int miscReg)
205 {
206  if (miscReg == MISCREG_TSC) {
207  return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
208  }
209 
210  if (miscReg == MISCREG_FSW) {
211  RegVal fsw = regVal[MISCREG_FSW];
213  return insertBits(fsw, 13, 11, top);
214  }
215 
216  if (miscReg == MISCREG_APIC_BASE) {
217  LocalApicBase base = regVal[MISCREG_APIC_BASE];
218  base.bsp = (tc->contextId() == 0);
219  return base;
220  }
221 
222  return readMiscRegNoEffect(miscReg);
223 }
224 
225 void
227 {
228  // Make sure we're not dealing with an illegal control register.
229  // Instructions should filter out these indexes, and nothing else should
230  // attempt to write to them directly.
231  assert(isValidMiscReg(miscReg));
232 
233  HandyM5Reg m5Reg = regVal[MISCREG_M5_REG];
234  int reg_width = 64;
235  switch (miscReg) {
236  case MISCREG_X87_TOP:
237  reg_width = 3;
238  break;
239  case MISCREG_FTW:
240  reg_width = 8;
241  break;
242  case MISCREG_FSW:
243  case MISCREG_FCW:
244  case MISCREG_FOP:
245  reg_width = 16;
246  break;
247  case MISCREG_MXCSR:
248  reg_width = 32;
249  break;
250  case MISCREG_FISEG:
251  case MISCREG_FOSEG:
252  if (m5Reg.submode != SixtyFourBitMode)
253  reg_width = 16;
254  break;
255  case MISCREG_FIOFF:
256  case MISCREG_FOOFF:
257  if (m5Reg.submode != SixtyFourBitMode)
258  reg_width = 32;
259  break;
260  default:
261  break;
262  }
263 
264  regVal[miscReg] = val & mask(reg_width);
265 }
266 
267 void
269 {
270  RegVal newVal = val;
271  switch(miscReg)
272  {
273  case MISCREG_CR0:
274  {
275  CR0 toggled = regVal[miscReg] ^ val;
276  CR0 newCR0 = val;
277  Efer efer = regVal[MISCREG_EFER];
278  if (toggled.pg && efer.lme) {
279  if (newCR0.pg) {
280  //Turning on long mode
281  efer.lma = 1;
282  regVal[MISCREG_EFER] = efer;
283  } else {
284  //Turning off long mode
285  efer.lma = 0;
286  regVal[MISCREG_EFER] = efer;
287  }
288  }
289  if (toggled.pg) {
290  tc->getMMUPtr()->flushAll();
291  }
292  //This must always be 1.
293  newCR0.et = 1;
294  newVal = newCR0;
296  newCR0,
300  }
301  break;
302  case MISCREG_CR2:
303  break;
304  case MISCREG_CR3:
305  static_cast<MMU *>(tc->getMMUPtr())->flushNonGlobal();
306  break;
307  case MISCREG_CR4:
308  {
309  CR4 toggled = regVal[miscReg] ^ val;
310  if (toggled.pae || toggled.pse || toggled.pge) {
311  tc->getMMUPtr()->flushAll();
312  }
313  }
314  break;
315  case MISCREG_CR8:
316  break;
317  case MISCREG_CS_ATTR:
318  {
319  SegAttr toggled = regVal[miscReg] ^ val;
320  SegAttr newCSAttr = val;
321  if (toggled.longMode) {
322  if (newCSAttr.longMode) {
327  } else {
332  }
333  }
336  newCSAttr,
339  }
340  break;
341  case MISCREG_SS_ATTR:
345  val,
347  break;
348  // These segments always actually use their bases, or in other words
349  // their effective bases must stay equal to their actual bases.
350  case MISCREG_FS_BASE:
351  case MISCREG_GS_BASE:
352  case MISCREG_HS_BASE:
353  case MISCREG_TSL_BASE:
354  case MISCREG_TSG_BASE:
355  case MISCREG_TR_BASE:
356  case MISCREG_IDTR_BASE:
358  break;
359  // These segments ignore their bases in 64 bit mode.
360  // their effective bases must stay equal to their actual bases.
361  case MISCREG_ES_BASE:
362  case MISCREG_CS_BASE:
363  case MISCREG_SS_BASE:
364  case MISCREG_DS_BASE:
365  {
366  Efer efer = regVal[MISCREG_EFER];
367  SegAttr csAttr = regVal[MISCREG_CS_ATTR];
368  if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
369  regVal[MISCREG_SEG_EFF_BASE(miscReg -
371  }
372  break;
373  case MISCREG_TSC:
375  return;
376  case MISCREG_DR0:
377  case MISCREG_DR1:
378  case MISCREG_DR2:
379  case MISCREG_DR3:
380  /* These should eventually set up breakpoints. */
381  break;
382  case MISCREG_DR4:
383  miscReg = MISCREG_DR6;
385  case MISCREG_DR6:
386  {
387  DR6 dr6 = regVal[MISCREG_DR6];
388  DR6 newDR6 = val;
389  dr6.b0 = newDR6.b0;
390  dr6.b1 = newDR6.b1;
391  dr6.b2 = newDR6.b2;
392  dr6.b3 = newDR6.b3;
393  dr6.bd = newDR6.bd;
394  dr6.bs = newDR6.bs;
395  dr6.bt = newDR6.bt;
396  newVal = dr6;
397  }
398  break;
399  case MISCREG_DR5:
400  miscReg = MISCREG_DR7;
402  case MISCREG_DR7:
403  {
404  DR7 dr7 = regVal[MISCREG_DR7];
405  DR7 newDR7 = val;
406  dr7.l0 = newDR7.l0;
407  dr7.g0 = newDR7.g0;
408  if (dr7.l0 || dr7.g0) {
409  panic("Debug register breakpoints not implemented.\n");
410  } else {
411  /* Disable breakpoint 0. */
412  }
413  dr7.l1 = newDR7.l1;
414  dr7.g1 = newDR7.g1;
415  if (dr7.l1 || dr7.g1) {
416  panic("Debug register breakpoints not implemented.\n");
417  } else {
418  /* Disable breakpoint 1. */
419  }
420  dr7.l2 = newDR7.l2;
421  dr7.g2 = newDR7.g2;
422  if (dr7.l2 || dr7.g2) {
423  panic("Debug register breakpoints not implemented.\n");
424  } else {
425  /* Disable breakpoint 2. */
426  }
427  dr7.l3 = newDR7.l3;
428  dr7.g3 = newDR7.g3;
429  if (dr7.l3 || dr7.g3) {
430  panic("Debug register breakpoints not implemented.\n");
431  } else {
432  /* Disable breakpoint 3. */
433  }
434  dr7.gd = newDR7.gd;
435  dr7.rw0 = newDR7.rw0;
436  dr7.len0 = newDR7.len0;
437  dr7.rw1 = newDR7.rw1;
438  dr7.len1 = newDR7.len1;
439  dr7.rw2 = newDR7.rw2;
440  dr7.len2 = newDR7.len2;
441  dr7.rw3 = newDR7.rw3;
442  dr7.len3 = newDR7.len3;
443  }
444  break;
445  case MISCREG_M5_REG:
446  // Writing anything to the m5reg with side effects makes it update
447  // based on the current values of the relevant registers. The actual
448  // value written is discarded.
454  return;
455  default:
456  break;
457  }
458  setMiscRegNoEffect(miscReg, newVal);
459 }
460 
461 void
463 {
465 }
466 
467 void
469 {
476 }
477 
478 void
480 {
482  tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
483 }
484 
485 std::string
487 {
488  return vendorString;
489 }
490 
491 } // namespace X86ISA
492 } // namespace gem5
gem5::X86ISA::mask
mask
Definition: misc.hh:802
gem5::X86ISA::MISCREG_FS_BASE
@ MISCREG_FS_BASE
Definition: misc.hh:322
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::X86ISA::MISCREG_M5_REG
@ MISCREG_M5_REG
Definition: misc.hh:143
gem5::X86ISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:177
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::X86ISA::MISCREG_DR1
@ MISCREG_DR1
Definition: misc.hh:131
mmu.hh
gem5::Clocked::curCycle
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Definition: clocked_object.hh:195
serialize.hh
gem5::X86ISA::isValidMiscReg
static bool isValidMiscReg(int index)
Definition: misc.hh:408
gem5::X86ISA::MISCREG_CR8
@ MISCREG_CR8
Definition: misc.hh:119
gem5::X86ISA::MISCREG_DR3
@ MISCREG_DR3
Definition: misc.hh:133
gem5::X86ISA::MISCREG_APIC_BASE
@ MISCREG_APIC_BASE
Definition: misc.hh:399
gem5::X86ISA::NUM_CCREGS
@ NUM_CCREGS
Definition: ccr.hh:56
gem5::X86ISA::ISA::vendorString
std::string vendorString
Definition: isa.hh:57
gem5::X86ISA::MISCREG_DS_EFF_BASE
@ MISCREG_DS_EFF_BASE
Definition: misc.hh:339
gem5::X86ISA::copyMiscRegs
static void copyMiscRegs(ThreadContext *src, ThreadContext *dest)
Definition: isa.cc:157
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::MISCREG_MTRRCAP
@ MISCREG_MTRRCAP
Definition: misc.hh:151
gem5::X86ISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:140
gem5::X86ISA::MISCREG_SS_BASE
@ MISCREG_SS_BASE
Definition: misc.hh:320
GEM5_FALLTHROUGH
#define GEM5_FALLTHROUGH
Definition: compiler.hh:61
ccr.hh
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::X86ISA::MISCREG_FIOFF
@ MISCREG_FIOFF
Definition: misc.hh:392
gem5::X86ISA::MISCREG_FISEG
@ MISCREG_FISEG
Definition: misc.hh:391
gem5::X86ISA::MISCREG_FOOFF
@ MISCREG_FOOFF
Definition: misc.hh:394
gem5::ThreadContext::readCCRegFlat
virtual RegVal readCCRegFlat(RegIndex idx) const =0
top
Definition: test.h:61
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::X86ISA::MISCREG_X87_TOP
@ MISCREG_X87_TOP
Definition: misc.hh:383
gem5::X86ISA::MISCREG_ES_BASE
@ MISCREG_ES_BASE
Definition: misc.hh:318
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::X86ISA::MISCREG_TR_BASE
@ MISCREG_TR_BASE
Definition: misc.hh:329
gem5::X86ISA::MISCREG_MCG_CAP
@ MISCREG_MCG_CAP
Definition: misc.hh:157
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::X86ISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:404
gem5::X86ISA::Virtual8086Mode
@ Virtual8086Mode
Definition: types.hh:201
gem5::X86ISA::MISCREG_DR2
@ MISCREG_DR2
Definition: misc.hh:132
gem5::X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:198
gem5::X86ISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:188
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::X86ISA::ISA::setMiscReg
void setMiscReg(int miscReg, RegVal val)
Definition: isa.cc:268
gem5::X86ISA::MISCREG_IDTR_BASE
@ MISCREG_IDTR_BASE
Definition: misc.hh:330
gem5::X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:114
decoder.hh
gem5::ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
gem5::X86ISA::MISCREG_DS_BASE
@ MISCREG_DS_BASE
Definition: misc.hh:321
gem5::X86ISA::MISCREG_SEG_BASE_BASE
@ MISCREG_SEG_BASE_BASE
Definition: misc.hh:317
gem5::X86ISA::MISCREG_HS_BASE
@ MISCREG_HS_BASE
Definition: misc.hh:324
gem5::X86ISA::MISCREG_CR2
@ MISCREG_CR2
Definition: misc.hh:113
gem5::X86ISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:462
gem5::X86ISA::MISCREG_CS_BASE
@ MISCREG_CS_BASE
Definition: misc.hh:319
gem5::X86ISA::MISCREG_DR7
@ MISCREG_DR7
Definition: misc.hh:137
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:64
gem5::X86ISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:468
gem5::X86ISA::MISCREG_FOP
@ MISCREG_FOP
Definition: misc.hh:395
gem5::X86ISA::MISCREG_ES_EFF_BASE
@ MISCREG_ES_EFF_BASE
Definition: misc.hh:336
gem5::X86ISA::MISCREG_FOSEG
@ MISCREG_FOSEG
Definition: misc.hh:393
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::X86ISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int miscReg) const
Definition: isa.cc:193
gem5::X86ISA::ProtectedMode
@ ProtectedMode
Definition: types.hh:200
gem5::X86ISA::MISCREG_DR4
@ MISCREG_DR4
Definition: misc.hh:134
gem5::X86ISA::ISA::setThreadContext
void setThreadContext(ThreadContext *_tc) override
Definition: isa.cc:479
gem5::X86ISA::MISCREG_TOP_MEM
@ MISCREG_TOP_MEM
Definition: misc.hh:289
gem5::X86ISA::MISCREG_SS_EFF_BASE
@ MISCREG_SS_EFF_BASE
Definition: misc.hh:338
int.hh
gem5::X86ISA::MISCREG_PAT
@ MISCREG_PAT
Definition: misc.hh:202
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::X86ISA::MISCREG_TSC
@ MISCREG_TSC
Definition: misc.hh:149
gem5::ThreadContext::setCCRegFlat
virtual void setCCRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::setFloatRegFlat
virtual void setFloatRegFlat(RegIndex idx, RegVal val)=0
gem5::X86ISA::MISCREG_DR0
@ MISCREG_DR0
Definition: misc.hh:130
gem5::X86ISA::ISA::clear
void clear()
Definition: isa.cc:110
gem5::X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:115
gem5::BaseISA::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition: isa.hh:68
gem5::X86ISA::MISCREG_CS_ATTR
@ MISCREG_CS_ATTR
Definition: misc.hh:369
gem5::X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:251
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
compiler.hh
gem5::X86ISA::MISCREG_RFLAGS
@ MISCREG_RFLAGS
Definition: misc.hh:140
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::X86ISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:157
gem5::X86ISA::MISCREG_TSL_BASE
@ MISCREG_TSL_BASE
Definition: misc.hh:325
gem5::X86ISA::ISA::readMiscReg
RegVal readMiscReg(int miscReg)
Definition: isa.cc:204
gem5::X86ISA::MISCREG_DR6
@ MISCREG_DR6
Definition: misc.hh:136
gem5::X86ISA::MISCREG_MXCSR
@ MISCREG_MXCSR
Definition: misc.hh:386
gem5::X86ISA::ISA::getVendorString
std::string getVendorString() const
Definition: isa.cc:486
isa.hh
gem5::X86ISA::MISCREG_FCW
@ MISCREG_FCW
Definition: misc.hh:387
gem5::X86ISA::CompatabilityMode
@ CompatabilityMode
Definition: types.hh:199
gem5::X86ISA::MISCREG_CS_EFF_BASE
@ MISCREG_CS_EFF_BASE
Definition: misc.hh:337
gem5::X86ISA::MISCREG_TSG_BASE
@ MISCREG_TSG_BASE
Definition: misc.hh:326
gem5::X86ISA::MISCREG_SS_ATTR
@ MISCREG_SS_ATTR
Definition: misc.hh:370
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::X86ISA::MISCREG_GS_BASE
@ MISCREG_GS_BASE
Definition: misc.hh:323
gem5::X86ISA::MISCREG_SEG_EFF_BASE
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:525
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::ISA::updateHandyM5Reg
void updateHandyM5Reg(Efer efer, CR0 cr0, SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
Definition: isa.cc:49
gem5::X86ISA::MISCREG_CR0
@ MISCREG_CR0
Definition: misc.hh:111
gem5::X86ISA::MISCREG_SYSCFG
@ MISCREG_SYSCFG
Definition: misc.hh:277
gem5::X86ISA::MISCREG_FSW
@ MISCREG_FSW
Definition: misc.hh:388
gem5::BaseMMU::flushAll
virtual void flushAll()
Definition: mmu.cc:51
gem5::X86ISA::RealMode
@ RealMode
Definition: types.hh:202
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::X86ISA::MISCREG_FTW
@ MISCREG_FTW
Definition: misc.hh:389
gem5::BaseISA
Definition: isa.hh:54
gem5::X86ISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int miscReg, RegVal val)
Definition: isa.cc:226
gem5::ThreadContext::readFloatRegFlat
virtual RegVal readFloatRegFlat(RegIndex idx) const =0
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
misc.hh
thread_context.hh
gem5::X86ISA::MISCREG_DR5
@ MISCREG_DR5
Definition: misc.hh:135
gem5::X86ISA::ISA::regVal
RegVal regVal[NUM_MISCREGS]
Definition: isa.hh:53
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::MMU
Definition: mmu.hh:51

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