gem5  v22.0.0.2
fs_workload.cc
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1 /*
2  * Copyright (c) 2007 The Hewlett-Packard Development Company
3  * Copyright (c) 2018 TU Dresden
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38 
39 #include "arch/x86/fs_workload.hh"
40 
41 #include "arch/x86/bios/acpi.hh"
42 #include "arch/x86/bios/intelmp.hh"
43 #include "arch/x86/bios/smbios.hh"
44 #include "arch/x86/faults.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/ACPI.hh"
48 #include "params/X86FsWorkload.hh"
49 #include "sim/system.hh"
50 
51 namespace gem5
52 {
53 
54 namespace X86ISA
55 {
56 
58  smbiosTable(p.smbios_table),
59  mpFloatingPointer(p.intel_mp_pointer),
60  mpConfigTable(p.intel_mp_table),
61  rsdp(p.acpi_description_table_pointer)
62 {}
63 
64 void
65 installSegDesc(ThreadContext *tc, int seg, SegDescriptor desc, bool longmode)
66 {
67  bool honorBase = !longmode || seg == segment_idx::Fs ||
69 
70  SegAttr attr = 0;
71 
72  attr.dpl = desc.dpl;
73  attr.unusable = 0;
74  attr.defaultSize = desc.d;
75  attr.longMode = desc.l;
76  attr.avl = desc.avl;
77  attr.granularity = desc.g;
78  attr.present = desc.p;
79  attr.system = desc.s;
80  attr.type = desc.type;
81  if (desc.s) {
82  if (desc.type.codeOrData) {
83  // Code segment
84  attr.expandDown = 0;
85  attr.readable = desc.type.r;
86  attr.writable = 0;
87  } else {
88  // Data segment
89  attr.expandDown = desc.type.e;
90  attr.readable = 1;
91  attr.writable = desc.type.w;
92  }
93  } else {
94  attr.readable = 1;
95  attr.writable = 1;
96  attr.expandDown = 0;
97  }
98 
99  tc->setMiscReg(misc_reg::segBase(seg), desc.base);
100  tc->setMiscReg(misc_reg::segEffBase(seg), honorBase ? desc.base : 0);
101  tc->setMiscReg(misc_reg::segLimit(seg), desc.limit);
103 }
104 
105 void
107 {
109 
110  for (auto *tc: system->threads) {
112 
113  if (tc->contextId() == 0) {
114  tc->activate();
115  } else {
116  // This is an application processor (AP). It should be initialized
117  // to look like only the BIOS POST has run on it and put then put
118  // it into a halted state.
119  tc->suspend();
120  }
121  }
122 
123  fatal_if(!kernelObj, "No kernel to load.");
124 
126  "Loading a 32 bit x86 kernel is not supported.");
127 
128  ThreadContext *tc = system->threads[0];
129  auto phys_proxy = system->physProxy;
130 
131  // This is the boot strap processor (BSP). Initialize it to look like
132  // the boot loader has just turned control over to the 64 bit OS. We
133  // won't actually set up real mode or legacy protected mode descriptor
134  // tables because we aren't executing any code that would require
135  // them. We do, however toggle the control bits in the correct order
136  // while allowing consistency checks and the underlying mechansims
137  // just to be safe.
138 
139  const int NumPDTs = 4;
140 
141  const Addr PageMapLevel4 = 0x70000;
142  const Addr PageDirPtrTable = 0x71000;
143  const Addr PageDirTable[NumPDTs] =
144  {0x72000, 0x73000, 0x74000, 0x75000};
145  const Addr GDTBase = 0x76000;
146 
147  const int PML4Bits = 9;
148  const int PDPTBits = 9;
149  const int PDTBits = 9;
150 
151  /*
152  * Set up the gdt.
153  */
154  uint8_t numGDTEntries = 0;
155  // Place holder at selector 0
156  uint64_t nullDescriptor = 0;
157  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, &nullDescriptor, 8);
158  numGDTEntries++;
159 
160  SegDescriptor initDesc = 0;
161  initDesc.type.codeOrData = 0; // code or data type
162  initDesc.type.c = 0; // conforming
163  initDesc.type.r = 1; // readable
164  initDesc.dpl = 0; // privilege
165  initDesc.p = 1; // present
166  initDesc.l = 1; // longmode - 64 bit
167  initDesc.d = 0; // operand size
168  initDesc.g = 1; // granularity
169  initDesc.s = 1; // system segment
170  initDesc.limit = 0xFFFFFFFF;
171  initDesc.base = 0;
172 
173  // 64 bit code segment
174  SegDescriptor csDesc = initDesc;
175  csDesc.type.codeOrData = 1;
176  csDesc.dpl = 0;
177  // Because we're dealing with a pointer and I don't think it's
178  // guaranteed that there isn't anything in a nonvirtual class between
179  // it's beginning in memory and it's actual data, we'll use an
180  // intermediary.
181  uint64_t csDescVal = csDesc;
182  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&csDescVal), 8);
183 
184  numGDTEntries++;
185 
186  SegSelector cs = 0;
187  cs.si = numGDTEntries - 1;
188 
189  tc->setMiscReg(misc_reg::Cs, (RegVal)cs);
190 
191  // 32 bit data segment
192  SegDescriptor dsDesc = initDesc;
193  dsDesc.type.e = 0;
194  dsDesc.type.w = 1;
195  dsDesc.d = 1;
196  dsDesc.baseHigh = 0;
197  dsDesc.baseLow = 0;
198 
199  uint64_t dsDescVal = dsDesc;
200  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&dsDescVal), 8);
201 
202  numGDTEntries++;
203 
204  SegSelector ds = 0;
205  ds.si = numGDTEntries - 1;
206 
212 
213  tc->setMiscReg(misc_reg::Tsl, 0);
214  SegAttr ldtAttr = 0;
215  ldtAttr.unusable = 1;
216  tc->setMiscReg(misc_reg::TslAttr, ldtAttr);
217  tc->setMiscReg(misc_reg::TsgBase, GDTBase);
218  tc->setMiscReg(misc_reg::TsgLimit, 8 * numGDTEntries - 1);
219 
220  SegDescriptor tssDesc = initDesc;
221  tssDesc.type = 0xB;
222  tssDesc.s = 0;
223 
224  uint64_t tssDescVal = tssDesc;
225  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&tssDescVal), 8);
226 
227  numGDTEntries++;
228 
229  SegSelector tss = 0;
230  tss.si = numGDTEntries - 1;
231 
232  tc->setMiscReg(misc_reg::Tr, (RegVal)tss);
233  installSegDesc(tc, segment_idx::Tr, tssDesc, true);
234 
235  /*
236  * Identity map the first 4GB of memory. In order to map this region
237  * of memory in long mode, there needs to be one actual page map level
238  * 4 entry which points to one page directory pointer table which
239  * points to 4 different page directory tables which are full of two
240  * megabyte pages. All of the other entries in valid tables are set
241  * to indicate that they don't pertain to anything valid and will
242  * cause a fault if used.
243  */
244 
245  // Put valid values in all of the various table entries which indicate
246  // that those entries don't point to further tables or pages. Then
247  // set the values of those entries which are needed.
248 
249  // Page Map Level 4
250 
251  // read/write, user, not present
252  uint64_t pml4e = htole<uint64_t>(0x6);
253  for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8)
254  phys_proxy.writeBlob(PageMapLevel4 + offset, (&pml4e), 8);
255  // Point to the only PDPT
256  pml4e = htole<uint64_t>(0x7 | PageDirPtrTable);
257  phys_proxy.writeBlob(PageMapLevel4, (&pml4e), 8);
258 
259  // Page Directory Pointer Table
260 
261  // read/write, user, not present
262  uint64_t pdpe = htole<uint64_t>(0x6);
263  for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8)
264  phys_proxy.writeBlob(PageDirPtrTable + offset, &pdpe, 8);
265  // Point to the PDTs
266  for (int table = 0; table < NumPDTs; table++) {
267  pdpe = htole<uint64_t>(0x7 | PageDirTable[table]);
268  phys_proxy.writeBlob(PageDirPtrTable + table * 8, &pdpe, 8);
269  }
270 
271  // Page Directory Tables
272 
273  Addr base = 0;
274  const Addr pageSize = 2 << 20;
275  for (int table = 0; table < NumPDTs; table++) {
276  for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
277  // read/write, user, present, 4MB
278  uint64_t pdte = htole(0x87 | base);
279  phys_proxy.writeBlob(PageDirTable[table] + offset, &pdte, 8);
280  base += pageSize;
281  }
282  }
283 
284  /*
285  * Transition from real mode all the way up to Long mode
286  */
287  CR0 cr0 = tc->readMiscRegNoEffect(misc_reg::Cr0);
288  // Turn off paging.
289  cr0.pg = 0;
290  tc->setMiscReg(misc_reg::Cr0, cr0);
291  // Turn on protected mode.
292  cr0.pe = 1;
293  tc->setMiscReg(misc_reg::Cr0, cr0);
294 
295  CR4 cr4 = tc->readMiscRegNoEffect(misc_reg::Cr4);
296  // Turn on pae.
297  cr4.pae = 1;
298  tc->setMiscReg(misc_reg::Cr4, cr4);
299 
300  // Point to the page tables.
301  tc->setMiscReg(misc_reg::Cr3, PageMapLevel4);
302 
304  // Enable long mode.
305  efer.lme = 1;
306  tc->setMiscReg(misc_reg::Efer, efer);
307 
308  // Start using longmode segments.
309  installSegDesc(tc, segment_idx::Cs, csDesc, true);
310  installSegDesc(tc, segment_idx::Ds, dsDesc, true);
311  installSegDesc(tc, segment_idx::Es, dsDesc, true);
312  installSegDesc(tc, segment_idx::Fs, dsDesc, true);
313  installSegDesc(tc, segment_idx::Gs, dsDesc, true);
314  installSegDesc(tc, segment_idx::Ss, dsDesc, true);
315 
316  // Activate long mode.
317  cr0.pg = 1;
318  tc->setMiscReg(misc_reg::Cr0, cr0);
319 
320  tc->pcState(kernelObj->entryPoint());
321 
322  // We should now be in long mode. Yay!
323 
324  Addr ebdaPos = 0xF0000;
325  Addr fixed, table;
326 
327  // Write out the SMBios/DMI table.
328  writeOutSMBiosTable(ebdaPos, fixed, table);
329  ebdaPos += (fixed + table);
330  ebdaPos = roundUp(ebdaPos, 16);
331 
332  // Write out the Intel MP Specification configuration table.
333  writeOutMPTable(ebdaPos, fixed, table);
334  ebdaPos += (fixed + table);
335 
336  // Write out ACPI tables
337  writeOutACPITables(ebdaPos, table);
338  ebdaPos += table;
339 }
340 
341 void
343  Addr &headerSize, Addr &structSize, Addr table)
344 {
345  // If the table location isn't specified, just put it after the header.
346  // The header size as of the 2.5 SMBios specification is 0x1F bytes.
347  if (!table)
348  table = header + 0x1F;
349  smbiosTable->setTableAddr(table);
350 
351  smbiosTable->writeOut(system->physProxy, header, headerSize, structSize);
352 
353  // Do some bounds checking to make sure we at least didn't step on
354  // ourselves.
355  assert(header > table || header + headerSize <= table);
356  assert(table > header || table + structSize <= header);
357 }
358 
359 void
360 FsWorkload::writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table)
361 {
362  // If the table location isn't specified and it exists, just put
363  // it after the floating pointer. The fp size as of the 1.4 Intel MP
364  // specification is 0x10 bytes.
365  if (mpConfigTable) {
366  if (!table)
367  table = fp + 0x10;
369  }
370 
372  if (mpConfigTable)
373  tableSize = mpConfigTable->writeOut(system->physProxy, table);
374  else
375  tableSize = 0;
376 
377  // Do some bounds checking to make sure we at least didn't step on
378  // ourselves and the fp structure was the size we thought it was.
379  assert(fp > table || fp + fpSize <= table);
380  assert(table > fp || table + tableSize <= fp);
381  assert(fpSize == 0x10);
382 }
383 
384 void
386 {
387  fpSize = 0;
388  if (rsdp) {
389  ACPI::LinearAllocator alloc(fp, 0x000FFFFF);
390  rsdp->write(system->physProxy, alloc);
391  fpSize = alloc.alloc(0, 0) - fp;
392  DPRINTF(ACPI, "Wrote ACPI tables to memory at %llx with size %llx.\n",
393  fp, fpSize);
394  }
395 }
396 
397 } // namespace X86ISA
398 } // namespace gem5
gem5::X86ISA::FsWorkload::writeOutSMBiosTable
void writeOutSMBiosTable(Addr header, Addr &headerSize, Addr &tableSize, Addr table=0)
Definition: fs_workload.cc:342
gem5::X86ISA::misc_reg::TslAttr
@ TslAttr
Definition: misc.hh:378
gem5::PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:192
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
system.hh
gem5::X86ISA::segment_idx::Ds
@ Ds
Definition: segment.hh:53
gem5::loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:137
gem5::X86ISA::ACPI::LinearAllocator::alloc
Addr alloc(std::size_t size, unsigned align) override
Definition: acpi.cc:91
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:327
gem5::ArmISA::attr
attr
Definition: misc_types.hh:656
intelmp.hh
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::misc_reg::Ss
@ Ss
Definition: misc.hh:307
gem5::X86ISA::FsWorkload::writeOutACPITables
void writeOutACPITables(Addr begin, Addr &size)
Definition: fs_workload.cc:385
gem5::X86ISA::FsWorkload::FsWorkload
FsWorkload(const Params &p)
Definition: fs_workload.cc:57
gem5::X86ISA::offset
offset
Definition: misc.hh:1024
gem5::X86ISA::InitInterrupt
Definition: faults.hh:349
gem5::X86ISA::misc_reg::Tr
@ Tr
Definition: misc.hh:316
gem5::X86ISA::FsWorkload::mpConfigTable
intelmp::ConfigTable * mpConfigTable
Definition: fs_workload.hh:100
gem5::X86ISA::misc_reg::segEffBase
static RegIndex segEffBase(int index)
Definition: misc.hh:517
header
output header
Definition: nop.cc:36
gem5::X86ISA::FsWorkload::rsdp
ACPI::RSDP * rsdp
Definition: fs_workload.hh:101
gem5::X86ISA::misc_reg::segAttr
static RegIndex segAttr(int index)
Definition: misc.hh:531
acpi.hh
gem5::X86ISA::InitInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:182
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
faults.hh
gem5::ArmISA::fp
Bitfield< 19, 16 > fp
Definition: misc_types.hh:177
gem5::KernelWorkload::kernelObj
loader::ObjectFile * kernelObj
Definition: kernel_workload.hh:69
gem5::X86ISA::segment_idx::Cs
@ Cs
Definition: segment.hh:51
gem5::X86ISA::intelmp::ConfigTable::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:186
gem5::X86ISA::FsWorkload::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: fs_workload.cc:106
gem5::X86ISA::smbios::SMBiosTable::writeOut
void writeOut(PortProxy &proxy, Addr addr, Addr &headerSize, Addr &structSize)
Definition: smbios.cc:217
gem5::X86ISA::misc_reg::TsgBase
@ TsgBase
Definition: misc.hh:329
gem5::X86ISA::misc_reg::segBase
static RegIndex segBase(int index)
Definition: misc.hh:510
gem5::KernelWorkload
Definition: kernel_workload.hh:45
gem5::X86ISA::ACPI::RSDP::write
Addr write(PortProxy &phys_proxy, Allocator &alloc) const
Definition: acpi.cc:111
smbios.hh
gem5::X86ISA::FsWorkload::smbiosTable
smbios::SMBiosTable * smbiosTable
Definition: fs_workload.hh:98
gem5::X86ISA::misc_reg::Cr0
@ Cr0
Definition: misc.hh:114
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::smbios::SMBiosTable::setTableAddr
void setTableAddr(Addr addr)
Definition: smbios.hh:224
gem5::X86ISA::FsWorkload::mpFloatingPointer
intelmp::FloatingPointer * mpFloatingPointer
Definition: fs_workload.hh:99
gem5::X86ISA::segment_idx::Gs
@ Gs
Definition: segment.hh:55
gem5::X86ISA::segment_idx::Es
@ Es
Definition: segment.hh:50
gem5::X86ISA::intelmp::FloatingPointer::setTableAddr
void setTableAddr(Addr addr)
Definition: intelmp.hh:112
gem5::X86ISA::ACPI::LinearAllocator
Definition: acpi.hh:80
gem5::loader::ObjectFile::getArch
Arch getArch() const
Definition: object_file.hh:127
gem5::X86ISA::segment_idx::Tr
@ Tr
Definition: segment.hh:64
gem5::X86ISA::FsWorkload::writeOutMPTable
void writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table=0)
Definition: fs_workload.cc:360
gem5::X86ISA::misc_reg::Ds
@ Ds
Definition: misc.hh:308
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::X86ISA::misc_reg::Tsl
@ Tsl
Definition: misc.hh:312
gem5::X86ISA::misc_reg::Cr3
@ Cr3
Definition: misc.hh:117
gem5::X86ISA::segment_idx::Ss
@ Ss
Definition: segment.hh:52
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::misc_reg::Cr4
@ Cr4
Definition: misc.hh:118
gem5::X86ISA::misc_reg::Cs
@ Cs
Definition: misc.hh:306
gem5::MipsISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:238
gem5::X86ISA::misc_reg::TsgLimit
@ TsgLimit
Definition: misc.hh:363
gem5::X86ISA::misc_reg::Gs
@ Gs
Definition: misc.hh:310
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::X86ISA::segment_idx::Fs
@ Fs
Definition: segment.hh:54
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
gem5::loader::I386
@ I386
Definition: object_file.hh:69
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::Workload::system
System * system
Definition: workload.hh:80
gem5::X86ISA::FsWorkload::Params
X86FsWorkloadParams Params
Definition: fs_workload.hh:81
gem5::X86ISA::misc_reg::Es
@ Es
Definition: misc.hh:305
fs_workload.hh
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::misc_reg::Efer
@ Efer
Definition: misc.hh:254
gem5::X86ISA::installSegDesc
void installSegDesc(ThreadContext *tc, int seg, SegDescriptor desc, bool longmode)
Definition: fs_workload.cc:65
object_file.hh
gem5::X86ISA::misc_reg::segLimit
static RegIndex segLimit(int index)
Definition: misc.hh:524
thread_context.hh
gem5::X86ISA::misc_reg::Fs
@ Fs
Definition: misc.hh:309
gem5::X86ISA::intelmp::FloatingPointer::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:109
gem5::KernelWorkload::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: kernel_workload.cc:96

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