gem5  v21.1.0.2
fs_workload.cc
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1 /*
2  * Copyright (c) 2007 The Hewlett-Packard Development Company
3  * Copyright (c) 2018 TU Dresden
4  * All rights reserved.
5  *
6  * The license below extends only to copyright in the software and shall
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38 
39 #include "arch/x86/fs_workload.hh"
40 
41 #include "arch/x86/bios/acpi.hh"
42 #include "arch/x86/bios/intelmp.hh"
43 #include "arch/x86/bios/smbios.hh"
44 #include "arch/x86/faults.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/ACPI.hh"
48 #include "params/X86FsWorkload.hh"
49 #include "sim/system.hh"
50 
51 namespace gem5
52 {
53 
54 namespace X86ISA
55 {
56 
58  smbiosTable(p.smbios_table),
59  mpFloatingPointer(p.intel_mp_pointer),
60  mpConfigTable(p.intel_mp_table),
61  rsdp(p.acpi_description_table_pointer)
62 {}
63 
64 void
66  SegDescriptor desc, bool longmode)
67 {
68  bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
69  seg == SEGMENT_REG_GS ||
70  seg == SEGMENT_REG_TSL ||
72 
73  SegAttr attr = 0;
74 
75  attr.dpl = desc.dpl;
76  attr.unusable = 0;
77  attr.defaultSize = desc.d;
78  attr.longMode = desc.l;
79  attr.avl = desc.avl;
80  attr.granularity = desc.g;
81  attr.present = desc.p;
82  attr.system = desc.s;
83  attr.type = desc.type;
84  if (desc.s) {
85  if (desc.type.codeOrData) {
86  // Code segment
87  attr.expandDown = 0;
88  attr.readable = desc.type.r;
89  attr.writable = 0;
90  } else {
91  // Data segment
92  attr.expandDown = desc.type.e;
93  attr.readable = 1;
94  attr.writable = desc.type.w;
95  }
96  } else {
97  attr.readable = 1;
98  attr.writable = 1;
99  attr.expandDown = 0;
100  }
101 
102  tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
103  tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
104  tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit);
106 }
107 
108 void
110 {
112 
113  for (auto *tc: system->threads) {
115 
116  if (tc->contextId() == 0) {
117  tc->activate();
118  } else {
119  // This is an application processor (AP). It should be initialized
120  // to look like only the BIOS POST has run on it and put then put
121  // it into a halted state.
122  tc->suspend();
123  }
124  }
125 
126  fatal_if(!kernelObj, "No kernel to load.");
127 
129  "Loading a 32 bit x86 kernel is not supported.");
130 
131  ThreadContext *tc = system->threads[0];
132  auto phys_proxy = system->physProxy;
133 
134  // This is the boot strap processor (BSP). Initialize it to look like
135  // the boot loader has just turned control over to the 64 bit OS. We
136  // won't actually set up real mode or legacy protected mode descriptor
137  // tables because we aren't executing any code that would require
138  // them. We do, however toggle the control bits in the correct order
139  // while allowing consistency checks and the underlying mechansims
140  // just to be safe.
141 
142  const int NumPDTs = 4;
143 
144  const Addr PageMapLevel4 = 0x70000;
145  const Addr PageDirPtrTable = 0x71000;
146  const Addr PageDirTable[NumPDTs] =
147  {0x72000, 0x73000, 0x74000, 0x75000};
148  const Addr GDTBase = 0x76000;
149 
150  const int PML4Bits = 9;
151  const int PDPTBits = 9;
152  const int PDTBits = 9;
153 
154  /*
155  * Set up the gdt.
156  */
157  uint8_t numGDTEntries = 0;
158  // Place holder at selector 0
159  uint64_t nullDescriptor = 0;
160  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, &nullDescriptor, 8);
161  numGDTEntries++;
162 
163  SegDescriptor initDesc = 0;
164  initDesc.type.codeOrData = 0; // code or data type
165  initDesc.type.c = 0; // conforming
166  initDesc.type.r = 1; // readable
167  initDesc.dpl = 0; // privilege
168  initDesc.p = 1; // present
169  initDesc.l = 1; // longmode - 64 bit
170  initDesc.d = 0; // operand size
171  initDesc.g = 1; // granularity
172  initDesc.s = 1; // system segment
173  initDesc.limit = 0xFFFFFFFF;
174  initDesc.base = 0;
175 
176  // 64 bit code segment
177  SegDescriptor csDesc = initDesc;
178  csDesc.type.codeOrData = 1;
179  csDesc.dpl = 0;
180  // Because we're dealing with a pointer and I don't think it's
181  // guaranteed that there isn't anything in a nonvirtual class between
182  // it's beginning in memory and it's actual data, we'll use an
183  // intermediary.
184  uint64_t csDescVal = csDesc;
185  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&csDescVal), 8);
186 
187  numGDTEntries++;
188 
189  SegSelector cs = 0;
190  cs.si = numGDTEntries - 1;
191 
192  tc->setMiscReg(MISCREG_CS, (RegVal)cs);
193 
194  // 32 bit data segment
195  SegDescriptor dsDesc = initDesc;
196  dsDesc.type.e = 0;
197  dsDesc.type.w = 1;
198  dsDesc.d = 1;
199  dsDesc.baseHigh = 0;
200  dsDesc.baseLow = 0;
201 
202  uint64_t dsDescVal = dsDesc;
203  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&dsDescVal), 8);
204 
205  numGDTEntries++;
206 
207  SegSelector ds = 0;
208  ds.si = numGDTEntries - 1;
209 
215 
216  tc->setMiscReg(MISCREG_TSL, 0);
217  SegAttr ldtAttr = 0;
218  ldtAttr.unusable = 1;
219  tc->setMiscReg(MISCREG_TSL_ATTR, ldtAttr);
220  tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
221  tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
222 
223  SegDescriptor tssDesc = initDesc;
224  tssDesc.type = 0xB;
225  tssDesc.s = 0;
226 
227  uint64_t tssDescVal = tssDesc;
228  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&tssDescVal), 8);
229 
230  numGDTEntries++;
231 
232  SegSelector tss = 0;
233  tss.si = numGDTEntries - 1;
234 
235  tc->setMiscReg(MISCREG_TR, (RegVal)tss);
236  installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
237 
238  /*
239  * Identity map the first 4GB of memory. In order to map this region
240  * of memory in long mode, there needs to be one actual page map level
241  * 4 entry which points to one page directory pointer table which
242  * points to 4 different page directory tables which are full of two
243  * megabyte pages. All of the other entries in valid tables are set
244  * to indicate that they don't pertain to anything valid and will
245  * cause a fault if used.
246  */
247 
248  // Put valid values in all of the various table entries which indicate
249  // that those entries don't point to further tables or pages. Then
250  // set the values of those entries which are needed.
251 
252  // Page Map Level 4
253 
254  // read/write, user, not present
255  uint64_t pml4e = htole<uint64_t>(0x6);
256  for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8)
257  phys_proxy.writeBlob(PageMapLevel4 + offset, (&pml4e), 8);
258  // Point to the only PDPT
259  pml4e = htole<uint64_t>(0x7 | PageDirPtrTable);
260  phys_proxy.writeBlob(PageMapLevel4, (&pml4e), 8);
261 
262  // Page Directory Pointer Table
263 
264  // read/write, user, not present
265  uint64_t pdpe = htole<uint64_t>(0x6);
266  for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8)
267  phys_proxy.writeBlob(PageDirPtrTable + offset, &pdpe, 8);
268  // Point to the PDTs
269  for (int table = 0; table < NumPDTs; table++) {
270  pdpe = htole<uint64_t>(0x7 | PageDirTable[table]);
271  phys_proxy.writeBlob(PageDirPtrTable + table * 8, &pdpe, 8);
272  }
273 
274  // Page Directory Tables
275 
276  Addr base = 0;
277  const Addr pageSize = 2 << 20;
278  for (int table = 0; table < NumPDTs; table++) {
279  for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
280  // read/write, user, present, 4MB
281  uint64_t pdte = htole(0x87 | base);
282  phys_proxy.writeBlob(PageDirTable[table] + offset, &pdte, 8);
283  base += pageSize;
284  }
285  }
286 
287  /*
288  * Transition from real mode all the way up to Long mode
289  */
290  CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
291  // Turn off paging.
292  cr0.pg = 0;
293  tc->setMiscReg(MISCREG_CR0, cr0);
294  // Turn on protected mode.
295  cr0.pe = 1;
296  tc->setMiscReg(MISCREG_CR0, cr0);
297 
298  CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
299  // Turn on pae.
300  cr4.pae = 1;
301  tc->setMiscReg(MISCREG_CR4, cr4);
302 
303  // Point to the page tables.
304  tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
305 
306  Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
307  // Enable long mode.
308  efer.lme = 1;
309  tc->setMiscReg(MISCREG_EFER, efer);
310 
311  // Start using longmode segments.
312  installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
313  installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
314  installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
315  installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
316  installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
317  installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
318 
319  // Activate long mode.
320  cr0.pg = 1;
321  tc->setMiscReg(MISCREG_CR0, cr0);
322 
323  tc->pcState(kernelObj->entryPoint());
324 
325  // We should now be in long mode. Yay!
326 
327  Addr ebdaPos = 0xF0000;
328  Addr fixed, table;
329 
330  // Write out the SMBios/DMI table.
331  writeOutSMBiosTable(ebdaPos, fixed, table);
332  ebdaPos += (fixed + table);
333  ebdaPos = roundUp(ebdaPos, 16);
334 
335  // Write out the Intel MP Specification configuration table.
336  writeOutMPTable(ebdaPos, fixed, table);
337  ebdaPos += (fixed + table);
338 
339  // Write out ACPI tables
340  writeOutACPITables(ebdaPos, table);
341  ebdaPos += table;
342 }
343 
344 void
346  Addr &headerSize, Addr &structSize, Addr table)
347 {
348  // If the table location isn't specified, just put it after the header.
349  // The header size as of the 2.5 SMBios specification is 0x1F bytes.
350  if (!table)
351  table = header + 0x1F;
352  smbiosTable->setTableAddr(table);
353 
354  smbiosTable->writeOut(system->physProxy, header, headerSize, structSize);
355 
356  // Do some bounds checking to make sure we at least didn't step on
357  // ourselves.
358  assert(header > table || header + headerSize <= table);
359  assert(table > header || table + structSize <= header);
360 }
361 
362 void
363 FsWorkload::writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table)
364 {
365  // If the table location isn't specified and it exists, just put
366  // it after the floating pointer. The fp size as of the 1.4 Intel MP
367  // specification is 0x10 bytes.
368  if (mpConfigTable) {
369  if (!table)
370  table = fp + 0x10;
372  }
373 
375  if (mpConfigTable)
376  tableSize = mpConfigTable->writeOut(system->physProxy, table);
377  else
378  tableSize = 0;
379 
380  // Do some bounds checking to make sure we at least didn't step on
381  // ourselves and the fp structure was the size we thought it was.
382  assert(fp > table || fp + fpSize <= table);
383  assert(table > fp || table + tableSize <= fp);
384  assert(fpSize == 0x10);
385 }
386 
387 void
389 {
390  fpSize = 0;
391  if (rsdp) {
392  ACPI::LinearAllocator alloc(fp, 0x000FFFFF);
393  rsdp->write(system->physProxy, alloc);
394  fpSize = alloc.alloc(0, 0) - fp;
395  DPRINTF(ACPI, "Wrote ACPI tables to memory at %llx with size %llx.\n",
396  fp, fpSize);
397  }
398 }
399 
400 } // namespace X86ISA
401 } // namespace gem5
gem5::X86ISA::installSegDesc
void installSegDesc(ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode)
Definition: fs_workload.cc:65
gem5::X86ISA::MISCREG_ES
@ MISCREG_ES
Definition: misc.hh:302
gem5::X86ISA::FsWorkload::writeOutSMBiosTable
void writeOutSMBiosTable(Addr header, Addr &headerSize, Addr &tableSize, Addr table=0)
Definition: fs_workload.cc:345
gem5::X86ISA::SEGMENT_REG_ES
@ SEGMENT_REG_ES
Definition: segment.hh:48
gem5::X86ISA::MISCREG_DS
@ MISCREG_DS
Definition: misc.hh:305
gem5::PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:192
gem5::X86ISA::MISCREG_TR
@ MISCREG_TR
Definition: misc.hh:313
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
system.hh
gem5::loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:125
gem5::X86ISA::MISCREG_TSL
@ MISCREG_TSL
Definition: misc.hh:309
gem5::X86ISA::ACPI::LinearAllocator::alloc
Addr alloc(std::size_t size, unsigned align) override
Definition: acpi.cc:91
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:332
gem5::X86ISA::MISCREG_TSG_LIMIT
@ MISCREG_TSG_LIMIT
Definition: misc.hh:360
gem5::ArmISA::attr
attr
Definition: misc_types.hh:655
gem5::X86ISA::MISCREG_SEG_LIMIT
static MiscRegIndex MISCREG_SEG_LIMIT(int index)
Definition: misc.hh:532
intelmp.hh
gem5::X86ISA::FsWorkload::writeOutACPITables
void writeOutACPITables(Addr begin, Addr &size)
Definition: fs_workload.cc:388
gem5::X86ISA::MISCREG_SEG_ATTR
static MiscRegIndex MISCREG_SEG_ATTR(int index)
Definition: misc.hh:539
gem5::X86ISA::FsWorkload::FsWorkload
FsWorkload(const Params &p)
Definition: fs_workload.cc:57
gem5::X86ISA::offset
offset
Definition: misc.hh:1030
gem5::X86ISA::InitInterrupt
Definition: faults.hh:350
gem5::X86ISA::SegmentRegIndex
SegmentRegIndex
Definition: segment.hh:46
gem5::X86ISA::SYS_SEGMENT_REG_TR
@ SYS_SEGMENT_REG_TR
Definition: segment.hh:62
gem5::X86ISA::FsWorkload::mpConfigTable
intelmp::ConfigTable * mpConfigTable
Definition: fs_workload.hh:98
header
output header
Definition: nop.cc:36
gem5::X86ISA::FsWorkload::rsdp
ACPI::RSDP * rsdp
Definition: fs_workload.hh:99
acpi.hh
gem5::X86ISA::InitInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:187
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
faults.hh
gem5::ArmISA::fp
Bitfield< 19, 16 > fp
Definition: misc_types.hh:176
gem5::KernelWorkload::kernelObj
loader::ObjectFile * kernelObj
Definition: kernel_workload.hh:69
gem5::X86ISA::MISCREG_GS
@ MISCREG_GS
Definition: misc.hh:307
gem5::X86ISA::SEGMENT_REG_CS
@ SEGMENT_REG_CS
Definition: segment.hh:49
gem5::X86ISA::intelmp::ConfigTable::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:186
gem5::X86ISA::FsWorkload::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: fs_workload.cc:109
gem5::X86ISA::smbios::SMBiosTable::writeOut
void writeOut(PortProxy &proxy, Addr addr, Addr &headerSize, Addr &structSize)
Definition: smbios.cc:217
gem5::X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:114
gem5::KernelWorkload
Definition: kernel_workload.hh:45
gem5::X86ISA::ACPI::RSDP::write
Addr write(PortProxy &phys_proxy, Allocator &alloc) const
Definition: acpi.cc:111
smbios.hh
gem5::X86ISA::FsWorkload::smbiosTable
smbios::SMBiosTable * smbiosTable
Definition: fs_workload.hh:96
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::X86ISA::SEGMENT_REG_GS
@ SEGMENT_REG_GS
Definition: segment.hh:53
gem5::X86ISA::SEGMENT_REG_TSL
@ SEGMENT_REG_TSL
Definition: segment.hh:55
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::smbios::SMBiosTable::setTableAddr
void setTableAddr(Addr addr)
Definition: smbios.hh:224
gem5::X86ISA::FsWorkload::mpFloatingPointer
intelmp::FloatingPointer * mpFloatingPointer
Definition: fs_workload.hh:97
gem5::X86ISA::intelmp::FloatingPointer::setTableAddr
void setTableAddr(Addr addr)
Definition: intelmp.hh:112
gem5::X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:115
gem5::X86ISA::ACPI::LinearAllocator
Definition: acpi.hh:80
gem5::X86ISA::SEGMENT_REG_DS
@ SEGMENT_REG_DS
Definition: segment.hh:51
gem5::X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:251
gem5::X86ISA::SEGMENT_REG_SS
@ SEGMENT_REG_SS
Definition: segment.hh:50
gem5::loader::ObjectFile::getArch
Arch getArch() const
Definition: object_file.hh:115
gem5::X86ISA::MISCREG_SEG_BASE
static MiscRegIndex MISCREG_SEG_BASE(int index)
Definition: misc.hh:518
gem5::X86ISA::FsWorkload::writeOutMPTable
void writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table=0)
Definition: fs_workload.cc:363
gem5::X86ISA::MISCREG_FS
@ MISCREG_FS
Definition: misc.hh:306
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::X86ISA::MISCREG_TSL_ATTR
@ MISCREG_TSL_ATTR
Definition: misc.hh:375
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::MISCREG_SS
@ MISCREG_SS
Definition: misc.hh:304
gem5::MipsISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:238
gem5::X86ISA::MISCREG_CS
@ MISCREG_CS
Definition: misc.hh:303
gem5::X86ISA::MISCREG_TSG_BASE
@ MISCREG_TSG_BASE
Definition: misc.hh:326
gem5::X86ISA::SEGMENT_REG_FS
@ SEGMENT_REG_FS
Definition: segment.hh:52
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::X86ISA::MISCREG_SEG_EFF_BASE
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:525
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::X86ISA::MISCREG_CR0
@ MISCREG_CR0
Definition: misc.hh:111
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
gem5::loader::I386
@ I386
Definition: object_file.hh:57
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::Workload::system
System * system
Definition: workload.hh:78
gem5::X86ISA::FsWorkload::Params
X86FsWorkloadParams Params
Definition: fs_workload.hh:81
fs_workload.hh
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
object_file.hh
thread_context.hh
gem5::X86ISA::intelmp::FloatingPointer::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:109
gem5::KernelWorkload::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: kernel_workload.cc:96

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