gem5  v22.0.0.2
tlb.cc
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37 
38 #include "arch/x86/tlb.hh"
39 
40 #include <cstring>
41 #include <memory>
42 
43 #include "arch/x86/faults.hh"
47 #include "arch/x86/regs/misc.hh"
48 #include "arch/x86/regs/msr.hh"
49 #include "arch/x86/x86_traits.hh"
50 #include "base/trace.hh"
51 #include "cpu/thread_context.hh"
52 #include "debug/TLB.hh"
53 #include "mem/packet_access.hh"
54 #include "mem/page_table.hh"
55 #include "mem/request.hh"
56 #include "sim/full_system.hh"
57 #include "sim/process.hh"
58 #include "sim/pseudo_inst.hh"
59 
60 namespace gem5
61 {
62 
63 namespace X86ISA {
64 
65 TLB::TLB(const Params &p)
66  : BaseTLB(p), configAddress(0), size(p.size),
67  tlb(size), lruSeq(0), m5opRange(p.system->m5opRange()), stats(this)
68 {
69  if (!size)
70  fatal("TLBs must have a non-zero size.\n");
71 
72  for (int x = 0; x < size; x++) {
73  tlb[x].trieHandle = NULL;
74  freeList.push_back(&tlb[x]);
75  }
76 
77  walker = p.walker;
78  walker->setTLB(this);
79 }
80 
81 void
83 {
84  // Find the entry with the lowest (and hence least recently updated)
85  // sequence number.
86 
87  unsigned lru = 0;
88  for (unsigned i = 1; i < size; i++) {
89  if (tlb[i].lruSeq < tlb[lru].lruSeq)
90  lru = i;
91  }
92 
93  assert(tlb[lru].trieHandle);
94  trie.remove(tlb[lru].trieHandle);
95  tlb[lru].trieHandle = NULL;
96  freeList.push_back(&tlb[lru]);
97 }
98 
99 TlbEntry *
100 TLB::insert(Addr vpn, const TlbEntry &entry)
101 {
102  // If somebody beat us to it, just use that existing entry.
103  TlbEntry *newEntry = trie.lookup(vpn);
104  if (newEntry) {
105  assert(newEntry->vaddr == vpn);
106  return newEntry;
107  }
108 
109  if (freeList.empty())
110  evictLRU();
111 
112  newEntry = freeList.front();
113  freeList.pop_front();
114 
115  *newEntry = entry;
116  newEntry->lruSeq = nextSeq();
117  newEntry->vaddr = vpn;
118  newEntry->trieHandle =
119  trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
120  return newEntry;
121 }
122 
123 TlbEntry *
124 TLB::lookup(Addr va, bool update_lru)
125 {
126  TlbEntry *entry = trie.lookup(va);
127  if (entry && update_lru)
128  entry->lruSeq = nextSeq();
129  return entry;
130 }
131 
132 void
134 {
135  DPRINTF(TLB, "Invalidating all entries.\n");
136  for (unsigned i = 0; i < size; i++) {
137  if (tlb[i].trieHandle) {
138  trie.remove(tlb[i].trieHandle);
139  tlb[i].trieHandle = NULL;
140  freeList.push_back(&tlb[i]);
141  }
142  }
143 }
144 
145 void
147 {
149 }
150 
151 void
153 {
154  DPRINTF(TLB, "Invalidating all non global entries.\n");
155  for (unsigned i = 0; i < size; i++) {
156  if (tlb[i].trieHandle && !tlb[i].global) {
157  trie.remove(tlb[i].trieHandle);
158  tlb[i].trieHandle = NULL;
159  freeList.push_back(&tlb[i]);
160  }
161  }
162 }
163 
164 void
165 TLB::demapPage(Addr va, uint64_t asn)
166 {
167  TlbEntry *entry = trie.lookup(va);
168  if (entry) {
169  trie.remove(entry->trieHandle);
170  entry->trieHandle = NULL;
171  freeList.push_back(entry);
172  }
173 }
174 
175 namespace
176 {
177 
178 Cycles
179 localMiscRegAccess(bool read, RegIndex regNum,
180  ThreadContext *tc, PacketPtr pkt)
181 {
182  if (read) {
183  RegVal data = htole(tc->readMiscReg(regNum));
184  assert(pkt->getSize() <= sizeof(RegVal));
185  pkt->setData((uint8_t *)&data);
186  } else {
187  RegVal data = htole(tc->readMiscRegNoEffect(regNum));
188  assert(pkt->getSize() <= sizeof(RegVal));
189  pkt->writeData((uint8_t *)&data);
190  tc->setMiscReg(regNum, letoh(data));
191  }
192  return Cycles(1);
193 }
194 
195 } // anonymous namespace
196 
197 Fault
199 {
200  DPRINTF(TLB, "Addresses references internal memory.\n");
201  Addr vaddr = req->getVaddr();
202  Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
203  if (prefix == IntAddrPrefixCPUID) {
204  panic("CPUID memory space not yet implemented!\n");
205  } else if (prefix == IntAddrPrefixMSR) {
206  vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
207 
208  RegIndex regNum;
209  if (!msrAddrToIndex(regNum, vaddr))
210  return std::make_shared<GeneralProtection>(0);
211 
212  req->setPaddr(req->getVaddr());
213  req->setLocalAccessor(
214  [read,regNum](ThreadContext *tc, PacketPtr pkt)
215  {
216  return localMiscRegAccess(read, regNum, tc, pkt);
217  }
218  );
219 
220  return NoFault;
221  } else if (prefix == IntAddrPrefixIO) {
222  // TODO If CPL > IOPL or in virtual mode, check the I/O permission
223  // bitmap in the TSS.
224 
225  Addr IOPort = vaddr & ~IntAddrPrefixMask;
226  // Make sure the address fits in the expected 16 bit IO address
227  // space.
228  assert(!(IOPort & ~0xFFFF));
229  if (IOPort == 0xCF8 && req->getSize() == 4) {
230  req->setPaddr(req->getVaddr());
231  req->setLocalAccessor(
232  [read](ThreadContext *tc, PacketPtr pkt)
233  {
234  return localMiscRegAccess(
235  read, misc_reg::PciConfigAddress, tc, pkt);
236  }
237  );
238  } else if ((IOPort & ~mask(2)) == 0xCFC) {
242  if (bits(configAddress, 31, 31)) {
243  req->setPaddr(PhysAddrPrefixPciConfig |
244  mbits(configAddress, 30, 2) |
245  (IOPort & mask(2)));
246  } else {
247  req->setPaddr(PhysAddrPrefixIO | IOPort);
248  }
249  } else {
251  req->setPaddr(PhysAddrPrefixIO | IOPort);
252  }
253  return NoFault;
254  } else {
255  panic("Access to unrecognized internal address space %#x.\n",
256  prefix);
257  }
258 }
259 
260 Fault
262  ThreadContext *tc, BaseMMU::Mode mode) const
263 {
264  Addr paddr = req->getPaddr();
265 
266  if (m5opRange.contains(paddr)) {
267  req->setFlags(Request::STRICT_ORDER);
268  uint8_t func;
270  req->setLocalAccessor(
271  [func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
272  {
273  uint64_t ret;
274  pseudo_inst::pseudoInst<X86PseudoInstABI, true>(tc, func, ret);
275  if (mode == BaseMMU::Read)
276  pkt->setLE(ret);
277  return Cycles(1);
278  }
279  );
280  } else if (FullSystem) {
281  // Check for an access to the local APIC
282  LocalApicBase localApicBase =
284  AddrRange apicRange(localApicBase.base * PageBytes,
285  (localApicBase.base + 1) * PageBytes);
286 
287  if (apicRange.contains(paddr)) {
288  // The Intel developer's manuals say the below restrictions apply,
289  // but the linux kernel, because of a compiler optimization, breaks
290  // them.
291  /*
292  // Check alignment
293  if (paddr & ((32/8) - 1))
294  return new GeneralProtection(0);
295  // Check access size
296  if (req->getSize() != (32/8))
297  return new GeneralProtection(0);
298  */
299  // Force the access to be uncacheable.
301  req->setPaddr(x86LocalAPICAddress(tc->contextId(),
302  paddr - apicRange.start()));
303  }
304  }
305 
306  return NoFault;
307 }
308 
309 Fault
311  ThreadContext *tc, BaseMMU::Translation *translation,
312  BaseMMU::Mode mode, bool &delayedResponse, bool timing)
313 {
314  Request::Flags flags = req->getFlags();
315  int seg = flags & SegmentFlagMask;
316  bool storeCheck = flags & Request::READ_MODIFY_WRITE;
317 
318  delayedResponse = false;
319 
320  // If this is true, we're dealing with a request to a non-memory address
321  // space.
322  if (seg == segment_idx::Ms) {
323  return translateInt(mode == BaseMMU::Read, req, tc);
324  }
325 
326  Addr vaddr = req->getVaddr();
327  DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
328 
329  HandyM5Reg m5Reg = tc->readMiscRegNoEffect(misc_reg::M5Reg);
330 
331  const Addr logAddrSize = (flags >> AddrSizeFlagShift) & AddrSizeFlagMask;
332  const int addrSize = 8 << logAddrSize;
333  const Addr addrMask = mask(addrSize);
334 
335  // If protected mode has been enabled...
336  if (m5Reg.prot) {
337  DPRINTF(TLB, "In protected mode.\n");
338  // If we're not in 64-bit mode, do protection/limit checks
339  if (m5Reg.mode != LongMode) {
340  DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
341 
342  // CPUs won't know to use CS when building fetch requests, so we
343  // need to override the value of "seg" here if this is a fetch.
344  if (mode == BaseMMU::Execute)
346 
348  // Check for an unusable segment.
349  if (attr.unusable) {
350  DPRINTF(TLB, "Unusable segment.\n");
351  return std::make_shared<GeneralProtection>(0);
352  }
353  bool expandDown = false;
354  if (seg >= segment_idx::Es && seg <= segment_idx::Hs) {
355  if (!attr.writable && (mode == BaseMMU::Write || storeCheck)) {
356  DPRINTF(TLB, "Tried to write to unwritable segment.\n");
357  return std::make_shared<GeneralProtection>(0);
358  }
359  if (!attr.readable && mode == BaseMMU::Read) {
360  DPRINTF(TLB, "Tried to read from unreadble segment.\n");
361  return std::make_shared<GeneralProtection>(0);
362  }
363  expandDown = attr.expandDown;
364 
365  }
368  Addr offset;
369  if (mode == BaseMMU::Execute)
370  offset = vaddr - base;
371  else
372  offset = (vaddr - base) & addrMask;
373  Addr endOffset = offset + req->getSize() - 1;
374  if (expandDown) {
375  DPRINTF(TLB, "Checking an expand down segment.\n");
376  warn_once("Expand down segments are untested.\n");
377  if (offset <= limit || endOffset <= limit)
378  return std::make_shared<GeneralProtection>(0);
379  } else {
380  if (offset > limit || endOffset > limit) {
381  DPRINTF(TLB, "Segment limit check failed, "
382  "offset = %#x limit = %#x.\n", offset, limit);
383  return std::make_shared<GeneralProtection>(0);
384  }
385  }
386  }
387  if (m5Reg.submode != SixtyFourBitMode && addrSize != 64)
388  vaddr &= mask(32);
389  // If paging is enabled, do the translation.
390  if (m5Reg.paging) {
391  DPRINTF(TLB, "Paging enabled.\n");
392  // The vaddr already has the segment base applied.
393  TlbEntry *entry = lookup(vaddr);
394  if (mode == BaseMMU::Read) {
395  stats.rdAccesses++;
396  } else {
397  stats.wrAccesses++;
398  }
399  if (!entry) {
400  DPRINTF(TLB, "Handling a TLB miss for "
401  "address %#x at pc %#x.\n",
402  vaddr, tc->pcState().instAddr());
403  if (mode == BaseMMU::Read) {
404  stats.rdMisses++;
405  } else {
406  stats.wrMisses++;
407  }
408  if (FullSystem) {
409  Fault fault = walker->start(tc, translation, req, mode);
410  if (timing || fault != NoFault) {
411  // This gets ignored in atomic mode.
412  delayedResponse = true;
413  return fault;
414  }
415  entry = lookup(vaddr);
416  assert(entry);
417  } else {
418  Process *p = tc->getProcessPtr();
419  const EmulationPageTable::Entry *pte =
420  p->pTable->lookup(vaddr);
421  if (!pte) {
422  return std::make_shared<PageFault>(vaddr, true, mode,
423  true, false);
424  } else {
425  Addr alignedVaddr = p->pTable->pageAlign(vaddr);
426  DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
427  pte->paddr);
428  entry = insert(alignedVaddr, TlbEntry(
429  p->pTable->pid(), alignedVaddr, pte->paddr,
432  }
433  DPRINTF(TLB, "Miss was serviced.\n");
434  }
435  }
436 
437  DPRINTF(TLB, "Entry found with paddr %#x, "
438  "doing protection checks.\n", entry->paddr);
439  // Do paging protection checks.
440  bool inUser = m5Reg.cpl == 3 && !(flags & CPL0FlagBit);
441  CR0 cr0 = tc->readMiscRegNoEffect(misc_reg::Cr0);
442  bool badWrite = (!entry->writable && (inUser || cr0.wp));
443  if ((inUser && !entry->user) ||
444  (mode == BaseMMU::Write && badWrite)) {
445  // The page must have been present to get into the TLB in
446  // the first place. We'll assume the reserved bits are
447  // fine even though we're not checking them.
448  return std::make_shared<PageFault>(vaddr, true, mode, inUser,
449  false);
450  }
451  if (storeCheck && badWrite) {
452  // This would fault if this were a write, so return a page
453  // fault that reflects that happening.
454  return std::make_shared<PageFault>(
455  vaddr, true, BaseMMU::Write, inUser, false);
456  }
457 
458  Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
459  DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
460  req->setPaddr(paddr);
461  if (entry->uncacheable)
463  } else {
464  //Use the address which already has segmentation applied.
465  DPRINTF(TLB, "Paging disabled.\n");
466  DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
467  req->setPaddr(vaddr);
468  }
469  } else {
470  // Real mode
471  DPRINTF(TLB, "In real mode.\n");
472  DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
473  req->setPaddr(vaddr);
474  }
475 
476  return finalizePhysical(req, tc, mode);
477 }
478 
479 Fault
482 {
483  bool delayedResponse;
484  return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
485 }
486 
487 Fault
490 {
491  unsigned logBytes;
492  const Addr vaddr = req->getVaddr();
493  Addr addr = vaddr;
494  Addr paddr = 0;
495  if (FullSystem) {
496  Fault fault = walker->startFunctional(tc, addr, logBytes, mode);
497  if (fault != NoFault)
498  return fault;
499  paddr = insertBits(addr, logBytes - 1, 0, vaddr);
500  } else {
501  Process *process = tc->getProcessPtr();
502  const auto *pte = process->pTable->lookup(vaddr);
503 
504  if (!pte && mode != BaseMMU::Execute) {
505  // Check if we just need to grow the stack.
506  if (process->fixupFault(vaddr)) {
507  // If we did, lookup the entry for the new page.
508  pte = process->pTable->lookup(vaddr);
509  }
510  }
511 
512  if (!pte)
513  return std::make_shared<PageFault>(vaddr, true, mode, true, false);
514 
515  paddr = pte->paddr | process->pTable->pageOffset(vaddr);
516  }
517  DPRINTF(TLB, "Translated (functional) %#x -> %#x.\n", vaddr, paddr);
518  req->setPaddr(paddr);
519  return NoFault;
520 }
521 
522 void
525 {
526  bool delayedResponse;
527  assert(translation);
528  Fault fault =
529  TLB::translate(req, tc, translation, mode, delayedResponse, true);
530  if (!delayedResponse)
531  translation->finish(fault, req, tc, mode);
532  else
533  translation->markDelayed();
534 }
535 
536 Walker *
538 {
539  return walker;
540 }
541 
543  : statistics::Group(parent),
544  ADD_STAT(rdAccesses, statistics::units::Count::get(),
545  "TLB accesses on read requests"),
546  ADD_STAT(wrAccesses, statistics::units::Count::get(),
547  "TLB accesses on write requests"),
548  ADD_STAT(rdMisses, statistics::units::Count::get(),
549  "TLB misses on read requests"),
550  ADD_STAT(wrMisses, statistics::units::Count::get(),
551  "TLB misses on write requests")
552 {
553 }
554 
555 void
557 {
558  // Only store the entries in use.
559  uint32_t _size = size - freeList.size();
560  SERIALIZE_SCALAR(_size);
562 
563  uint32_t _count = 0;
564  for (uint32_t x = 0; x < size; x++) {
565  if (tlb[x].trieHandle != NULL)
566  tlb[x].serializeSection(cp, csprintf("Entry%d", _count++));
567  }
568 }
569 
570 void
572 {
573  // Do not allow to restore with a smaller tlb.
574  uint32_t _size;
575  UNSERIALIZE_SCALAR(_size);
576  if (_size > size) {
577  fatal("TLB size less than the one in checkpoint!");
578  }
579 
581 
582  for (uint32_t x = 0; x < _size; x++) {
583  TlbEntry *newEntry = freeList.front();
584  freeList.pop_front();
585 
586  newEntry->unserializeSection(cp, csprintf("Entry%d", x));
587  newEntry->trieHandle = trie.insert(newEntry->vaddr,
588  TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
589  }
590 }
591 
592 Port *
594 {
595  return &walker->getPort("port");
596 }
597 
598 } // namespace X86ISA
599 } // namespace gem5
gem5::EmulationPageTable::Entry::flags
uint64_t flags
Definition: page_table.hh:59
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::X86ISA::mask
mask
Definition: misc.hh:796
gem5::X86ISA::TlbEntry::writable
bool writable
Definition: pagetable.hh:77
gem5::ArmISA::tlb
Bitfield< 59, 56 > tlb
Definition: misc_types.hh:92
gem5::X86ISA::TLB::tlb
std::vector< TlbEntry > tlb
Definition: tlb.hh:98
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
x86_traits.hh
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::X86ISA::x
Bitfield< 1 > x
Definition: types.hh:108
gem5::X86ISA::TLB::TLB
TLB(const Params &p)
Definition: tlb.cc:65
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:343
gem5::X86ISA::SegmentFlagMask
constexpr Request::FlagsType SegmentFlagMask
Definition: ldstflags.hh:54
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::X86ISA::misc_reg::PciConfigAddress
@ PciConfigAddress
Definition: misc.hh:404
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::X86ISA::TlbEntry::trieHandle
TlbEntryTrie::Handle trieHandle
Definition: pagetable.hh:94
gem5::EmulationPageTable::Uncacheable
@ Uncacheable
Definition: page_table.hh:99
gem5::X86ISA::x86LocalAPICAddress
static Addr x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
Definition: x86_traits.hh:91
gem5::X86ISA::mode
Bitfield< 3 > mode
Definition: types.hh:192
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::X86ISA::TLB::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tlb.cc:571
microldstop.hh
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::X86ISA::IntAddrPrefixMSR
const Addr IntAddrPrefixMSR
Definition: x86_traits.hh:64
gem5::Packet::setData
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
Definition: packet.hh:1265
gem5::X86ISA::TlbEntry::user
bool user
Definition: pagetable.hh:79
gem5::X86ISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Definition: tlb.cc:523
pseudo_inst.hh
gem5::X86ISA::misc_reg::M5Reg
@ M5Reg
Definition: misc.hh:146
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::attr
attr
Definition: misc_types.hh:656
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:56
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:471
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.cc:480
gem5::X86ISA::Walker::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: pagetable_walker.cc:173
gem5::BaseMMU::Translation::markDelayed
virtual void markDelayed()=0
Signal that the translation has been delayed due to a hw page table walk.
gem5::X86ISA::offset
offset
Definition: misc.hh:1024
gem5::X86ISA::TLB::getWalker
Walker * getWalker()
Definition: tlb.cc:88
gem5::X86ISA::Walker::start
Fault start(ThreadContext *_tc, BaseMMU::Translation *translation, const RequestPtr &req, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:72
gem5::X86ISA::TLB::flushNonGlobal
void flushNonGlobal()
Definition: tlb.cc:152
pagetable_walker.hh
gem5::X86ISA::misc_reg::ApicBase
@ ApicBase
Definition: misc.hh:401
gem5::Trie::lookup
Value * lookup(Key key)
Method which looks up the Value corresponding to a particular key.
Definition: trie.hh:300
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::X86ISA::misc_reg::segAttr
static RegIndex segAttr(int index)
Definition: misc.hh:531
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::X86ISA::TLB::TlbStats::rdMisses
statistics::Scalar rdMisses
Definition: tlb.hh:113
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:133
gem5::X86ISA::limit
BitfieldType< SegDescriptorLimit > limit
Definition: misc.hh:924
gem5::X86ISA::Walker
Definition: pagetable_walker.hh:60
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::EmulationPageTable::ReadOnly
@ ReadOnly
Definition: page_table.hh:100
gem5::X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:204
gem5::Request::READ_MODIFY_WRITE
@ READ_MODIFY_WRITE
This request is a read which will be followed by a write.
Definition: request.hh:161
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
faults.hh
gem5::X86ISA::segment_idx::Cs
@ Cs
Definition: segment.hh:51
request.hh
gem5::X86ISA::TLB::translateInt
Fault translateInt(bool read, RequestPtr req, ThreadContext *tc)
Definition: tlb.cc:198
gem5::X86ISA::TLB::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tlb.cc:556
gem5::X86ISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.cc:488
gem5::X86ISA::AddrSizeFlagShift
constexpr auto AddrSizeFlagShift
Definition: ldstflags.hh:57
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:56
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::Process::fixupFault
bool fixupFault(Addr vaddr)
Attempt to fix up a fault at vaddr by allocating a page on the stack.
Definition: process.cc:365
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::X86ISA::TlbEntry
Definition: pagetable.hh:65
gem5::X86ISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
Definition: tlb.cc:261
gem5::X86ISA::TLB::freeList
EntryList freeList
Definition: tlb.hh:100
gem5::X86ISA::misc_reg::segBase
static RegIndex segBase(int index)
Definition: misc.hh:510
gem5::Flags< FlagsType >
gem5::Trie::remove
Value * remove(Handle handle)
Method to delete a value from the trie.
Definition: trie.hh:317
gem5::X86ISA::TLB::setConfigAddress
void setConfigAddress(uint32_t addr)
Definition: tlb.cc:146
gem5::Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:125
gem5::X86ISA::misc_reg::Cr0
@ Cr0
Definition: misc.hh:114
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Serializable::unserializeSection
void unserializeSection(CheckpointIn &cp, const char *name)
Unserialize an a child object.
Definition: serialize.cc:81
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:185
msr.hh
gem5::X86ISA::segment_idx::Es
@ Es
Definition: segment.hh:50
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::X86ISA::IntAddrPrefixMask
const Addr IntAddrPrefixMask
Definition: x86_traits.hh:62
process.hh
gem5::BaseTLB
Definition: tlb.hh:58
gem5::X86ISA::TlbEntry::uncacheable
bool uncacheable
Definition: pagetable.hh:84
gem5::X86ISA::TLB::trie
TlbEntryTrie trie
Definition: tlb.hh:102
gem5::X86ISA::TLB::stats
gem5::X86ISA::TLB::TlbStats stats
gem5::X86ISA::TLB::TlbStats::wrMisses
statistics::Scalar wrMisses
Definition: tlb.hh:114
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::IntAddrPrefixCPUID
const Addr IntAddrPrefixCPUID
Definition: x86_traits.hh:63
flags
uint8_t flags
Definition: helpers.cc:66
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::pseudo_inst::decodeAddrOffset
static void decodeAddrOffset(Addr offset, uint8_t &func)
Definition: pseudo_inst.hh:63
gem5::X86ISA::TlbEntry::paddr
Addr paddr
Definition: pagetable.hh:68
gem5::Packet::writeData
void writeData(uint8_t *p) const
Copy data from the packet to the memory at the provided pointer.
Definition: packet.hh:1294
gem5::X86ISA::TLB::m5opRange
AddrRange m5opRange
Definition: tlb.hh:105
gem5::X86ISA::TLB::translate
Fault translate(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayedResponse, bool timing)
Definition: tlb.cc:310
gem5::X86ISA::PhysAddrPrefixPciConfig
const Addr PhysAddrPrefixPciConfig
Definition: x86_traits.hh:68
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::TLB::lookup
TlbEntry * lookup(Addr va, bool update_lru=true)
Definition: tlb.cc:124
gem5::Trie< Addr, TlbEntry >::MaxBits
static const unsigned MaxBits
Definition: trie.hh:135
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::X86ISA::expandDown
Bitfield< 14 > expandDown
Definition: misc.hh:996
packet_access.hh
gem5::X86ISA::TLB::demapPage
void demapPage(Addr va, uint64_t asn) override
Definition: tlb.cc:165
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::X86ISA::segment_idx::Ms
@ Ms
Definition: segment.hh:60
gem5::X86ISA::TLB::insert
TlbEntry * insert(Addr vpn, const TlbEntry &entry)
Definition: tlb.cc:143
full_system.hh
gem5::X86ISA::TLB::evictLRU
void evictLRU()
Definition: tlb.cc:94
gem5::Process
Definition: process.hh:68
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::X86ISA::TLB::TlbStats::rdAccesses
statistics::Scalar rdAccesses
Definition: tlb.hh:111
gem5::X86ISA::TLB::TlbStats::TlbStats
TlbStats(statistics::Group *parent)
Definition: tlb.cc:519
gem5::EmulationPageTable::Entry::paddr
Addr paddr
Definition: page_table.hh:58
gem5::X86ISA::CPL0FlagBit
constexpr auto CPL0FlagBit
Definition: ldstflags.hh:56
gem5::X86ISA::TlbEntry::vaddr
Addr vaddr
Definition: pagetable.hh:71
gem5::X86ISA::AddrSizeFlagMask
constexpr auto AddrSizeFlagMask
Definition: ldstflags.hh:58
gem5::X86ISA::TLB
Definition: tlb.hh:60
gem5::X86ISA::TlbEntry::lruSeq
uint64_t lruSeq
Definition: pagetable.hh:92
gem5::X86ISA::Walker::startFunctional
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:97
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::Walker::setTLB
void setTLB(TLB *_tlb)
Definition: pagetable_walker.hh:196
pseudo_inst_abi.hh
gem5::X86ISA::TLB::configAddress
uint32_t configAddress
Definition: tlb.hh:67
gem5::X86ISA::msrAddrToIndex
bool msrAddrToIndex(RegIndex &reg_num, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition: msr.cc:150
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
Definition: tlb.cc:133
gem5::X86ISA::TLB::Params
X86TLBParams Params
Definition: tlb.hh:71
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::X86ISA::TLB::getTableWalkerPort
Port * getTableWalkerPort() override
Get the table walker port.
Definition: tlb.cc:593
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::X86ISA::TLB::lruSeq
uint64_t lruSeq
Definition: tlb.hh:103
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::X86ISA::TlbEntry::logBytes
unsigned logBytes
Definition: pagetable.hh:73
gem5::X86ISA::TLB::TlbStats::wrAccesses
statistics::Scalar wrAccesses
Definition: tlb.hh:112
gem5::X86ISA::TLB::walker
Walker * walker
Definition: tlb.hh:84
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::IntAddrPrefixIO
const Addr IntAddrPrefixIO
Definition: x86_traits.hh:65
trace.hh
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::Trie::insert
Handle insert(Key key, unsigned width, Value *val)
Method which inserts a key/value pair into the trie.
Definition: trie.hh:212
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
tlb.hh
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::X86ISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:49
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::EmulationPageTable::pageOffset
Addr pageOffset(Addr a)
Definition: page_table.hh:112
gem5::X86ISA::TLB::size
uint32_t size
Definition: tlb.hh:96
misc.hh
gem5::EmulationPageTable::Entry
Definition: page_table.hh:56
gem5::BaseMMU::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
gem5::X86ISA::misc_reg::segLimit
static RegIndex segLimit(int index)
Definition: misc.hh:524
gem5::X86ISA::PhysAddrPrefixIO
const Addr PhysAddrPrefixIO
Definition: x86_traits.hh:67
thread_context.hh
gem5::X86ISA::TLB::nextSeq
uint64_t nextSeq()
Definition: tlb.hh:128
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::segment_idx::Hs
@ Hs
Definition: segment.hh:56

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