gem5  v21.1.0.2
process.cc
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1 /*
2  * Copyright (c) 2014 Advanced Micro Devices, Inc.
3  * Copyright (c) 2007 The Hewlett-Packard Development Company
4  * All rights reserved.
5  *
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41 
42 #include "arch/x86/process.hh"
43 
44 #include <string>
45 #include <vector>
46 
47 #include "arch/x86/fs_workload.hh"
48 #include "arch/x86/page_size.hh"
49 #include "arch/x86/regs/misc.hh"
50 #include "arch/x86/regs/segment.hh"
51 #include "arch/x86/se_workload.hh"
52 #include "arch/x86/types.hh"
55 #include "base/logging.hh"
56 #include "base/trace.hh"
57 #include "cpu/thread_context.hh"
58 #include "debug/Stack.hh"
60 #include "mem/page_table.hh"
61 #include "params/Process.hh"
62 #include "sim/aux_vector.hh"
63 #include "sim/byteswap.hh"
64 #include "sim/process_impl.hh"
65 #include "sim/syscall_desc.hh"
66 #include "sim/syscall_return.hh"
67 #include "sim/system.hh"
68 
69 namespace gem5
70 {
71 
72 using namespace X86ISA;
73 
74 template class MultiLevelPageTable<LongModePTE<47, 39>,
75  LongModePTE<38, 30>,
76  LongModePTE<29, 21>,
77  LongModePTE<20, 12> >;
78 typedef MultiLevelPageTable<LongModePTE<47, 39>,
79  LongModePTE<38, 30>,
80  LongModePTE<29, 21>,
82 
83 X86Process::X86Process(const ProcessParams &params,
84  loader::ObjectFile *objFile) :
85  Process(params, params.useArchPT ?
86  static_cast<EmulationPageTable *>(
87  new ArchPageTable(params.name, params.pid,
88  params.system, PageBytes)) :
89  new EmulationPageTable(params.name, params.pid,
90  PageBytes),
91  objFile)
92 {
93 }
94 
96  Process *p, RegVal flags)
97 {
98  Process::clone(old_tc, new_tc, p, flags);
99  X86Process *process = (X86Process*)p;
100  *process = *this;
101 }
102 
103 X86_64Process::X86_64Process(const ProcessParams &params,
104  loader::ObjectFile *objFile) :
105  X86Process(params, objFile)
106 {
107  vsyscallPage.base = 0xffffffffff600000ULL;
109  vsyscallPage.vtimeOffset = 0x400;
111 
112  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
113  Addr stack_base = 0x7FFFFFFFF000ULL;
114  Addr max_stack_size = 8 * 1024 * 1024;
115  Addr next_thread_stack_base = stack_base - max_stack_size;
116  Addr mmap_end = 0x7FFFF7FFF000ULL;
117 
118  memState = std::make_shared<MemState>(
119  this, brk_point, stack_base, max_stack_size,
120  next_thread_stack_base, mmap_end);
121 }
122 
123 
124 I386Process::I386Process(const ProcessParams &params,
125  loader::ObjectFile *objFile) :
126  X86Process(params, objFile)
127 {
128  if (kvmInSE)
129  panic("KVM CPU model does not support 32 bit processes");
130 
131  _gdtStart = 0xffffd000ULL;
133 
134  vsyscallPage.base = 0xffffe000ULL;
138 
139  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
140  Addr stack_base = _gdtStart;
141  Addr max_stack_size = 8 * 1024 * 1024;
142  Addr next_thread_stack_base = stack_base - max_stack_size;
143  Addr mmap_end = 0xB7FFF000ULL;
144 
145  memState = std::make_shared<MemState>(
146  this, brk_point, stack_base, max_stack_size,
147  next_thread_stack_base, mmap_end);
148 }
149 
150 void
152 {
154 
155  if (useForClone)
156  return;
157 
159 
160  // Set up the vsyscall page for this process.
161  memState->mapRegion(vsyscallPage.base, vsyscallPage.size, "vsyscall");
162  uint8_t vtimeBlob[] = {
163  0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
164  0x0f,0x05, // syscall
165  0xc3 // retq
166  };
168  vtimeBlob, sizeof(vtimeBlob));
169 
170  uint8_t vgettimeofdayBlob[] = {
171  0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
172  0x0f,0x05, // syscall
173  0xc3 // retq
174  };
175  initVirtMem->writeBlob(
177  vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
178 
179  if (kvmInSE) {
180  PortProxy physProxy = system->physProxy;
181 
182  Addr syscallCodePhysAddr = system->allocPhysPages(1);
183  Addr gdtPhysAddr = system->allocPhysPages(1);
184  Addr idtPhysAddr = system->allocPhysPages(1);
185  Addr istPhysAddr = system->allocPhysPages(1);
186  Addr tssPhysAddr = system->allocPhysPages(1);
187  Addr pfHandlerPhysAddr = system->allocPhysPages(1);
188 
189  /*
190  * Set up the gdt.
191  */
192  uint8_t numGDTEntries = 0;
193  uint64_t nullDescriptor = 0;
194  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
195  &nullDescriptor, 8);
196  numGDTEntries++;
197 
198  SegDescriptor initDesc = 0;
199  initDesc.type.codeOrData = 0; // code or data type
200  initDesc.type.c = 0; // conforming
201  initDesc.type.r = 1; // readable
202  initDesc.dpl = 0; // privilege
203  initDesc.p = 1; // present
204  initDesc.l = 1; // longmode - 64 bit
205  initDesc.d = 0; // operand size
206  initDesc.g = 1;
207  initDesc.s = 1; // system segment
208  initDesc.limit = 0xFFFFFFFF;
209  initDesc.base = 0;
210 
211  //64 bit code segment
212  SegDescriptor csLowPLDesc = initDesc;
213  csLowPLDesc.type.codeOrData = 1;
214  csLowPLDesc.dpl = 0;
215  uint64_t csLowPLDescVal = csLowPLDesc;
216  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
217  &csLowPLDescVal, 8);
218 
219  numGDTEntries++;
220 
221  SegSelector csLowPL = 0;
222  csLowPL.si = numGDTEntries - 1;
223  csLowPL.rpl = 0;
224 
225  //64 bit data segment
226  SegDescriptor dsLowPLDesc = initDesc;
227  dsLowPLDesc.type.codeOrData = 0;
228  dsLowPLDesc.dpl = 0;
229  uint64_t dsLowPLDescVal = dsLowPLDesc;
230  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
231  &dsLowPLDescVal, 8);
232 
233  numGDTEntries++;
234 
235  SegSelector dsLowPL = 0;
236  dsLowPL.si = numGDTEntries - 1;
237  dsLowPL.rpl = 0;
238 
239  //64 bit data segment
240  SegDescriptor dsDesc = initDesc;
241  dsDesc.type.codeOrData = 0;
242  dsDesc.dpl = 3;
243  uint64_t dsDescVal = dsDesc;
244  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
245  &dsDescVal, 8);
246 
247  numGDTEntries++;
248 
249  SegSelector ds = 0;
250  ds.si = numGDTEntries - 1;
251  ds.rpl = 3;
252 
253  //64 bit code segment
254  SegDescriptor csDesc = initDesc;
255  csDesc.type.codeOrData = 1;
256  csDesc.dpl = 3;
257  uint64_t csDescVal = csDesc;
258  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
259  &csDescVal, 8);
260 
261  numGDTEntries++;
262 
263  SegSelector cs = 0;
264  cs.si = numGDTEntries - 1;
265  cs.rpl = 3;
266 
267  SegSelector scall = 0;
268  scall.si = csLowPL.si;
269  scall.rpl = 0;
270 
271  SegSelector sret = 0;
272  sret.si = dsLowPL.si;
273  sret.rpl = 3;
274 
275  /* In long mode the TSS has been extended to 16 Bytes */
276  TSSlow TSSDescLow = 0;
277  TSSDescLow.type = 0xB;
278  TSSDescLow.dpl = 0; // Privelege level 0
279  TSSDescLow.p = 1; // Present
280  TSSDescLow.limit = 0xFFFFFFFF;
281  TSSDescLow.base = bits(TSSVirtAddr, 31, 0);
282 
283  TSShigh TSSDescHigh = 0;
284  TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
285 
286  struct TSSDesc
287  {
288  uint64_t low;
289  uint64_t high;
290  } tssDescVal = {TSSDescLow, TSSDescHigh};
291 
292  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
293  &tssDescVal, sizeof(tssDescVal));
294 
295  numGDTEntries++;
296 
297  SegSelector tssSel = 0;
298  tssSel.si = numGDTEntries - 1;
299 
300  uint64_t tss_base_addr = (TSSDescHigh.base << 32) | TSSDescLow.base;
301  uint64_t tss_limit = TSSDescLow.limit;
302 
303  SegAttr tss_attr = 0;
304 
305  tss_attr.type = TSSDescLow.type;
306  tss_attr.dpl = TSSDescLow.dpl;
307  tss_attr.present = TSSDescLow.p;
308  tss_attr.granularity = TSSDescLow.g;
309  tss_attr.unusable = 0;
310 
311  for (int i = 0; i < contextIds.size(); i++) {
313 
314  tc->setMiscReg(MISCREG_CS, cs);
315  tc->setMiscReg(MISCREG_DS, ds);
316  tc->setMiscReg(MISCREG_ES, ds);
317  tc->setMiscReg(MISCREG_FS, ds);
318  tc->setMiscReg(MISCREG_GS, ds);
319  tc->setMiscReg(MISCREG_SS, ds);
320 
321  // LDT
322  tc->setMiscReg(MISCREG_TSL, 0);
323  SegAttr tslAttr = 0;
324  tslAttr.present = 1;
325  tslAttr.type = 2;
326  tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
327 
329  tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
330 
331  tc->setMiscReg(MISCREG_TR, tssSel);
332  tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
333  tc->setMiscReg(MISCREG_TR_EFF_BASE, tss_base_addr);
334  tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
335  tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
336 
337  //Start using longmode segments.
338  installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
339  installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
340  installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
341  installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
342  installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
343  installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
344 
345  Efer efer = 0;
346  efer.sce = 1; // Enable system call extensions.
347  efer.lme = 1; // Enable long mode.
348  efer.lma = 1; // Activate long mode.
349  efer.nxe = 1; // Enable nx support.
350  efer.svme = 0; // Disable svm support for now.
351  efer.ffxsr = 0; // Disable fast fxsave and fxrstor.
352  tc->setMiscReg(MISCREG_EFER, efer);
353 
354  //Set up the registers that describe the operating mode.
355  CR0 cr0 = 0;
356  cr0.pg = 1; // Turn on paging.
357  cr0.cd = 0; // Don't disable caching.
358  cr0.nw = 0; // This is bit is defined to be ignored.
359  cr0.am = 0; // No alignment checking
360  cr0.wp = 0; // Supervisor mode can write read only pages
361  cr0.ne = 1;
362  cr0.et = 1; // This should always be 1
363  cr0.ts = 0; // We don't do task switching, so causing fp exceptions
364  // would be pointless.
365  cr0.em = 0; // Allow x87 instructions to execute natively.
366  cr0.mp = 1; // This doesn't really matter, but the manual suggests
367  // setting it to one.
368  cr0.pe = 1; // We're definitely in protected mode.
369  tc->setMiscReg(MISCREG_CR0, cr0);
370 
371  CR0 cr2 = 0;
372  tc->setMiscReg(MISCREG_CR2, cr2);
373 
374  CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
375  tc->setMiscReg(MISCREG_CR3, cr3);
376 
377  CR4 cr4 = 0;
378  //Turn on pae.
379  cr4.osxsave = 0; // Disable XSAVE and Proc Extended States
380  cr4.osxmmexcpt = 0; // Operating System Unmasked Exception
381  cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
382  cr4.pce = 0; // Performance-Monitoring Counter Enable
383  cr4.pge = 0; // Page-Global Enable
384  cr4.mce = 0; // Machine Check Enable
385  cr4.pae = 1; // Physical-Address Extension
386  cr4.pse = 0; // Page Size Extensions
387  cr4.de = 0; // Debugging Extensions
388  cr4.tsd = 0; // Time Stamp Disable
389  cr4.pvi = 0; // Protected-Mode Virtual Interrupts
390  cr4.vme = 0; // Virtual-8086 Mode Extensions
391 
392  tc->setMiscReg(MISCREG_CR4, cr4);
393 
394  CR8 cr8 = 0;
395  tc->setMiscReg(MISCREG_CR8, cr8);
396 
397  tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
398 
399  tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
400 
402  tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
403 
405  tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
406 
407  /* enabling syscall and sysret */
408  RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
409  tc->setMiscReg(MISCREG_STAR, star);
411  tc->setMiscReg(MISCREG_LSTAR, lstar);
412  RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
413  tc->setMiscReg(MISCREG_SF_MASK, sfmask);
414  }
415 
416  /* Set up the content of the TSS and write it to physical memory. */
417 
418  struct
419  {
420  uint32_t reserved0; // +00h
421  uint32_t RSP0_low; // +04h
422  uint32_t RSP0_high; // +08h
423  uint32_t RSP1_low; // +0Ch
424  uint32_t RSP1_high; // +10h
425  uint32_t RSP2_low; // +14h
426  uint32_t RSP2_high; // +18h
427  uint32_t reserved1; // +1Ch
428  uint32_t reserved2; // +20h
429  uint32_t IST1_low; // +24h
430  uint32_t IST1_high; // +28h
431  uint32_t IST2_low; // +2Ch
432  uint32_t IST2_high; // +30h
433  uint32_t IST3_low; // +34h
434  uint32_t IST3_high; // +38h
435  uint32_t IST4_low; // +3Ch
436  uint32_t IST4_high; // +40h
437  uint32_t IST5_low; // +44h
438  uint32_t IST5_high; // +48h
439  uint32_t IST6_low; // +4Ch
440  uint32_t IST6_high; // +50h
441  uint32_t IST7_low; // +54h
442  uint32_t IST7_high; // +58h
443  uint32_t reserved3; // +5Ch
444  uint32_t reserved4; // +60h
445  uint16_t reserved5; // +64h
446  uint16_t IO_MapBase; // +66h
447  } tss;
448 
450  uint64_t IST_start = ISTVirtAddr + PageBytes;
451  tss.IST1_low = IST_start;
452  tss.IST1_high = IST_start >> 32;
453  tss.RSP0_low = tss.IST1_low;
454  tss.RSP0_high = tss.IST1_high;
455  tss.RSP1_low = tss.IST1_low;
456  tss.RSP1_high = tss.IST1_high;
457  tss.RSP2_low = tss.IST1_low;
458  tss.RSP2_high = tss.IST1_high;
459  physProxy.writeBlob(tssPhysAddr, &tss, sizeof(tss));
460 
461  /* Setting IDT gates */
462  GateDescriptorLow PFGateLow = 0;
463  PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
464  PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
465  PFGateLow.selector = csLowPL;
466  PFGateLow.p = 1;
467  PFGateLow.dpl = 0;
468  PFGateLow.type = 0xe; // gate interrupt type
469  PFGateLow.IST = 0; // setting IST to 0 and using RSP0
470 
471  GateDescriptorHigh PFGateHigh = 0;
472  PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
473 
474  struct
475  {
476  uint64_t low;
477  uint64_t high;
478  } PFGate = {PFGateLow, PFGateHigh};
479 
480  physProxy.writeBlob(idtPhysAddr + 0xE0, &PFGate, sizeof(PFGate));
481 
482  /* System call handler */
483  uint8_t syscallBlob[] = {
484  // mov %rax, (0xffffc90000007000)
485  0x48, 0xa3, 0x00, 0x70, 0x00,
486  0x00, 0x00, 0xc9, 0xff, 0xff,
487  // sysret
488  0x48, 0x0f, 0x07
489  };
490 
491  physProxy.writeBlob(syscallCodePhysAddr,
492  syscallBlob, sizeof(syscallBlob));
493 
495  uint8_t faultBlob[] = {
496  // mov %rax, (0xffffc90000007000)
497  0x48, 0xa3, 0x00, 0x70, 0x00,
498  0x00, 0x00, 0xc9, 0xff, 0xff,
499  // add $0x8, %rsp # skip error
500  0x48, 0x83, 0xc4, 0x08,
501  // iretq
502  0x48, 0xcf
503  };
504 
505  physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
506 
507  /* Syscall handler */
508  pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
509  PageBytes, false);
510  /* GDT */
511  pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
512  /* IDT */
513  pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
514  /* TSS */
515  pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
516  /* IST */
517  pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
518  /* PF handler */
519  pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
520  /* MMIO region for m5ops */
522  16 * PageBytes, false);
523  } else {
524  for (int i = 0; i < contextIds.size(); i++) {
526 
527  SegAttr dataAttr = 0;
528  dataAttr.dpl = 3;
529  dataAttr.unusable = 0;
530  dataAttr.defaultSize = 1;
531  dataAttr.longMode = 1;
532  dataAttr.avl = 0;
533  dataAttr.granularity = 1;
534  dataAttr.present = 1;
535  dataAttr.type = 3;
536  dataAttr.writable = 1;
537  dataAttr.readable = 1;
538  dataAttr.expandDown = 0;
539  dataAttr.system = 1;
540 
541  // Initialize the segment registers.
542  for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
545  tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
546  }
547 
548  SegAttr csAttr = 0;
549  csAttr.dpl = 3;
550  csAttr.unusable = 0;
551  csAttr.defaultSize = 0;
552  csAttr.longMode = 1;
553  csAttr.avl = 0;
554  csAttr.granularity = 1;
555  csAttr.present = 1;
556  csAttr.type = 10;
557  csAttr.writable = 0;
558  csAttr.readable = 1;
559  csAttr.expandDown = 0;
560  csAttr.system = 1;
561 
562  tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
563 
564  Efer efer = 0;
565  efer.sce = 1; // Enable system call extensions.
566  efer.lme = 1; // Enable long mode.
567  efer.lma = 1; // Activate long mode.
568  efer.nxe = 1; // Enable nx support.
569  efer.svme = 0; // Disable svm support for now. It isn't implemented.
570  efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
571  tc->setMiscReg(MISCREG_EFER, efer);
572 
573  // Set up the registers that describe the operating mode.
574  CR0 cr0 = 0;
575  cr0.pg = 1; // Turn on paging.
576  cr0.cd = 0; // Don't disable caching.
577  cr0.nw = 0; // This is bit is defined to be ignored.
578  cr0.am = 0; // No alignment checking
579  cr0.wp = 0; // Supervisor mode can write read only pages
580  cr0.ne = 1;
581  cr0.et = 1; // This should always be 1
582  cr0.ts = 0; // We don't do task switching, so causing fp exceptions
583  // would be pointless.
584  cr0.em = 0; // Allow x87 instructions to execute natively.
585  cr0.mp = 1; // This doesn't really matter, but the manual suggests
586  // setting it to one.
587  cr0.pe = 1; // We're definitely in protected mode.
588  tc->setMiscReg(MISCREG_CR0, cr0);
589 
590  tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
591  }
592  }
593 }
594 
595 void
597 {
599 
601 
602  /*
603  * Set up a GDT for this process. The whole GDT wouldn't really be for
604  * this process, but the only parts we care about are.
605  */
607  uint64_t zero = 0;
608  assert(_gdtSize % sizeof(zero) == 0);
609  for (Addr gdtCurrent = _gdtStart;
610  gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
611  initVirtMem->write(gdtCurrent, zero);
612  }
613 
614  // Set up the vsyscall page for this process.
615  memState->mapRegion(vsyscallPage.base, vsyscallPage.size, "vsyscall");
616  uint8_t vsyscallBlob[] = {
617  0x51, // push %ecx
618  0x52, // push %edp
619  0x55, // push %ebp
620  0x89, 0xe5, // mov %esp, %ebp
621  0x0f, 0x34 // sysenter
622  };
624  vsyscallBlob, sizeof(vsyscallBlob));
625 
626  uint8_t vsysexitBlob[] = {
627  0x5d, // pop %ebp
628  0x5a, // pop %edx
629  0x59, // pop %ecx
630  0xc3 // ret
631  };
633  vsysexitBlob, sizeof(vsysexitBlob));
634 
635  for (int i = 0; i < contextIds.size(); i++) {
637 
638  SegAttr dataAttr = 0;
639  dataAttr.dpl = 3;
640  dataAttr.unusable = 0;
641  dataAttr.defaultSize = 1;
642  dataAttr.longMode = 0;
643  dataAttr.avl = 0;
644  dataAttr.granularity = 1;
645  dataAttr.present = 1;
646  dataAttr.type = 3;
647  dataAttr.writable = 1;
648  dataAttr.readable = 1;
649  dataAttr.expandDown = 0;
650  dataAttr.system = 1;
651 
652  // Initialize the segment registers.
653  for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
656  tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
658  tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
659  }
660 
661  SegAttr csAttr = 0;
662  csAttr.dpl = 3;
663  csAttr.unusable = 0;
664  csAttr.defaultSize = 1;
665  csAttr.longMode = 0;
666  csAttr.avl = 0;
667  csAttr.granularity = 1;
668  csAttr.present = 1;
669  csAttr.type = 0xa;
670  csAttr.writable = 0;
671  csAttr.readable = 1;
672  csAttr.expandDown = 0;
673  csAttr.system = 1;
674 
675  tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
676 
680 
681  // Set the LDT selector to 0 to deactivate it.
683 
684  Efer efer = 0;
685  efer.sce = 1; // Enable system call extensions.
686  efer.lme = 1; // Enable long mode.
687  efer.lma = 0; // Deactivate long mode.
688  efer.nxe = 1; // Enable nx support.
689  efer.svme = 0; // Disable svm support for now. It isn't implemented.
690  efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
691  tc->setMiscReg(MISCREG_EFER, efer);
692 
693  // Set up the registers that describe the operating mode.
694  CR0 cr0 = 0;
695  cr0.pg = 1; // Turn on paging.
696  cr0.cd = 0; // Don't disable caching.
697  cr0.nw = 0; // This is bit is defined to be ignored.
698  cr0.am = 0; // No alignment checking
699  cr0.wp = 0; // Supervisor mode can write read only pages
700  cr0.ne = 1;
701  cr0.et = 1; // This should always be 1
702  cr0.ts = 0; // We don't do task switching, so causing fp exceptions
703  // would be pointless.
704  cr0.em = 0; // Allow x87 instructions to execute natively.
705  cr0.mp = 1; // This doesn't really matter, but the manual suggests
706  // setting it to one.
707  cr0.pe = 1; // We're definitely in protected mode.
708  tc->setMiscReg(MISCREG_CR0, cr0);
709 
710  tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
711  }
712 }
713 
714 template<class IntType>
715 void
716 X86Process::argsInit(int pageSize,
718 {
719  int intSize = sizeof(IntType);
720 
722 
723  std::string filename;
724  if (argv.size() < 1)
725  filename = "";
726  else
727  filename = argv[0];
728 
729  // We want 16 byte alignment
730  uint64_t align = 16;
731 
732  enum X86CpuFeature
733  {
734  X86_OnboardFPU = 1 << 0,
735  X86_VirtualModeExtensions = 1 << 1,
736  X86_DebuggingExtensions = 1 << 2,
737  X86_PageSizeExtensions = 1 << 3,
738 
739  X86_TimeStampCounter = 1 << 4,
740  X86_ModelSpecificRegisters = 1 << 5,
741  X86_PhysicalAddressExtensions = 1 << 6,
742  X86_MachineCheckExtensions = 1 << 7,
743 
744  X86_CMPXCHG8Instruction = 1 << 8,
745  X86_OnboardAPIC = 1 << 9,
746  X86_SYSENTER_SYSEXIT = 1 << 11,
747 
748  X86_MemoryTypeRangeRegisters = 1 << 12,
749  X86_PageGlobalEnable = 1 << 13,
750  X86_MachineCheckArchitecture = 1 << 14,
751  X86_CMOVInstruction = 1 << 15,
752 
753  X86_PageAttributeTable = 1 << 16,
754  X86_36BitPSEs = 1 << 17,
755  X86_ProcessorSerialNumber = 1 << 18,
756  X86_CLFLUSHInstruction = 1 << 19,
757 
758  X86_DebugTraceStore = 1 << 21,
759  X86_ACPIViaMSR = 1 << 22,
760  X86_MultimediaExtensions = 1 << 23,
761 
762  X86_FXSAVE_FXRSTOR = 1 << 24,
763  X86_StreamingSIMDExtensions = 1 << 25,
764  X86_StreamingSIMDExtensions2 = 1 << 26,
765  X86_CPUSelfSnoop = 1 << 27,
766 
767  X86_HyperThreading = 1 << 28,
768  X86_AutomaticClockControl = 1 << 29,
769  X86_IA64Processor = 1 << 30
770  };
771 
772  // Setup the auxiliary vectors. These will already have endian
773  // conversion. Auxiliary vectors are loaded only for elf formatted
774  // executables; the auxv is responsible for passing information from
775  // the OS to the interpreter.
776  auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
777  if (elfObject) {
778  uint64_t features =
779  X86_OnboardFPU |
780  X86_VirtualModeExtensions |
781  X86_DebuggingExtensions |
782  X86_PageSizeExtensions |
783  X86_TimeStampCounter |
784  X86_ModelSpecificRegisters |
785  X86_PhysicalAddressExtensions |
786  X86_MachineCheckExtensions |
787  X86_CMPXCHG8Instruction |
788  X86_OnboardAPIC |
789  X86_SYSENTER_SYSEXIT |
790  X86_MemoryTypeRangeRegisters |
791  X86_PageGlobalEnable |
792  X86_MachineCheckArchitecture |
793  X86_CMOVInstruction |
794  X86_PageAttributeTable |
795  X86_36BitPSEs |
796 // X86_ProcessorSerialNumber |
797  X86_CLFLUSHInstruction |
798 // X86_DebugTraceStore |
799 // X86_ACPIViaMSR |
800  X86_MultimediaExtensions |
801  X86_FXSAVE_FXRSTOR |
802  X86_StreamingSIMDExtensions |
803  X86_StreamingSIMDExtensions2 |
804 // X86_CPUSelfSnoop |
805 // X86_HyperThreading |
806 // X86_AutomaticClockControl |
807 // X86_IA64Processor |
808  0;
809 
810  // Bits which describe the system hardware capabilities
811  // XXX Figure out what these should be
812  auxv.emplace_back(gem5::auxv::Hwcap, features);
813  // The system page size
814  auxv.emplace_back(gem5::auxv::Pagesz, X86ISA::PageBytes);
815  // Frequency at which times() increments
816  // Defined to be 100 in the kernel source.
817  auxv.emplace_back(gem5::auxv::Clktck, 100);
818  // This is the virtual address of the program header tables if they
819  // appear in the executable image.
820  auxv.emplace_back(gem5::auxv::Phdr, elfObject->programHeaderTable());
821  // This is the size of a program header entry from the elf file.
822  auxv.emplace_back(gem5::auxv::Phent, elfObject->programHeaderSize());
823  // This is the number of program headers from the original elf file.
824  auxv.emplace_back(gem5::auxv::Phnum, elfObject->programHeaderCount());
825  // This is the base address of the ELF interpreter; it should be
826  // zero for static executables or contain the base address for
827  // dynamic executables.
828  auxv.emplace_back(gem5::auxv::Base, getBias());
829  // XXX Figure out what this should be.
830  auxv.emplace_back(gem5::auxv::Flags, 0);
831  // The entry point to the program
832  auxv.emplace_back(gem5::auxv::Entry, objFile->entryPoint());
833  // Different user and group IDs
834  auxv.emplace_back(gem5::auxv::Uid, uid());
835  auxv.emplace_back(gem5::auxv::Euid, euid());
836  auxv.emplace_back(gem5::auxv::Gid, gid());
837  auxv.emplace_back(gem5::auxv::Egid, egid());
838  // Whether to enable "secure mode" in the executable
839  auxv.emplace_back(gem5::auxv::Secure, 0);
840  // The address of 16 "random" bytes.
841  auxv.emplace_back(gem5::auxv::Random, 0);
842  // The name of the program
843  auxv.emplace_back(gem5::auxv::Execfn, 0);
844  // The platform string
845  auxv.emplace_back(gem5::auxv::Platform, 0);
846  }
847 
848  // Figure out how big the initial stack needs to be
849 
850  // A sentry NULL void pointer at the top of the stack.
851  int sentry_size = intSize;
852 
853  // This is the name of the file which is present on the initial stack
854  // It's purpose is to let the user space linker examine the original file.
855  int file_name_size = filename.size() + 1;
856 
857  const int numRandomBytes = 16;
858  int aux_data_size = numRandomBytes;
859 
860  std::string platform = "x86_64";
861  aux_data_size += platform.size() + 1;
862 
863  int env_data_size = 0;
864  for (int i = 0; i < envp.size(); ++i)
865  env_data_size += envp[i].size() + 1;
866  int arg_data_size = 0;
867  for (int i = 0; i < argv.size(); ++i)
868  arg_data_size += argv[i].size() + 1;
869 
870  // The info_block needs to be padded so its size is a multiple of the
871  // alignment mask. Also, it appears that there needs to be at least some
872  // padding, so if the size is already a multiple, we need to increase it
873  // anyway.
874  int base_info_block_size =
875  sentry_size + file_name_size + env_data_size + arg_data_size;
876 
877  int info_block_size = roundUp(base_info_block_size, align);
878 
879  int info_block_padding = info_block_size - base_info_block_size;
880 
881  // Each auxiliary vector is two 8 byte words
882  int aux_array_size = intSize * 2 * (auxv.size() + 1);
883 
884  int envp_array_size = intSize * (envp.size() + 1);
885  int argv_array_size = intSize * (argv.size() + 1);
886 
887  int argc_size = intSize;
888 
889  // Figure out the size of the contents of the actual initial frame
890  int frame_size =
891  aux_array_size +
892  envp_array_size +
893  argv_array_size +
894  argc_size;
895 
896  // There needs to be padding after the auxiliary vector data so that the
897  // very bottom of the stack is aligned properly.
898  int partial_size = frame_size + aux_data_size;
899  int aligned_partial_size = roundUp(partial_size, align);
900  int aux_padding = aligned_partial_size - partial_size;
901 
902  int space_needed =
903  info_block_size +
904  aux_data_size +
905  aux_padding +
906  frame_size;
907 
908  Addr stack_base = memState->getStackBase();
909 
910  Addr stack_min = stack_base - space_needed;
911  stack_min = roundDown(stack_min, align);
912 
913  unsigned stack_size = stack_base - stack_min;
914  stack_size = roundUp(stack_size, pageSize);
915  memState->setStackSize(stack_size);
916 
917  // map memory
918  Addr stack_end = roundDown(stack_base - stack_size, pageSize);
919 
920  DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
921  memState->mapRegion(stack_end, stack_size, "stack");
922 
923  // map out initial stack contents
924  IntType sentry_base = stack_base - sentry_size;
925  IntType file_name_base = sentry_base - file_name_size;
926  IntType env_data_base = file_name_base - env_data_size;
927  IntType arg_data_base = env_data_base - arg_data_size;
928  IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
929  IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
930  IntType envp_array_base = auxv_array_base - envp_array_size;
931  IntType argv_array_base = envp_array_base - argv_array_size;
932  IntType argc_base = argv_array_base - argc_size;
933 
934  DPRINTF(Stack, "The addresses of items on the initial stack:\n");
935  DPRINTF(Stack, "0x%x - file name\n", file_name_base);
936  DPRINTF(Stack, "0x%x - env data\n", env_data_base);
937  DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
938  DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
939  DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
940  DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
941  DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
942  DPRINTF(Stack, "0x%x - argc \n", argc_base);
943  DPRINTF(Stack, "0x%x - stack min\n", stack_min);
944 
945  // write contents to stack
946 
947  // figure out argc
948  IntType argc = argv.size();
949  IntType guestArgc = htole(argc);
950 
951  // Write out the sentry void *
952  IntType sentry_NULL = 0;
953  initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
954 
955  // Write the file name
956  initVirtMem->writeString(file_name_base, filename.c_str());
957 
958  // Fix up the aux vectors which point to data
959  assert(auxv[auxv.size() - 3].type == gem5::auxv::Random);
960  auxv[auxv.size() - 3].val = aux_data_base;
961  assert(auxv[auxv.size() - 2].type == gem5::auxv::Execfn);
962  auxv[auxv.size() - 2].val = argv_array_base;
963  assert(auxv[auxv.size() - 1].type == gem5::auxv::Platform);
964  auxv[auxv.size() - 1].val = aux_data_base + numRandomBytes;
965 
966 
967  // Copy the aux stuff
968  Addr auxv_array_end = auxv_array_base;
969  for (const auto &aux: auxv) {
970  initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
971  auxv_array_end += sizeof(aux);
972  }
973  // Write out the terminating zeroed auxiliary vector
974  const gem5::auxv::AuxVector<uint64_t> zero(0, 0);
975  initVirtMem->write(auxv_array_end, zero);
976  auxv_array_end += sizeof(zero);
977 
978  initVirtMem->writeString(aux_data_base, platform.c_str());
979 
980  copyStringArray(envp, envp_array_base, env_data_base,
981  ByteOrder::little, *initVirtMem);
982  copyStringArray(argv, argv_array_base, arg_data_base,
983  ByteOrder::little, *initVirtMem);
984 
985  initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
986 
988  // Set the stack pointer register
989  tc->setIntReg(INTREG_RSP, stack_min);
990 
991  // There doesn't need to be any segment base added in since we're dealing
992  // with the flat segmentation model.
993  tc->pcState(getStartPC());
994 
995  // Align the "stack_min" to a page boundary.
996  memState->setStackMin(roundDown(stack_min, pageSize));
997 }
998 
999 void
1001 {
1003  extraAuxvs.emplace_back(auxv::SysinfoEhdr, vsyscallPage.base);
1004  X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1005 }
1006 
1007 void
1009 {
1011  //Tell the binary where the vsyscall part of the vsyscall page is.
1012  extraAuxvs.emplace_back(auxv::Sysinfo,
1014  extraAuxvs.emplace_back(auxv::SysinfoEhdr, vsyscallPage.base);
1015  X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1016 }
1017 
1018 void
1020  Process *p, RegVal flags)
1021 {
1022  X86Process::clone(old_tc, new_tc, p, flags);
1023  ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1024 }
1025 
1026 void
1028  Process *p, RegVal flags)
1029 {
1030  X86Process::clone(old_tc, new_tc, p, flags);
1031  ((I386Process*)p)->vsyscallPage = vsyscallPage;
1032 }
1033 
1034 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::X86ISA::installSegDesc
void installSegDesc(ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode)
Definition: fs_workload.cc:65
gem5::X86ISA::MISCREG_ES
@ MISCREG_ES
Definition: misc.hh:302
gem5::loader::MemoryImage::maxAddr
Addr maxAddr() const
Definition: memory_image.hh:136
gem5::auxv::Platform
@ Platform
Definition: aux_vector.hh:84
gem5::X86ISA::SEGMENT_REG_ES
@ SEGMENT_REG_ES
Definition: segment.hh:48
gem5::Process::euid
uint64_t euid()
Definition: process.hh:83
gem5::X86ISA::I386Process::vsyscallPage
VSyscallPage vsyscallPage
Definition: process.hh:162
gem5::X86ISA::MISCREG_SEG_SEL
static MiscRegIndex MISCREG_SEG_SEL(int index)
Definition: misc.hh:511
gem5::X86ISA::MISCREG_DS
@ MISCREG_DS
Definition: misc.hh:305
gem5::EmulationPageTable
Definition: page_table.hh:52
gem5::loader::ObjectFile
Definition: object_file.hh:85
gem5::auxv::Gid
@ Gid
Definition: aux_vector.hh:82
gem5::X86ISA::MISCREG_TR_EFF_BASE
@ MISCREG_TR_EFF_BASE
Definition: misc.hh:347
gem5::PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:192
gem5::X86ISA::MISCREG_TR
@ MISCREG_TR
Definition: misc.hh:313
gem5::X86ISA::X86_64Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:151
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
system.hh
gem5::Process::clone
virtual void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *new_p, RegVal flags)
Definition: process.cc:166
gem5::Process::getStartPC
Addr getStartPC()
Definition: process.cc:490
gem5::Process::initVirtMem
std::unique_ptr< SETranslatingPortProxy > initVirtMem
Definition: process.hh:174
gem5::loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:125
gem5::X86ISA::MISCREG_TSL
@ MISCREG_TSL
Definition: misc.hh:309
gem5::X86ISA::I386Process::VSyscallPage::size
Addr size
Definition: process.hh:144
gem5::auxv::Random
@ Random
Definition: aux_vector.hh:89
gem5::X86ISA::MISCREG_CR8
@ MISCREG_CR8
Definition: misc.hh:119
gem5::Process::getBias
Addr getBias()
Definition: process.cc:482
gem5::X86ISA::MISCREG_APIC_BASE
@ MISCREG_APIC_BASE
Definition: misc.hh:399
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:332
gem5::X86ISA::MISCREG_TSG_LIMIT
@ MISCREG_TSG_LIMIT
Definition: misc.hh:360
gem5::X86ISA::MISCREG_SEG_LIMIT
static MiscRegIndex MISCREG_SEG_LIMIT(int index)
Definition: misc.hh:532
gem5::X86ISA::PFHandlerVirtAddr
const Addr PFHandlerVirtAddr
Definition: se_workload.hh:46
gem5::auxv::Hwcap
@ Hwcap
Definition: aux_vector.hh:85
gem5::X86ISA::MISCREG_SEG_ATTR
static MiscRegIndex MISCREG_SEG_ATTR(int index)
Definition: misc.hh:539
gem5::X86ISA::X86Process::_gdtSize
Addr _gdtSize
Definition: process.hh:71
gem5::loader::ElfObject
Definition: elf_object.hh:64
gem5::Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:287
gem5::ArchPageTable
MultiLevelPageTable< LongModePTE< 47, 39 >, LongModePTE< 38, 30 >, LongModePTE< 29, 21 >, LongModePTE< 20, 12 > > ArchPageTable
Definition: process.cc:81
gem5::X86ISA::I386Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:596
process_impl.hh
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::X86ISA::I386Process::argsInit
void argsInit(int pageSize)
Definition: process.cc:1008
gem5::Process::egid
uint64_t egid()
Definition: process.hh:85
std::vector
STL vector class.
Definition: stl.hh:37
gem5::X86ISA::MISCREG_TR_BASE
@ MISCREG_TR_BASE
Definition: misc.hh:329
gem5::X86ISA::MISCREG_STAR
@ MISCREG_STAR
Definition: misc.hh:253
gem5::auxv::Phent
@ Phent
Definition: aux_vector.hh:73
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::X86ISA::MISCREG_IDTR_BASE
@ MISCREG_IDTR_BASE
Definition: misc.hh:330
gem5::X86ISA::X86_64Process::VSyscallPage::size
Addr size
Definition: process.hh:106
gem5::Process::gid
uint64_t gid()
Definition: process.hh:84
gem5::X86ISA::MISCREG_GS
@ MISCREG_GS
Definition: misc.hh:307
gem5::X86ISA::MISCREG_TSG_EFF_BASE
@ MISCREG_TSG_EFF_BASE
Definition: misc.hh:344
gem5::X86ISA::SEGMENT_REG_CS
@ SEGMENT_REG_CS
Definition: segment.hh:49
gem5::X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:114
gem5::Process::useForClone
bool useForClone
Definition: process.hh:169
gem5::Process::memState
std::shared_ptr< MemState > memState
Definition: process.hh:276
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
gem5::Process::allocateMem
void allocateMem(Addr vaddr, int64_t size, bool clobber=false)
Definition: process.cc:316
gem5::X86ISA::I386Process
Definition: process.hh:137
gem5::X86ISA::X86Process
Definition: process.hh:67
gem5::X86ISA::X86_64Process::argsInit
void argsInit(int pageSize)
Definition: process.cc:1000
gem5::X86ISA::TSSVirtAddr
const Addr TSSVirtAddr
Definition: se_workload.hh:43
gem5::X86ISA::MISCREG_SF_MASK
@ MISCREG_SF_MASK
Definition: misc.hh:257
gem5::X86ISA::MISCREG_CR2
@ MISCREG_CR2
Definition: misc.hh:113
gem5::Process::uid
uint64_t uid()
Definition: process.hh:82
gem5::X86ISA::auxv::SysinfoEhdr
@ SysinfoEhdr
Definition: process.hh:62
gem5::X86ISA::MISCREG_LSTAR
@ MISCREG_LSTAR
Definition: misc.hh:254
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:76
gem5::auxv::Pagesz
@ Pagesz
Definition: aux_vector.hh:75
elf_object.hh
gem5::X86ISA::MISCREG_IDTR_LIMIT
@ MISCREG_IDTR_LIMIT
Definition: misc.hh:364
gem5::high
high
Definition: intmath.hh:176
gem5::X86ISA::X86_64Process::clone
void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process, RegVal flags) override
Definition: process.cc:1019
syscall_return.hh
gem5::auxv::Secure
@ Secure
Definition: aux_vector.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
multi_level_page_table.hh
gem5::X86ISA::NUM_SEGMENTREGS
@ NUM_SEGMENTREGS
Definition: segment.hh:65
gem5::X86ISA::SEGMENT_REG_GS
@ SEGMENT_REG_GS
Definition: segment.hh:53
gem5::auxv::Clktck
@ Clktck
Definition: aux_vector.hh:86
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:171
gem5::X86ISA::I386Process::clone
void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process, RegVal flags) override
Definition: process.cc:1027
gem5::copyStringArray
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:43
segment.hh
gem5::auxv::AuxVector
Definition: aux_vector.hh:45
gem5::auxv::Phdr
@ Phdr
Definition: aux_vector.hh:72
gem5::X86ISA::I386Process::VSyscallPage::vsysexitOffset
Addr vsysexitOffset
Definition: process.hh:146
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:115
gem5::Process::argv
std::vector< std::string > argv
Definition: process.hh:213
gem5::X86ISA::SEGMENT_REG_DS
@ SEGMENT_REG_DS
Definition: segment.hh:51
page_size.hh
gem5::X86ISA::MISCREG_CS_ATTR
@ MISCREG_CS_ATTR
Definition: misc.hh:369
gem5::X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:251
gem5::X86ISA::SEGMENT_REG_SS
@ SEGMENT_REG_SS
Definition: segment.hh:50
gem5::X86ISA::I386Process::VSyscallPage::vsyscallOffset
Addr vsyscallOffset
Definition: process.hh:145
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::MISCREG_SEG_BASE
static MiscRegIndex MISCREG_SEG_BASE(int index)
Definition: misc.hh:518
gem5::X86ISA::X86_64Process::VSyscallPage::vgettimeofdayOffset
Addr vgettimeofdayOffset
Definition: process.hh:108
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::X86ISA::MISCREG_FS
@ MISCREG_FS
Definition: misc.hh:306
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::X86ISA::MISCREG_TSL_ATTR
@ MISCREG_TSL_ATTR
Definition: misc.hh:375
gem5::System::allocPhysPages
Addr allocPhysPages(int npages, int poolID=0)
Allocate npages contiguous unused physical pages.
Definition: system.cc:355
gem5::auxv::Egid
@ Egid
Definition: aux_vector.hh:83
gem5::auxv::Entry
@ Entry
Definition: aux_vector.hh:78
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::MISCREG_SS
@ MISCREG_SS
Definition: misc.hh:304
gem5::Process::envp
std::vector< std::string > envp
Definition: process.hh:214
gem5::X86ISA::MISCREG_MXCSR
@ MISCREG_MXCSR
Definition: misc.hh:386
gem5::MipsISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:238
gem5::auxv::Phnum
@ Phnum
Definition: aux_vector.hh:74
se_workload.hh
name
const std::string & name()
Definition: trace.cc:49
gem5::X86ISA::X86_64Process::X86_64Process
X86_64Process(const ProcessParams &params, loader::ObjectFile *objFile)
Definition: process.cc:103
gem5::MultiLevelPageTable
Definition: multi_level_page_table.hh:183
gem5::Process
Definition: process.hh:67
gem5::X86ISA::MISCREG_CS
@ MISCREG_CS
Definition: misc.hh:303
gem5::auxv::Execfn
@ Execfn
Definition: aux_vector.hh:91
gem5::X86ISA::X86_64Process::VSyscallPage::vtimeOffset
Addr vtimeOffset
Definition: process.hh:107
gem5::X86ISA::MISCREG_TSG_BASE
@ MISCREG_TSG_BASE
Definition: misc.hh:326
gem5::X86ISA::X86_64Process::vsyscallPage
VSyscallPage vsyscallPage
Definition: process.hh:124
gem5::EmulationPageTable::map
virtual void map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags=0)
Maps a virtual memory region to a physical memory region.
Definition: page_table.cc:48
gem5::X86ISA::MISCREG_TR_LIMIT
@ MISCREG_TR_LIMIT
Definition: misc.hh:363
gem5::X86ISA::LongModePTE
Definition: pagetable.hh:155
gem5::X86ISA::X86_64Process::VSyscallPage::base
Addr base
Definition: process.hh:105
gem5::X86ISA::X86Process::X86Process
X86Process(const ProcessParams &params, loader::ObjectFile *objFile)
Definition: process.cc:83
aux_vector.hh
process.hh
gem5::X86ISA::SEGMENT_REG_FS
@ SEGMENT_REG_FS
Definition: segment.hh:52
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::X86ISA::MISCREG_SEG_EFF_BASE
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:525
gem5::X86ISA::ISTVirtAddr
const Addr ISTVirtAddr
Definition: se_workload.hh:45
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::X86Process::argsInit
void argsInit(int pageSize, std::vector< gem5::auxv::AuxVector< IntType >> extraAuxvs)
Definition: process.cc:716
gem5::X86ISA::X86Process::clone
void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process, RegVal flags) override
Definition: process.cc:95
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::auxv::Uid
@ Uid
Definition: aux_vector.hh:80
gem5::X86ISA::MISCREG_CR0
@ MISCREG_CR0
Definition: misc.hh:111
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
logging.hh
gem5::Process::system
System * system
Definition: process.hh:162
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::X86ISA::MMIORegionPhysAddr
const Addr MMIORegionPhysAddr
Definition: se_workload.hh:48
gem5::auxv::Euid
@ Euid
Definition: aux_vector.hh:81
gem5::X86ISA::MISCREG_TR_ATTR
@ MISCREG_TR_ATTR
Definition: misc.hh:379
gem5::Process::contextIds
std::vector< ContextID > contextIds
Definition: process.hh:159
trace.hh
gem5::X86ISA::X86_64Process
Definition: process.hh:99
gem5::X86ISA::MMIORegionVirtAddr
const Addr MMIORegionVirtAddr
Definition: se_workload.hh:47
fs_workload.hh
gem5::X86ISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:49
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::I386Process::VSyscallPage::base
Addr base
Definition: process.hh:143
gem5::auxv::Flags
@ Flags
Definition: aux_vector.hh:77
gem5::X86ISA::X86Process::_gdtStart
Addr _gdtStart
Definition: process.hh:70
misc.hh
gem5::Process::kvmInSE
bool kvmInSE
Definition: process.hh:167
gem5::X86ISA::syscallCodeVirtAddr
const Addr syscallCodeVirtAddr
Definition: se_workload.hh:40
object_file.hh
types.hh
gem5::Process::image
loader::MemoryImage image
Definition: process.hh:211
thread_context.hh
gem5::Process::objFile
loader::ObjectFile * objFile
Definition: process.hh:210
gem5::X86ISA::GDTVirtAddr
const Addr GDTVirtAddr
Definition: se_workload.hh:41
gem5::X86ISA::auxv::Sysinfo
@ Sysinfo
Definition: process.hh:61
syscall_desc.hh
byteswap.hh
gem5::X86ISA::I386Process::I386Process
I386Process(const ProcessParams &params, loader::ObjectFile *objFile)
Definition: process.cc:124
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::IDTVirtAddr
const Addr IDTVirtAddr
Definition: se_workload.hh:42

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