gem5  v22.0.0.2
process.cc
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1 /*
2  * Copyright (c) 2014 Advanced Micro Devices, Inc.
3  * Copyright (c) 2007 The Hewlett-Packard Development Company
4  * All rights reserved.
5  *
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41 
42 #include "arch/x86/process.hh"
43 
44 #include <string>
45 #include <vector>
46 
47 #include "arch/x86/fs_workload.hh"
48 #include "arch/x86/page_size.hh"
49 #include "arch/x86/regs/int.hh"
50 #include "arch/x86/regs/misc.hh"
51 #include "arch/x86/regs/segment.hh"
52 #include "arch/x86/se_workload.hh"
53 #include "arch/x86/types.hh"
56 #include "base/logging.hh"
57 #include "base/trace.hh"
58 #include "cpu/thread_context.hh"
59 #include "debug/Stack.hh"
61 #include "mem/page_table.hh"
62 #include "params/Process.hh"
63 #include "sim/aux_vector.hh"
64 #include "sim/byteswap.hh"
65 #include "sim/process_impl.hh"
66 #include "sim/syscall_desc.hh"
67 #include "sim/syscall_return.hh"
68 #include "sim/system.hh"
69 
70 namespace gem5
71 {
72 
73 using namespace X86ISA;
74 
75 template class MultiLevelPageTable<LongModePTE<47, 39>,
76  LongModePTE<38, 30>,
77  LongModePTE<29, 21>,
78  LongModePTE<20, 12> >;
79 typedef MultiLevelPageTable<LongModePTE<47, 39>,
80  LongModePTE<38, 30>,
81  LongModePTE<29, 21>,
83 
84 X86Process::X86Process(const ProcessParams &params,
85  loader::ObjectFile *objFile) :
86  Process(params, params.useArchPT ?
87  static_cast<EmulationPageTable *>(
88  new ArchPageTable(params.name, params.pid,
89  params.system, PageBytes)) :
90  new EmulationPageTable(params.name, params.pid,
91  PageBytes),
92  objFile)
93 {
94 }
95 
98 {
99  Process::clone(old_tc, new_tc, p, flags);
100  X86Process *process = (X86Process*)p;
101  *process = *this;
102 }
103 
104 X86_64Process::X86_64Process(const ProcessParams &params,
105  loader::ObjectFile *objFile) :
106  X86Process(params, objFile)
107 {
108  vsyscallPage.base = 0xffffffffff600000ULL;
110  vsyscallPage.vtimeOffset = 0x400;
112 
113  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
114  Addr stack_base = 0x7FFFFFFFF000ULL;
115  Addr max_stack_size = 8 * 1024 * 1024;
116  Addr next_thread_stack_base = stack_base - max_stack_size;
117  Addr mmap_end = 0x7FFFF7FFF000ULL;
118 
119  memState = std::make_shared<MemState>(
120  this, brk_point, stack_base, max_stack_size,
121  next_thread_stack_base, mmap_end);
122 }
123 
124 
125 I386Process::I386Process(const ProcessParams &params,
126  loader::ObjectFile *objFile) :
127  X86Process(params, objFile)
128 {
129  if (kvmInSE)
130  panic("KVM CPU model does not support 32 bit processes");
131 
132  _gdtStart = 0xffffd000ULL;
134 
135  vsyscallPage.base = 0xffffe000ULL;
139 
140  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
141  Addr stack_base = _gdtStart;
142  Addr max_stack_size = 8 * 1024 * 1024;
143  Addr next_thread_stack_base = stack_base - max_stack_size;
144  Addr mmap_end = 0xB7FFF000ULL;
145 
146  memState = std::make_shared<MemState>(
147  this, brk_point, stack_base, max_stack_size,
148  next_thread_stack_base, mmap_end);
149 }
150 
151 void
153 {
155 
156  if (useForClone)
157  return;
158 
160 
161  // Set up the vsyscall page for this process.
162  memState->mapRegion(vsyscallPage.base, vsyscallPage.size, "vsyscall");
163  uint8_t vtimeBlob[] = {
164  0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
165  0x0f,0x05, // syscall
166  0xc3 // retq
167  };
169  vtimeBlob, sizeof(vtimeBlob));
170 
171  uint8_t vgettimeofdayBlob[] = {
172  0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
173  0x0f,0x05, // syscall
174  0xc3 // retq
175  };
176  initVirtMem->writeBlob(
178  vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
179 
180  if (kvmInSE) {
181  PortProxy physProxy = system->physProxy;
182 
183  Addr syscallCodePhysAddr = seWorkload->allocPhysPages(1);
184  Addr gdtPhysAddr = seWorkload->allocPhysPages(1);
185  Addr idtPhysAddr = seWorkload->allocPhysPages(1);
186  Addr istPhysAddr = seWorkload->allocPhysPages(1);
187  Addr tssPhysAddr = seWorkload->allocPhysPages(1);
188  Addr pfHandlerPhysAddr = seWorkload->allocPhysPages(1);
189 
190  /*
191  * Set up the gdt.
192  */
193  uint8_t numGDTEntries = 0;
194  uint64_t nullDescriptor = 0;
195  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
196  &nullDescriptor, 8);
197  numGDTEntries++;
198 
199  SegDescriptor initDesc = 0;
200  initDesc.type.codeOrData = 0; // code or data type
201  initDesc.type.c = 0; // conforming
202  initDesc.type.r = 1; // readable
203  initDesc.dpl = 0; // privilege
204  initDesc.p = 1; // present
205  initDesc.l = 1; // longmode - 64 bit
206  initDesc.d = 0; // operand size
207  initDesc.g = 1;
208  initDesc.s = 1; // system segment
209  initDesc.limit = 0xFFFFFFFF;
210  initDesc.base = 0;
211 
212  //64 bit code segment
213  SegDescriptor csLowPLDesc = initDesc;
214  csLowPLDesc.type.codeOrData = 1;
215  csLowPLDesc.dpl = 0;
216  uint64_t csLowPLDescVal = csLowPLDesc;
217  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
218  &csLowPLDescVal, 8);
219 
220  numGDTEntries++;
221 
222  SegSelector csLowPL = 0;
223  csLowPL.si = numGDTEntries - 1;
224  csLowPL.rpl = 0;
225 
226  //64 bit data segment
227  SegDescriptor dsLowPLDesc = initDesc;
228  dsLowPLDesc.type.codeOrData = 0;
229  dsLowPLDesc.dpl = 0;
230  uint64_t dsLowPLDescVal = dsLowPLDesc;
231  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
232  &dsLowPLDescVal, 8);
233 
234  numGDTEntries++;
235 
236  SegSelector dsLowPL = 0;
237  dsLowPL.si = numGDTEntries - 1;
238  dsLowPL.rpl = 0;
239 
240  //64 bit data segment
241  SegDescriptor dsDesc = initDesc;
242  dsDesc.type.codeOrData = 0;
243  dsDesc.dpl = 3;
244  uint64_t dsDescVal = dsDesc;
245  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
246  &dsDescVal, 8);
247 
248  numGDTEntries++;
249 
250  SegSelector ds = 0;
251  ds.si = numGDTEntries - 1;
252  ds.rpl = 3;
253 
254  //64 bit code segment
255  SegDescriptor csDesc = initDesc;
256  csDesc.type.codeOrData = 1;
257  csDesc.dpl = 3;
258  uint64_t csDescVal = csDesc;
259  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
260  &csDescVal, 8);
261 
262  numGDTEntries++;
263 
264  SegSelector cs = 0;
265  cs.si = numGDTEntries - 1;
266  cs.rpl = 3;
267 
268  SegSelector scall = 0;
269  scall.si = csLowPL.si;
270  scall.rpl = 0;
271 
272  SegSelector sret = 0;
273  sret.si = dsLowPL.si;
274  sret.rpl = 3;
275 
276  /* In long mode the TSS has been extended to 16 Bytes */
277  TSSlow TSSDescLow = 0;
278  TSSDescLow.type = 0xB;
279  TSSDescLow.dpl = 0; // Privelege level 0
280  TSSDescLow.p = 1; // Present
281  TSSDescLow.limit = 0xFFFFFFFF;
282  TSSDescLow.base = bits(TSSVirtAddr, 31, 0);
283 
284  TSShigh TSSDescHigh = 0;
285  TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
286 
287  struct TSSDesc
288  {
289  uint64_t low;
290  uint64_t high;
291  } tssDescVal = {TSSDescLow, TSSDescHigh};
292 
293  physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
294  &tssDescVal, sizeof(tssDescVal));
295 
296  numGDTEntries++;
297 
298  SegSelector tssSel = 0;
299  tssSel.si = numGDTEntries - 1;
300 
301  uint64_t tss_base_addr = (TSSDescHigh.base << 32) | TSSDescLow.base;
302  uint64_t tss_limit = TSSDescLow.limit;
303 
304  SegAttr tss_attr = 0;
305 
306  tss_attr.type = TSSDescLow.type;
307  tss_attr.dpl = TSSDescLow.dpl;
308  tss_attr.present = TSSDescLow.p;
309  tss_attr.granularity = TSSDescLow.g;
310  tss_attr.unusable = 0;
311 
312  for (int i = 0; i < contextIds.size(); i++) {
314 
315  tc->setMiscReg(misc_reg::Cs, cs);
316  tc->setMiscReg(misc_reg::Ds, ds);
317  tc->setMiscReg(misc_reg::Es, ds);
318  tc->setMiscReg(misc_reg::Fs, ds);
319  tc->setMiscReg(misc_reg::Gs, ds);
320  tc->setMiscReg(misc_reg::Ss, ds);
321 
322  // LDT
323  tc->setMiscReg(misc_reg::Tsl, 0);
324  SegAttr tslAttr = 0;
325  tslAttr.unusable = 1;
326  tslAttr.present = 0;
327  tslAttr.type = 2;
328  tc->setMiscReg(misc_reg::TslAttr, tslAttr);
329 
331  tc->setMiscReg(misc_reg::TsgLimit, 8 * numGDTEntries - 1);
332 
333  tc->setMiscReg(misc_reg::Tr, tssSel);
334  tc->setMiscReg(misc_reg::TrBase, tss_base_addr);
335  tc->setMiscReg(misc_reg::TrEffBase, tss_base_addr);
336  tc->setMiscReg(misc_reg::TrLimit, tss_limit);
337  tc->setMiscReg(misc_reg::TrAttr, tss_attr);
338 
339  //Start using longmode segments.
340  installSegDesc(tc, segment_idx::Cs, csDesc, true);
341  installSegDesc(tc, segment_idx::Ds, dsDesc, true);
342  installSegDesc(tc, segment_idx::Es, dsDesc, true);
343  installSegDesc(tc, segment_idx::Fs, dsDesc, true);
344  installSegDesc(tc, segment_idx::Gs, dsDesc, true);
345  installSegDesc(tc, segment_idx::Ss, dsDesc, true);
346 
347  Efer efer = 0;
348  efer.sce = 1; // Enable system call extensions.
349  efer.lme = 1; // Enable long mode.
350  efer.lma = 1; // Activate long mode.
351  efer.nxe = 1; // Enable nx support.
352  efer.svme = 0; // Disable svm support for now.
353  efer.ffxsr = 0; // Disable fast fxsave and fxrstor.
354  tc->setMiscReg(misc_reg::Efer, efer);
355 
356  //Set up the registers that describe the operating mode.
357  CR0 cr0 = 0;
358  cr0.pg = 1; // Turn on paging.
359  cr0.cd = 0; // Don't disable caching.
360  cr0.nw = 0; // This is bit is defined to be ignored.
361  cr0.am = 0; // No alignment checking
362  cr0.wp = 0; // Supervisor mode can write read only pages
363  cr0.ne = 1;
364  cr0.et = 1; // This should always be 1
365  cr0.ts = 0; // We don't do task switching, so causing fp exceptions
366  // would be pointless.
367  cr0.em = 0; // Allow x87 instructions to execute natively.
368  cr0.mp = 1; // This doesn't really matter, but the manual suggests
369  // setting it to one.
370  cr0.pe = 1; // We're definitely in protected mode.
371  tc->setMiscReg(misc_reg::Cr0, cr0);
372 
373  CR0 cr2 = 0;
374  tc->setMiscReg(misc_reg::Cr2, cr2);
375 
376  CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
377  tc->setMiscReg(misc_reg::Cr3, cr3);
378 
379  CR4 cr4 = 0;
380  //Turn on pae.
381  cr4.osxsave = 0; // Disable XSAVE and Proc Extended States
382  cr4.osxmmexcpt = 0; // Operating System Unmasked Exception
383  cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
384  cr4.pce = 0; // Performance-Monitoring Counter Enable
385  cr4.pge = 0; // Page-Global Enable
386  cr4.mce = 0; // Machine Check Enable
387  cr4.pae = 1; // Physical-Address Extension
388  cr4.pse = 0; // Page Size Extensions
389  cr4.de = 0; // Debugging Extensions
390  cr4.tsd = 0; // Time Stamp Disable
391  cr4.pvi = 0; // Protected-Mode Virtual Interrupts
392  cr4.vme = 0; // Virtual-8086 Mode Extensions
393 
394  tc->setMiscReg(misc_reg::Cr4, cr4);
395 
396  CR8 cr8 = 0;
397  tc->setMiscReg(misc_reg::Cr8, cr8);
398 
399  tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
400 
401  tc->setMiscReg(misc_reg::ApicBase, 0xfee00900);
402 
404  tc->setMiscReg(misc_reg::TsgLimit, 0xffff);
405 
407  tc->setMiscReg(misc_reg::IdtrLimit, 0xffff);
408 
409  /* enabling syscall and sysret */
410  RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
411  tc->setMiscReg(misc_reg::Star, star);
413  tc->setMiscReg(misc_reg::Lstar, lstar);
414  RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
415  tc->setMiscReg(misc_reg::SfMask, sfmask);
416  }
417 
418  /* Set up the content of the TSS and write it to physical memory. */
419 
420  struct
421  {
422  uint32_t reserved0; // +00h
423  uint32_t RSP0_low; // +04h
424  uint32_t RSP0_high; // +08h
425  uint32_t RSP1_low; // +0Ch
426  uint32_t RSP1_high; // +10h
427  uint32_t RSP2_low; // +14h
428  uint32_t RSP2_high; // +18h
429  uint32_t reserved1; // +1Ch
430  uint32_t reserved2; // +20h
431  uint32_t IST1_low; // +24h
432  uint32_t IST1_high; // +28h
433  uint32_t IST2_low; // +2Ch
434  uint32_t IST2_high; // +30h
435  uint32_t IST3_low; // +34h
436  uint32_t IST3_high; // +38h
437  uint32_t IST4_low; // +3Ch
438  uint32_t IST4_high; // +40h
439  uint32_t IST5_low; // +44h
440  uint32_t IST5_high; // +48h
441  uint32_t IST6_low; // +4Ch
442  uint32_t IST6_high; // +50h
443  uint32_t IST7_low; // +54h
444  uint32_t IST7_high; // +58h
445  uint32_t reserved3; // +5Ch
446  uint32_t reserved4; // +60h
447  uint16_t reserved5; // +64h
448  uint16_t IO_MapBase; // +66h
449  } tss;
450 
452  uint64_t IST_start = ISTVirtAddr + PageBytes;
453  tss.IST1_low = IST_start;
454  tss.IST1_high = IST_start >> 32;
455  tss.RSP0_low = tss.IST1_low;
456  tss.RSP0_high = tss.IST1_high;
457  tss.RSP1_low = tss.IST1_low;
458  tss.RSP1_high = tss.IST1_high;
459  tss.RSP2_low = tss.IST1_low;
460  tss.RSP2_high = tss.IST1_high;
461  physProxy.writeBlob(tssPhysAddr, &tss, sizeof(tss));
462 
463  /* Setting IDT gates */
464  GateDescriptorLow PFGateLow = 0;
465  PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
466  PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
467  PFGateLow.selector = csLowPL;
468  PFGateLow.p = 1;
469  PFGateLow.dpl = 0;
470  PFGateLow.type = 0xe; // gate interrupt type
471  PFGateLow.IST = 0; // setting IST to 0 and using RSP0
472 
473  GateDescriptorHigh PFGateHigh = 0;
474  PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
475 
476  struct
477  {
478  uint64_t low;
479  uint64_t high;
480  } PFGate = {PFGateLow, PFGateHigh};
481 
482  physProxy.writeBlob(idtPhysAddr + 0xE0, &PFGate, sizeof(PFGate));
483 
484  /* System call handler */
485  uint8_t syscallBlob[] = {
486  // mov %rax, (0xffffc90000007000)
487  0x48, 0xa3, 0x00, 0x70, 0x00,
488  0x00, 0x00, 0xc9, 0xff, 0xff,
489  // sysret
490  0x48, 0x0f, 0x07
491  };
492 
493  physProxy.writeBlob(syscallCodePhysAddr,
494  syscallBlob, sizeof(syscallBlob));
495 
497  uint8_t faultBlob[] = {
498  // mov %rax, (0xffffc90000007000)
499  0x48, 0xa3, 0x00, 0x70, 0x00,
500  0x00, 0x00, 0xc9, 0xff, 0xff,
501  // add $0x8, %rsp # skip error
502  0x48, 0x83, 0xc4, 0x08,
503  // iretq
504  0x48, 0xcf
505  };
506 
507  physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
508 
509  /* Syscall handler */
510  pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
511  PageBytes, false);
512  /* GDT */
513  pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
514  /* IDT */
515  pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
516  /* TSS */
517  pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
518  /* IST */
519  pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
520  /* PF handler */
521  pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
522  /* MMIO region for m5ops */
523  auto m5op_range = system->m5opRange();
524  if (m5op_range.size()) {
525  pTable->map(MMIORegionVirtAddr, m5op_range.start(),
526  m5op_range.size(), false);
527  }
528  } else {
529  for (int i = 0; i < contextIds.size(); i++) {
531 
532  SegAttr dataAttr = 0;
533  dataAttr.dpl = 3;
534  dataAttr.unusable = 0;
535  dataAttr.defaultSize = 1;
536  dataAttr.longMode = 1;
537  dataAttr.avl = 0;
538  dataAttr.granularity = 1;
539  dataAttr.present = 1;
540  dataAttr.type = 3;
541  dataAttr.writable = 1;
542  dataAttr.readable = 1;
543  dataAttr.expandDown = 0;
544  dataAttr.system = 1;
545 
546  // Initialize the segment registers.
547  for (int seg = 0; seg < segment_idx::NumIdxs; seg++) {
550  tc->setMiscRegNoEffect(misc_reg::segAttr(seg), dataAttr);
551  }
552 
553  SegAttr csAttr = 0;
554  csAttr.dpl = 3;
555  csAttr.unusable = 0;
556  csAttr.defaultSize = 0;
557  csAttr.longMode = 1;
558  csAttr.avl = 0;
559  csAttr.granularity = 1;
560  csAttr.present = 1;
561  csAttr.type = 10;
562  csAttr.writable = 0;
563  csAttr.readable = 1;
564  csAttr.expandDown = 0;
565  csAttr.system = 1;
566 
568 
569  Efer efer = 0;
570  efer.sce = 1; // Enable system call extensions.
571  efer.lme = 1; // Enable long mode.
572  efer.lma = 1; // Activate long mode.
573  efer.nxe = 1; // Enable nx support.
574  efer.svme = 0; // Disable svm support for now. It isn't implemented.
575  efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
576  tc->setMiscReg(misc_reg::Efer, efer);
577 
578  // Set up the registers that describe the operating mode.
579  CR0 cr0 = 0;
580  cr0.pg = 1; // Turn on paging.
581  cr0.cd = 0; // Don't disable caching.
582  cr0.nw = 0; // This is bit is defined to be ignored.
583  cr0.am = 0; // No alignment checking
584  cr0.wp = 0; // Supervisor mode can write read only pages
585  cr0.ne = 1;
586  cr0.et = 1; // This should always be 1
587  cr0.ts = 0; // We don't do task switching, so causing fp exceptions
588  // would be pointless.
589  cr0.em = 0; // Allow x87 instructions to execute natively.
590  cr0.mp = 1; // This doesn't really matter, but the manual suggests
591  // setting it to one.
592  cr0.pe = 1; // We're definitely in protected mode.
593  tc->setMiscReg(misc_reg::Cr0, cr0);
594 
595  tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
596  }
597  }
598 }
599 
600 void
602 {
604 
606 
607  /*
608  * Set up a GDT for this process. The whole GDT wouldn't really be for
609  * this process, but the only parts we care about are.
610  */
612  uint64_t zero = 0;
613  assert(_gdtSize % sizeof(zero) == 0);
614  for (Addr gdtCurrent = _gdtStart;
615  gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
616  initVirtMem->write(gdtCurrent, zero);
617  }
618 
619  // Set up the vsyscall page for this process.
620  memState->mapRegion(vsyscallPage.base, vsyscallPage.size, "vsyscall");
621  uint8_t vsyscallBlob[] = {
622  0x51, // push %ecx
623  0x52, // push %edp
624  0x55, // push %ebp
625  0x89, 0xe5, // mov %esp, %ebp
626  0x0f, 0x34 // sysenter
627  };
629  vsyscallBlob, sizeof(vsyscallBlob));
630 
631  uint8_t vsysexitBlob[] = {
632  0x5d, // pop %ebp
633  0x5a, // pop %edx
634  0x59, // pop %ecx
635  0xc3 // ret
636  };
638  vsysexitBlob, sizeof(vsysexitBlob));
639 
640  for (int i = 0; i < contextIds.size(); i++) {
642 
643  SegAttr dataAttr = 0;
644  dataAttr.dpl = 3;
645  dataAttr.unusable = 0;
646  dataAttr.defaultSize = 1;
647  dataAttr.longMode = 0;
648  dataAttr.avl = 0;
649  dataAttr.granularity = 1;
650  dataAttr.present = 1;
651  dataAttr.type = 3;
652  dataAttr.writable = 1;
653  dataAttr.readable = 1;
654  dataAttr.expandDown = 0;
655  dataAttr.system = 1;
656 
657  // Initialize the segment registers.
658  for (int seg = 0; seg < segment_idx::NumIdxs; seg++) {
661  tc->setMiscRegNoEffect(misc_reg::segAttr(seg), dataAttr);
663  tc->setMiscRegNoEffect(misc_reg::segLimit(seg), (uint32_t)(-1));
664  }
665 
666  SegAttr csAttr = 0;
667  csAttr.dpl = 3;
668  csAttr.unusable = 0;
669  csAttr.defaultSize = 1;
670  csAttr.longMode = 0;
671  csAttr.avl = 0;
672  csAttr.granularity = 1;
673  csAttr.present = 1;
674  csAttr.type = 0xa;
675  csAttr.writable = 0;
676  csAttr.readable = 1;
677  csAttr.expandDown = 0;
678  csAttr.system = 1;
679 
681 
685 
686  // Set the LDT selector to 0 to deactivate it.
688  SegAttr attr = 0;
689  attr.unusable = 1;
691 
692  Efer efer = 0;
693  efer.sce = 1; // Enable system call extensions.
694  efer.lme = 1; // Enable long mode.
695  efer.lma = 0; // Deactivate long mode.
696  efer.nxe = 1; // Enable nx support.
697  efer.svme = 0; // Disable svm support for now. It isn't implemented.
698  efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
699  tc->setMiscReg(misc_reg::Efer, efer);
700 
701  // Set up the registers that describe the operating mode.
702  CR0 cr0 = 0;
703  cr0.pg = 1; // Turn on paging.
704  cr0.cd = 0; // Don't disable caching.
705  cr0.nw = 0; // This is bit is defined to be ignored.
706  cr0.am = 0; // No alignment checking
707  cr0.wp = 0; // Supervisor mode can write read only pages
708  cr0.ne = 1;
709  cr0.et = 1; // This should always be 1
710  cr0.ts = 0; // We don't do task switching, so causing fp exceptions
711  // would be pointless.
712  cr0.em = 0; // Allow x87 instructions to execute natively.
713  cr0.mp = 1; // This doesn't really matter, but the manual suggests
714  // setting it to one.
715  cr0.pe = 1; // We're definitely in protected mode.
716  tc->setMiscReg(misc_reg::Cr0, cr0);
717 
718  tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
719  }
720 }
721 
722 template<class IntType>
723 void
724 X86Process::argsInit(int pageSize,
726 {
727  int intSize = sizeof(IntType);
728 
730 
731  std::string filename;
732  if (argv.size() < 1)
733  filename = "";
734  else
735  filename = argv[0];
736 
737  // We want 16 byte alignment
738  uint64_t align = 16;
739 
740  enum X86CpuFeature
741  {
742  X86_OnboardFPU = 1 << 0,
743  X86_VirtualModeExtensions = 1 << 1,
744  X86_DebuggingExtensions = 1 << 2,
745  X86_PageSizeExtensions = 1 << 3,
746 
747  X86_TimeStampCounter = 1 << 4,
748  X86_ModelSpecificRegisters = 1 << 5,
749  X86_PhysicalAddressExtensions = 1 << 6,
750  X86_MachineCheckExtensions = 1 << 7,
751 
752  X86_CMPXCHG8Instruction = 1 << 8,
753  X86_OnboardAPIC = 1 << 9,
754  X86_SYSENTER_SYSEXIT = 1 << 11,
755 
756  X86_MemoryTypeRangeRegisters = 1 << 12,
757  X86_PageGlobalEnable = 1 << 13,
758  X86_MachineCheckArchitecture = 1 << 14,
759  X86_CMOVInstruction = 1 << 15,
760 
761  X86_PageAttributeTable = 1 << 16,
762  X86_36BitPSEs = 1 << 17,
763  X86_ProcessorSerialNumber = 1 << 18,
764  X86_CLFLUSHInstruction = 1 << 19,
765 
766  X86_DebugTraceStore = 1 << 21,
767  X86_ACPIViaMSR = 1 << 22,
768  X86_MultimediaExtensions = 1 << 23,
769 
770  X86_FXSAVE_FXRSTOR = 1 << 24,
771  X86_StreamingSIMDExtensions = 1 << 25,
772  X86_StreamingSIMDExtensions2 = 1 << 26,
773  X86_CPUSelfSnoop = 1 << 27,
774 
775  X86_HyperThreading = 1 << 28,
776  X86_AutomaticClockControl = 1 << 29,
777  X86_IA64Processor = 1 << 30
778  };
779 
780  // Setup the auxiliary vectors. These will already have endian
781  // conversion. Auxiliary vectors are loaded only for elf formatted
782  // executables; the auxv is responsible for passing information from
783  // the OS to the interpreter.
784  auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
785  if (elfObject) {
786  uint64_t features =
787  X86_OnboardFPU |
788  X86_VirtualModeExtensions |
789  X86_DebuggingExtensions |
790  X86_PageSizeExtensions |
791  X86_TimeStampCounter |
792  X86_ModelSpecificRegisters |
793  X86_PhysicalAddressExtensions |
794  X86_MachineCheckExtensions |
795  X86_CMPXCHG8Instruction |
796  X86_OnboardAPIC |
797  X86_SYSENTER_SYSEXIT |
798  X86_MemoryTypeRangeRegisters |
799  X86_PageGlobalEnable |
800  X86_MachineCheckArchitecture |
801  X86_CMOVInstruction |
802  X86_PageAttributeTable |
803  X86_36BitPSEs |
804 // X86_ProcessorSerialNumber |
805  X86_CLFLUSHInstruction |
806 // X86_DebugTraceStore |
807 // X86_ACPIViaMSR |
808  X86_MultimediaExtensions |
809  X86_FXSAVE_FXRSTOR |
810  X86_StreamingSIMDExtensions |
811  X86_StreamingSIMDExtensions2 |
812 // X86_CPUSelfSnoop |
813 // X86_HyperThreading |
814 // X86_AutomaticClockControl |
815 // X86_IA64Processor |
816  0;
817 
818  // Bits which describe the system hardware capabilities
819  // XXX Figure out what these should be
820  auxv.emplace_back(gem5::auxv::Hwcap, features);
821  // The system page size
822  auxv.emplace_back(gem5::auxv::Pagesz, X86ISA::PageBytes);
823  // Frequency at which times() increments
824  // Defined to be 100 in the kernel source.
825  auxv.emplace_back(gem5::auxv::Clktck, 100);
826  // This is the virtual address of the program header tables if they
827  // appear in the executable image.
828  auxv.emplace_back(gem5::auxv::Phdr, elfObject->programHeaderTable());
829  // This is the size of a program header entry from the elf file.
830  auxv.emplace_back(gem5::auxv::Phent, elfObject->programHeaderSize());
831  // This is the number of program headers from the original elf file.
832  auxv.emplace_back(gem5::auxv::Phnum, elfObject->programHeaderCount());
833  // This is the base address of the ELF interpreter; it should be
834  // zero for static executables or contain the base address for
835  // dynamic executables.
836  auxv.emplace_back(gem5::auxv::Base, getBias());
837  // XXX Figure out what this should be.
838  auxv.emplace_back(gem5::auxv::Flags, 0);
839  // The entry point to the program
840  auxv.emplace_back(gem5::auxv::Entry, objFile->entryPoint());
841  // Different user and group IDs
842  auxv.emplace_back(gem5::auxv::Uid, uid());
843  auxv.emplace_back(gem5::auxv::Euid, euid());
844  auxv.emplace_back(gem5::auxv::Gid, gid());
845  auxv.emplace_back(gem5::auxv::Egid, egid());
846  // Whether to enable "secure mode" in the executable
847  auxv.emplace_back(gem5::auxv::Secure, 0);
848  // The address of 16 "random" bytes.
849  auxv.emplace_back(gem5::auxv::Random, 0);
850  // The name of the program
851  auxv.emplace_back(gem5::auxv::Execfn, 0);
852  // The platform string
853  auxv.emplace_back(gem5::auxv::Platform, 0);
854  }
855 
856  // Figure out how big the initial stack needs to be
857 
858  // A sentry NULL void pointer at the top of the stack.
859  int sentry_size = intSize;
860 
861  // This is the name of the file which is present on the initial stack
862  // It's purpose is to let the user space linker examine the original file.
863  int file_name_size = filename.size() + 1;
864 
865  const int numRandomBytes = 16;
866  int aux_data_size = numRandomBytes;
867 
868  std::string platform = "x86_64";
869  aux_data_size += platform.size() + 1;
870 
871  int env_data_size = 0;
872  for (int i = 0; i < envp.size(); ++i)
873  env_data_size += envp[i].size() + 1;
874  int arg_data_size = 0;
875  for (int i = 0; i < argv.size(); ++i)
876  arg_data_size += argv[i].size() + 1;
877 
878  // The info_block needs to be padded so its size is a multiple of the
879  // alignment mask. Also, it appears that there needs to be at least some
880  // padding, so if the size is already a multiple, we need to increase it
881  // anyway.
882  int base_info_block_size =
883  sentry_size + file_name_size + env_data_size + arg_data_size;
884 
885  int info_block_size = roundUp(base_info_block_size, align);
886 
887  int info_block_padding = info_block_size - base_info_block_size;
888 
889  // Each auxiliary vector is two 8 byte words
890  int aux_array_size = intSize * 2 * (auxv.size() + 1);
891 
892  int envp_array_size = intSize * (envp.size() + 1);
893  int argv_array_size = intSize * (argv.size() + 1);
894 
895  int argc_size = intSize;
896 
897  // Figure out the size of the contents of the actual initial frame
898  int frame_size =
899  aux_array_size +
900  envp_array_size +
901  argv_array_size +
902  argc_size;
903 
904  // There needs to be padding after the auxiliary vector data so that the
905  // very bottom of the stack is aligned properly.
906  int partial_size = frame_size + aux_data_size;
907  int aligned_partial_size = roundUp(partial_size, align);
908  int aux_padding = aligned_partial_size - partial_size;
909 
910  int space_needed =
911  info_block_size +
912  aux_data_size +
913  aux_padding +
914  frame_size;
915 
916  Addr stack_base = memState->getStackBase();
917 
918  Addr stack_min = stack_base - space_needed;
919  stack_min = roundDown(stack_min, align);
920 
921  unsigned stack_size = stack_base - stack_min;
922  stack_size = roundUp(stack_size, pageSize);
923  memState->setStackSize(stack_size);
924 
925  // map memory
926  Addr stack_end = roundDown(stack_base - stack_size, pageSize);
927 
928  DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
929  memState->mapRegion(stack_end, stack_size, "stack");
930 
931  // map out initial stack contents
932  IntType sentry_base = stack_base - sentry_size;
933  IntType file_name_base = sentry_base - file_name_size;
934  IntType env_data_base = file_name_base - env_data_size;
935  IntType arg_data_base = env_data_base - arg_data_size;
936  IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
937  IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
938  IntType envp_array_base = auxv_array_base - envp_array_size;
939  IntType argv_array_base = envp_array_base - argv_array_size;
940  IntType argc_base = argv_array_base - argc_size;
941 
942  DPRINTF(Stack, "The addresses of items on the initial stack:\n");
943  DPRINTF(Stack, "0x%x - file name\n", file_name_base);
944  DPRINTF(Stack, "0x%x - env data\n", env_data_base);
945  DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
946  DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
947  DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
948  DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
949  DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
950  DPRINTF(Stack, "0x%x - argc \n", argc_base);
951  DPRINTF(Stack, "0x%x - stack min\n", stack_min);
952 
953  // write contents to stack
954 
955  // figure out argc
956  IntType argc = argv.size();
957  IntType guestArgc = htole(argc);
958 
959  // Write out the sentry void *
960  IntType sentry_NULL = 0;
961  initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
962 
963  // Write the file name
964  initVirtMem->writeString(file_name_base, filename.c_str());
965 
966  // Fix up the aux vectors which point to data
967  assert(auxv[auxv.size() - 3].type == gem5::auxv::Random);
968  auxv[auxv.size() - 3].val = aux_data_base;
969  assert(auxv[auxv.size() - 2].type == gem5::auxv::Execfn);
970  auxv[auxv.size() - 2].val = argv_array_base;
971  assert(auxv[auxv.size() - 1].type == gem5::auxv::Platform);
972  auxv[auxv.size() - 1].val = aux_data_base + numRandomBytes;
973 
974 
975  // Copy the aux stuff
976  Addr auxv_array_end = auxv_array_base;
977  for (const auto &aux: auxv) {
978  initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
979  auxv_array_end += sizeof(aux);
980  }
981  // Write out the terminating zeroed auxiliary vector
982  const gem5::auxv::AuxVector<uint64_t> zero(0, 0);
983  initVirtMem->write(auxv_array_end, zero);
984  auxv_array_end += sizeof(zero);
985 
986  initVirtMem->writeString(aux_data_base, platform.c_str());
987 
988  copyStringArray(envp, envp_array_base, env_data_base,
989  ByteOrder::little, *initVirtMem);
990  copyStringArray(argv, argv_array_base, arg_data_base,
991  ByteOrder::little, *initVirtMem);
992 
993  initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
994 
996  // Set the stack pointer register
997  tc->setReg(int_reg::Rsp, stack_min);
998 
999  // There doesn't need to be any segment base added in since we're dealing
1000  // with the flat segmentation model.
1001  tc->pcState(getStartPC());
1002 
1003  // Align the "stack_min" to a page boundary.
1004  memState->setStackMin(roundDown(stack_min, pageSize));
1005 }
1006 
1007 void
1009 {
1011  extraAuxvs.emplace_back(auxv::SysinfoEhdr, vsyscallPage.base);
1012  X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
1013 }
1014 
1015 void
1017 {
1019  //Tell the binary where the vsyscall part of the vsyscall page is.
1020  extraAuxvs.emplace_back(auxv::Sysinfo,
1022  extraAuxvs.emplace_back(auxv::SysinfoEhdr, vsyscallPage.base);
1023  X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
1024 }
1025 
1026 void
1028  Process *p, RegVal flags)
1029 {
1030  X86Process::clone(old_tc, new_tc, p, flags);
1031  ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
1032 }
1033 
1034 void
1036  Process *p, RegVal flags)
1037 {
1038  X86Process::clone(old_tc, new_tc, p, flags);
1039  ((I386Process*)p)->vsyscallPage = vsyscallPage;
1040 }
1041 
1042 } // namespace gem5
gem5::X86ISA::misc_reg::Lstar
@ Lstar
Definition: misc.hh:257
gem5::loader::MemoryImage::maxAddr
Addr maxAddr() const
Definition: memory_image.hh:136
gem5::auxv::Platform
@ Platform
Definition: aux_vector.hh:82
gem5::Process::euid
uint64_t euid()
Definition: process.hh:84
gem5::X86ISA::I386Process::vsyscallPage
VSyscallPage vsyscallPage
Definition: process.hh:162
gem5::X86ISA::misc_reg::TslAttr
@ TslAttr
Definition: misc.hh:378
gem5::EmulationPageTable
Definition: page_table.hh:53
gem5::loader::ObjectFile
Definition: object_file.hh:97
gem5::auxv::Gid
@ Gid
Definition: aux_vector.hh:80
gem5::PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:192
gem5::X86ISA::X86_64Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:152
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::X86ISA::misc_reg::Star
@ Star
Definition: misc.hh:256
system.hh
gem5::Process::clone
virtual void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *new_p, RegVal flags)
Definition: process.cc:167
gem5::Process::getStartPC
Addr getStartPC()
Definition: process.cc:497
gem5::X86ISA::segment_idx::Ds
@ Ds
Definition: segment.hh:53
gem5::Process::initVirtMem
std::unique_ptr< SETranslatingPortProxy > initVirtMem
Definition: process.hh:188
gem5::loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:137
gem5::X86ISA::I386Process::VSyscallPage::size
Addr size
Definition: process.hh:144
gem5::auxv::Random
@ Random
Definition: aux_vector.hh:87
gem5::Process::getBias
Addr getBias()
Definition: process.cc:489
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:327
gem5::ArmISA::attr
attr
Definition: misc_types.hh:656
gem5::X86ISA::PFHandlerVirtAddr
const Addr PFHandlerVirtAddr
Definition: se_workload.hh:46
gem5::auxv::Hwcap
@ Hwcap
Definition: aux_vector.hh:83
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::misc_reg::Ss
@ Ss
Definition: misc.hh:307
gem5::X86ISA::X86Process::_gdtSize
Addr _gdtSize
Definition: process.hh:71
gem5::loader::ElfObject
Definition: elf_object.hh:64
gem5::Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:288
gem5::ArchPageTable
MultiLevelPageTable< LongModePTE< 47, 39 >, LongModePTE< 38, 30 >, LongModePTE< 29, 21 >, LongModePTE< 20, 12 > > ArchPageTable
Definition: process.cc:82
gem5::X86ISA::misc_reg::Tr
@ Tr
Definition: misc.hh:316
gem5::X86ISA::misc_reg::segEffBase
static RegIndex segEffBase(int index)
Definition: misc.hh:517
gem5::X86ISA::I386Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:601
gem5::X86ISA::misc_reg::ApicBase
@ ApicBase
Definition: misc.hh:401
process_impl.hh
gem5::X86ISA::misc_reg::segAttr
static RegIndex segAttr(int index)
Definition: misc.hh:531
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::X86ISA::I386Process::argsInit
void argsInit(int pageSize)
Definition: process.cc:1016
gem5::Process::egid
uint64_t egid()
Definition: process.hh:86
std::vector
STL vector class.
Definition: stl.hh:37
gem5::Process::seWorkload
SEWorkload * seWorkload
Definition: process.hh:176
gem5::auxv::Phent
@ Phent
Definition: aux_vector.hh:71
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::X86ISA::segment_idx::Cs
@ Cs
Definition: segment.hh:51
gem5::X86ISA::X86_64Process::VSyscallPage::size
Addr size
Definition: process.hh:106
gem5::Process::gid
uint64_t gid()
Definition: process.hh:85
gem5::Process::useForClone
bool useForClone
Definition: process.hh:183
gem5::Process::memState
std::shared_ptr< MemState > memState
Definition: process.hh:290
gem5::X86ISA::misc_reg::SfMask
@ SfMask
Definition: misc.hh:260
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
gem5::Process::allocateMem
void allocateMem(Addr vaddr, int64_t size, bool clobber=false)
Definition: process.cc:317
gem5::SEWorkload::allocPhysPages
Addr allocPhysPages(int npages, int pool_id=0)
Definition: se_workload.cc:75
gem5::X86ISA::misc_reg::TsgEffBase
@ TsgEffBase
Definition: misc.hh:347
gem5::X86ISA::I386Process
Definition: process.hh:137
gem5::X86ISA::misc_reg::TsgBase
@ TsgBase
Definition: misc.hh:329
gem5::X86ISA::X86Process
Definition: process.hh:67
gem5::X86ISA::X86_64Process::argsInit
void argsInit(int pageSize)
Definition: process.cc:1008
gem5::X86ISA::TSSVirtAddr
const Addr TSSVirtAddr
Definition: se_workload.hh:43
gem5::X86ISA::misc_reg::segSel
static RegIndex segSel(int index)
Definition: misc.hh:503
gem5::X86ISA::misc_reg::TrAttr
@ TrAttr
Definition: misc.hh:382
gem5::X86ISA::misc_reg::segBase
static RegIndex segBase(int index)
Definition: misc.hh:510
gem5::Process::uid
uint64_t uid()
Definition: process.hh:83
gem5::X86ISA::auxv::SysinfoEhdr
@ SysinfoEhdr
Definition: process.hh:62
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::auxv::Pagesz
@ Pagesz
Definition: aux_vector.hh:73
elf_object.hh
gem5::high
high
Definition: intmath.hh:176
gem5::X86ISA::X86_64Process::clone
void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process, RegVal flags) override
Definition: process.cc:1027
syscall_return.hh
gem5::auxv::Secure
@ Secure
Definition: aux_vector.hh:85
gem5::X86ISA::misc_reg::Cr0
@ Cr0
Definition: misc.hh:114
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
multi_level_page_table.hh
gem5::auxv::Clktck
@ Clktck
Definition: aux_vector.hh:84
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
int.hh
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:185
gem5::X86ISA::I386Process::clone
void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process, RegVal flags) override
Definition: process.cc:1035
gem5::copyStringArray
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:43
gem5::X86ISA::misc_reg::Mxcsr
@ Mxcsr
Definition: misc.hh:388
segment.hh
gem5::X86ISA::segment_idx::Gs
@ Gs
Definition: segment.hh:55
gem5::X86ISA::segment_idx::Es
@ Es
Definition: segment.hh:50
gem5::auxv::AuxVector
Definition: aux_vector.hh:43
gem5::auxv::Phdr
@ Phdr
Definition: aux_vector.hh:70
gem5::X86ISA::I386Process::VSyscallPage::vsysexitOffset
Addr vsysexitOffset
Definition: process.hh:146
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::Process::argv
std::vector< std::string > argv
Definition: process.hh:227
page_size.hh
gem5::X86ISA::I386Process::VSyscallPage::vsyscallOffset
Addr vsyscallOffset
Definition: process.hh:145
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
flags
uint8_t flags
Definition: helpers.cc:66
gem5::X86ISA::X86_64Process::VSyscallPage::vgettimeofdayOffset
Addr vgettimeofdayOffset
Definition: process.hh:108
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::X86ISA::misc_reg::Cr2
@ Cr2
Definition: misc.hh:116
gem5::X86ISA::misc_reg::Ds
@ Ds
Definition: misc.hh:308
gem5::X86ISA::misc_reg::Tsl
@ Tsl
Definition: misc.hh:312
gem5::X86ISA::misc_reg::Cr3
@ Cr3
Definition: misc.hh:117
gem5::auxv::Egid
@ Egid
Definition: aux_vector.hh:81
gem5::X86ISA::segment_idx::Ss
@ Ss
Definition: segment.hh:52
gem5::auxv::Entry
@ Entry
Definition: aux_vector.hh:76
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::misc_reg::Cr4
@ Cr4
Definition: misc.hh:118
gem5::X86ISA::misc_reg::Cs
@ Cs
Definition: misc.hh:306
gem5::Process::envp
std::vector< std::string > envp
Definition: process.hh:228
gem5::MipsISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:238
gem5::auxv::Phnum
@ Phnum
Definition: aux_vector.hh:72
se_workload.hh
name
const std::string & name()
Definition: trace.cc:49
gem5::X86ISA::X86_64Process::X86_64Process
X86_64Process(const ProcessParams &params, loader::ObjectFile *objFile)
Definition: process.cc:104
gem5::MultiLevelPageTable
Definition: multi_level_page_table.hh:186
gem5::Process
Definition: process.hh:68
gem5::auxv::Execfn
@ Execfn
Definition: aux_vector.hh:89
gem5::X86ISA::X86_64Process::VSyscallPage::vtimeOffset
Addr vtimeOffset
Definition: process.hh:107
gem5::X86ISA::X86_64Process::vsyscallPage
VSyscallPage vsyscallPage
Definition: process.hh:124
gem5::EmulationPageTable::map
virtual void map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags=0)
Maps a virtual memory region to a physical memory region.
Definition: page_table.cc:48
gem5::X86ISA::LongModePTE
Definition: pagetable.hh:155
gem5::X86ISA::misc_reg::IdtrBase
@ IdtrBase
Definition: misc.hh:333
gem5::X86ISA::X86_64Process::VSyscallPage::base
Addr base
Definition: process.hh:105
gem5::X86ISA::X86Process::X86Process
X86Process(const ProcessParams &params, loader::ObjectFile *objFile)
Definition: process.cc:84
gem5::X86ISA::misc_reg::TsgLimit
@ TsgLimit
Definition: misc.hh:363
gem5::X86ISA::misc_reg::Gs
@ Gs
Definition: misc.hh:310
aux_vector.hh
process.hh
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::X86ISA::segment_idx::Fs
@ Fs
Definition: segment.hh:54
gem5::X86ISA::ISTVirtAddr
const Addr ISTVirtAddr
Definition: se_workload.hh:45
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::X86Process::argsInit
void argsInit(int pageSize, std::vector< gem5::auxv::AuxVector< IntType >> extraAuxvs)
Definition: process.cc:724
gem5::System::m5opRange
const AddrRange & m5opRange() const
Range used by memory-mapped m5 pseudo-ops if enabled.
Definition: system.hh:577
gem5::X86ISA::X86Process::clone
void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process, RegVal flags) override
Definition: process.cc:96
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::auxv::Uid
@ Uid
Definition: aux_vector.hh:78
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
logging.hh
gem5::Process::system
System * system
Definition: process.hh:174
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::auxv::Euid
@ Euid
Definition: aux_vector.hh:79
gem5::Process::contextIds
std::vector< ContextID > contextIds
Definition: process.hh:171
trace.hh
gem5::X86ISA::X86_64Process
Definition: process.hh:99
gem5::X86ISA::MMIORegionVirtAddr
const Addr MMIORegionVirtAddr
Definition: se_workload.hh:47
gem5::X86ISA::misc_reg::Es
@ Es
Definition: misc.hh:305
fs_workload.hh
gem5::X86ISA::misc_reg::Cr8
@ Cr8
Definition: misc.hh:122
gem5::X86ISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:49
gem5::X86ISA::misc_reg::IdtrLimit
@ IdtrLimit
Definition: misc.hh:367
gem5::X86ISA::segment_idx::NumIdxs
@ NumIdxs
Definition: segment.hh:67
page_table.hh
gem5::X86ISA::misc_reg::TrEffBase
@ TrEffBase
Definition: misc.hh:350
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::misc_reg::TrLimit
@ TrLimit
Definition: misc.hh:366
gem5::X86ISA::misc_reg::Efer
@ Efer
Definition: misc.hh:254
gem5::X86ISA::I386Process::VSyscallPage::base
Addr base
Definition: process.hh:143
gem5::auxv::Flags
@ Flags
Definition: aux_vector.hh:75
gem5::X86ISA::installSegDesc
void installSegDesc(ThreadContext *tc, int seg, SegDescriptor desc, bool longmode)
Definition: fs_workload.cc:65
gem5::X86ISA::X86Process::_gdtStart
Addr _gdtStart
Definition: process.hh:70
gem5::X86ISA::misc_reg::CsAttr
@ CsAttr
Definition: misc.hh:372
misc.hh
gem5::Process::kvmInSE
bool kvmInSE
Definition: process.hh:181
gem5::X86ISA::syscallCodeVirtAddr
const Addr syscallCodeVirtAddr
Definition: se_workload.hh:40
object_file.hh
types.hh
gem5::X86ISA::misc_reg::segLimit
static RegIndex segLimit(int index)
Definition: misc.hh:524
gem5::Process::image
loader::MemoryImage image
Definition: process.hh:225
thread_context.hh
gem5::Process::objFile
loader::ObjectFile * objFile
Definition: process.hh:224
gem5::X86ISA::misc_reg::Fs
@ Fs
Definition: misc.hh:309
gem5::X86ISA::GDTVirtAddr
const Addr GDTVirtAddr
Definition: se_workload.hh:41
gem5::X86ISA::misc_reg::TrBase
@ TrBase
Definition: misc.hh:332
gem5::X86ISA::auxv::Sysinfo
@ Sysinfo
Definition: process.hh:61
syscall_desc.hh
byteswap.hh
gem5::X86ISA::I386Process::I386Process
I386Process(const ProcessParams &params, loader::ObjectFile *objFile)
Definition: process.cc:125
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183
gem5::X86ISA::IDTVirtAddr
const Addr IDTVirtAddr
Definition: se_workload.hh:42

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