gem5  v21.1.0.2
ns_gige.hh
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28 
34 #ifndef __DEV_NET_NS_GIGE_HH__
35 #define __DEV_NET_NS_GIGE_HH__
36 
37 #include "base/inet.hh"
38 #include "dev/io_device.hh"
39 #include "dev/net/etherdevice.hh"
40 #include "dev/net/etherint.hh"
41 #include "dev/net/etherpkt.hh"
42 #include "dev/net/ns_gige_reg.h"
43 #include "dev/net/pktfifo.hh"
44 #include "params/NSGigE.hh"
45 #include "sim/eventq.hh"
46 
47 namespace gem5
48 {
49 
50 // Hash filtering constants
51 const uint16_t FHASH_ADDR = 0x100;
52 const uint16_t FHASH_SIZE = 0x100;
53 
54 // EEPROM constants
55 const uint8_t EEPROM_READ = 0x2;
56 const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
57 const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
58 const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
59 const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
60 
64 struct dp_regs
65 {
66  uint32_t command;
67  uint32_t config;
68  uint32_t mear;
69  uint32_t ptscr;
70  uint32_t isr;
71  uint32_t imr;
72  uint32_t ier;
73  uint32_t ihr;
74  uint32_t txdp;
75  uint32_t txdp_hi;
76  uint32_t txcfg;
77  uint32_t gpior;
78  uint32_t rxdp;
79  uint32_t rxdp_hi;
80  uint32_t rxcfg;
81  uint32_t pqcr;
82  uint32_t wcsr;
83  uint32_t pcr;
84  uint32_t rfcr;
85  uint32_t rfdr;
86  uint32_t brar;
87  uint32_t brdr;
88  uint32_t srr;
89  uint32_t mibc;
90  uint32_t vrcr;
91  uint32_t vtcr;
92  uint32_t vdr;
93  uint32_t ccsr;
94  uint32_t tbicr;
95  uint32_t tbisr;
96  uint32_t tanar;
97  uint32_t tanlpar;
98  uint32_t taner;
99  uint32_t tesr;
100 };
101 
102 struct dp_rom
103 {
108  uint8_t perfectMatch[ETH_ADDR_LEN];
109 
115 };
116 
117 class NSGigEInt;
118 class Packet;
119 
123 class NSGigE : public EtherDevBase
124 {
125  public:
127  enum TxState
128  {
136  };
137 
139  enum RxState
140  {
148  };
149 
150  enum DmaState
151  {
157  };
158 
161  {
166  };
167 
168  protected:
172 
174  bool ioEnable;
175 
176  /*** BASIC STRUCTURES FOR TX/RX ***/
177  /* Data FIFOs */
180 
184  uint8_t *txPacketBufPtr;
185  uint8_t *rxPacketBufPtr;
186  uint32_t txXferLen;
187  uint32_t rxXferLen;
188  bool rxDmaFree;
189  bool txDmaFree;
190 
196 
197  /* tx State Machine */
199  bool txEnable;
200 
202  bool CTDD;
204  bool txHalt;
208  uint32_t txDescCnt;
210 
213  bool rxEnable;
214 
216  bool CRDD;
218  uint32_t rxPktBytes;
220  bool rxHalt;
224  uint32_t rxDescCnt;
226 
228 
231  bool eepromClk;
232  uint8_t eepromBitsToRx;
233  uint8_t eepromOpcode;
234  uint8_t eepromAddress;
235  uint16_t eepromData;
236 
237  protected:
240 
243 
244  void *rxDmaData;
246  int rxDmaLen;
247  bool doRxDmaRead();
248  bool doRxDmaWrite();
249 
250  void *txDmaData;
252  int txDmaLen;
253  bool doTxDmaRead();
254  bool doTxDmaWrite();
255 
256  void rxDmaReadDone();
258 
259  void rxDmaWriteDone();
261 
262  void txDmaReadDone();
264 
265  void txDmaWriteDone();
267 
270 
271  protected:
274 
275  void txReset();
276  void rxReset();
277  void regsReset();
278 
279  void rxKick();
282 
283  void txKick();
286 
287  void eepromKick();
288 
292  void transmit();
294  {
295  transmit();
296  if (txState == txFifoBlock)
297  txKick();
298  }
300 
301  void txDump() const;
302  void rxDump() const;
303 
308  bool rxFilter(const EthPacketPtr &packet);
313  bool acceptArp;
315 
319  void devIntrPost(uint32_t interrupts);
320  void devIntrClear(uint32_t interrupts);
321  void devIntrChangeMask();
322 
326  void cpuIntrPost(Tick when);
327  void cpuInterrupt();
328  void cpuIntrClear();
329 
332 
333  public:
334  PARAMS(NSGigE);
335 
336  NSGigE(const Params &params);
337  ~NSGigE();
338 
339  Port &getPort(const std::string &if_name,
340  PortID idx=InvalidPortID) override;
341 
342  Tick writeConfig(PacketPtr pkt) override;
343 
344  Tick read(PacketPtr pkt) override;
345  Tick write(PacketPtr pkt) override;
346 
347  bool cpuIntrPending() const;
348  void cpuIntrAck() { cpuIntrClear(); }
349 
350  bool recvPacket(EthPacketPtr packet);
351  void transferDone();
352 
353  void serialize(CheckpointOut &cp) const override;
354  void unserialize(CheckpointIn &cp) override;
355 
356  void drainResume() override;
357 };
358 
359 /*
360  * Ethernet Interface for an Ethernet Device
361  */
362 class NSGigEInt : public EtherInt
363 {
364  private:
366 
367  public:
368  NSGigEInt(const std::string &name, NSGigE *d)
369  : EtherInt(name), dev(d)
370  { }
371 
372  virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
373  virtual void sendDone() { dev->transferDone(); }
374 };
375 
376 } // namespace gem5
377 
378 #endif // __DEV_NET_NS_GIGE_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::EtherDevBase
Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy.
Definition: etherdevice.hh:143
gem5::NSGigE::rxDmaAddr
Addr rxDmaAddr
Definition: ns_gige.hh:245
gem5::NSGigE::rxFilter
bool rxFilter(const EthPacketPtr &packet)
Definition: ns_gige.cc:1909
gem5::NSGigE::txDmaAddr
Addr txDmaAddr
Definition: ns_gige.hh:251
gem5::dp_rom
Definition: ns_gige.hh:102
gem5::dp_regs::config
uint32_t config
Definition: ns_gige.hh:67
gem5::EEPROM_PMATCH0_ADDR
const uint8_t EEPROM_PMATCH0_ADDR
Definition: ns_gige.hh:59
gem5::NSGigE::dmaIdle
@ dmaIdle
Definition: ns_gige.hh:152
io_device.hh
gem5::dp_regs::command
uint32_t command
Definition: ns_gige.hh:66
gem5::FHASH_ADDR
const uint16_t FHASH_ADDR
Definition: ns_gige.hh:51
gem5::dp_rom::filterHash
uint8_t filterHash[FHASH_SIZE]
for hash table memory.
Definition: ns_gige.hh:114
gem5::NSGigE::interface
NSGigEInt * interface
Definition: ns_gige.hh:331
gem5::NSGigE::rxIdle
@ rxIdle
Definition: ns_gige.hh:141
gem5::dp_regs::wcsr
uint32_t wcsr
Definition: ns_gige.hh:82
gem5::NSGigE::rxPacket
EthPacketPtr rxPacket
Definition: ns_gige.hh:183
gem5::dp_regs::mibc
uint32_t mibc
Definition: ns_gige.hh:89
gem5::NSGigE::writeConfig
Tick writeConfig(PacketPtr pkt) override
This is to write to the PCI general configuration registers.
Definition: ns_gige.cc:151
gem5::NSGigE::acceptMulticast
bool acceptMulticast
Definition: ns_gige.hh:310
gem5::NSGigE::txFifoBlock
@ txFifoBlock
Definition: ns_gige.hh:132
gem5::NSGigE::txFragPtr
Addr txFragPtr
ptr to the next byte in the current fragment
Definition: ns_gige.hh:206
gem5::NSGigE::dmaReading
@ dmaReading
Definition: ns_gige.hh:153
gem5::NSGigE
NS DP83820 Ethernet device model.
Definition: ns_gige.hh:123
gem5::NSGigE::txDescRefr
@ txDescRefr
Definition: ns_gige.hh:130
gem5::EEPROM_SIZE
const uint8_t EEPROM_SIZE
Definition: ns_gige.hh:56
gem5::NSGigE::rxFragPtr
Addr rxFragPtr
ptr to the next byte in current fragment
Definition: ns_gige.hh:222
gem5::NSGigE::RxState
RxState
Receive State Machine States.
Definition: ns_gige.hh:139
gem5::NSGigE::rxFilterEnable
bool rxFilterEnable
receive address filter
Definition: ns_gige.hh:307
gem5::dp_regs::gpior
uint32_t gpior
Definition: ns_gige.hh:77
gem5::dp_regs::tbisr
uint32_t tbisr
Definition: ns_gige.hh:95
gem5::dp_regs::tbicr
uint32_t tbicr
Definition: ns_gige.hh:94
gem5::NSGigE::rxDmaFree
bool rxDmaFree
Definition: ns_gige.hh:188
gem5::NSGigE::rxDump
void rxDump() const
gem5::dp_regs::vdr
uint32_t vdr
Definition: ns_gige.hh:92
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::NSGigE::dmaWriteWaiting
@ dmaWriteWaiting
Definition: ns_gige.hh:156
gem5::NSGigE::txDesc64
ns_desc64 txDesc64
Definition: ns_gige.hh:194
gem5::NSGigEInt::NSGigEInt
NSGigEInt(const std::string &name, NSGigE *d)
Definition: ns_gige.hh:368
gem5::dp_regs
Ethernet device registers.
Definition: ns_gige.hh:64
etherint.hh
gem5::NSGigE::eepromData
uint16_t eepromData
Definition: ns_gige.hh:235
gem5::NSGigE::rom
dp_rom rom
Definition: ns_gige.hh:171
gem5::NSGigE::multicastHashEnable
bool multicastHashEnable
Definition: ns_gige.hh:314
gem5::dp_regs::tesr
uint32_t tesr
Definition: ns_gige.hh:99
gem5::NSGigE::dmaReadWaiting
@ dmaReadWaiting
Definition: ns_gige.hh:155
gem5::dp_regs::pqcr
uint32_t pqcr
Definition: ns_gige.hh:81
gem5::dp_regs::rxdp_hi
uint32_t rxdp_hi
Definition: ns_gige.hh:79
gem5::dp_regs::taner
uint32_t taner
Definition: ns_gige.hh:98
gem5::NSGigE::TxState
TxState
Transmit State Machine states.
Definition: ns_gige.hh:127
gem5::NSGigE::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: ns_gige.cc:175
gem5::NSGigE::txFragRead
@ txFragRead
Definition: ns_gige.hh:133
gem5::EtherInt::name
const std::string & name() const
Return port name (for DPRINTF).
Definition: etherint.hh:62
gem5::NSGigE::rxHalt
bool rxHalt
halt the rx state machine after current packet
Definition: ns_gige.hh:220
gem5::NSGigE::regs
dp_regs regs
device register file
Definition: ns_gige.hh:170
gem5::NSGigE::dmaWriteFactor
Tick dmaWriteFactor
Definition: ns_gige.hh:242
gem5::NSGigE::rxDescWrite
@ rxDescWrite
Definition: ns_gige.hh:146
gem5::NSGigE::txDmaState
DmaState txDmaState
Definition: ns_gige.hh:209
gem5::NSGigE::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: ns_gige.cc:2002
gem5::NSGigE::acceptArp
bool acceptArp
Definition: ns_gige.hh:313
gem5::dp_regs::mear
uint32_t mear
Definition: ns_gige.hh:68
ns_gige_reg.h
gem5::NSGigE::doRxDmaWrite
bool doRxDmaWrite()
Definition: ns_gige.cc:1010
gem5::NSGigE::txHalt
bool txHalt
halt the tx state machine after next packet
Definition: ns_gige.hh:204
gem5::NSGigE::txXferLen
uint32_t txXferLen
Definition: ns_gige.hh:186
gem5::EtherInt
Definition: etherint.hh:50
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::NSGigE::cpuIntrAck
void cpuIntrAck()
Definition: ns_gige.hh:348
gem5::NSGigE::rxEnable
bool rxEnable
Definition: ns_gige.hh:213
gem5::NSGigE::rxKick
void rxKick()
Definition: ns_gige.cc:1040
gem5::NSGigE::extstsEnable
bool extstsEnable
Definition: ns_gige.hh:227
gem5::NSGigE::dmaDataFree
bool dmaDataFree
Definition: ns_gige.hh:269
gem5::NSGigE::txState
TxState txState
Definition: ns_gige.hh:198
gem5::NSGigE::txKickEvent
EventFunctionWrapper txKickEvent
Definition: ns_gige.hh:285
gem5::NSGigE::rxDmaWriteDone
void rxDmaWriteDone()
Definition: ns_gige.cc:1023
gem5::NSGigE::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ns_gige.cc:409
gem5::NSGigE::txDescCnt
uint32_t txDescCnt
count of bytes remaining in the current descriptor
Definition: ns_gige.hh:208
gem5::NSGigE::txPacket
EthPacketPtr txPacket
various helper vars
Definition: ns_gige.hh:182
gem5::dp_regs::brar
uint32_t brar
Definition: ns_gige.hh:86
gem5::FHASH_SIZE
const uint16_t FHASH_SIZE
Definition: ns_gige.hh:52
gem5::NSGigE::eepromGetAddress
@ eepromGetAddress
Definition: ns_gige.hh:164
gem5::NSGigE::dmaWriting
@ dmaWriting
Definition: ns_gige.hh:154
gem5::NSGigE::dmaWriteDelay
Tick dmaWriteDelay
Definition: ns_gige.hh:239
gem5::NSGigE::txDump
void txDump() const
gem5::NSGigE::~NSGigE
~NSGigE()
Definition: ns_gige.cc:142
gem5::NSGigE::rxKickEvent
EventFunctionWrapper rxKickEvent
Definition: ns_gige.hh:281
gem5::NSGigE::rxReset
void rxReset()
Definition: ns_gige.cc:941
gem5::NSGigE::eepromOpcode
uint8_t eepromOpcode
Definition: ns_gige.hh:233
gem5::NSGigE::eepromGetOpcode
@ eepromGetOpcode
Definition: ns_gige.hh:163
gem5::NSGigE::dmaDescFree
bool dmaDescFree
Definition: ns_gige.hh:268
gem5::NSGigE::rxDescRead
@ rxDescRead
Definition: ns_gige.hh:143
gem5::NSGigE::acceptBroadcast
bool acceptBroadcast
Definition: ns_gige.hh:309
gem5::NSGigE::eepromAddress
uint8_t eepromAddress
Definition: ns_gige.hh:234
gem5::NSGigE::txAdvance
@ txAdvance
Definition: ns_gige.hh:135
gem5::NSGigE::cpuInterrupt
void cpuInterrupt()
Definition: ns_gige.cc:880
gem5::EthPacketPtr
std::shared_ptr< EthPacketData > EthPacketPtr
Definition: etherpkt.hh:90
gem5::NSGigE::rxState
RxState rxState
rx State Machine
Definition: ns_gige.hh:212
gem5::dp_regs::imr
uint32_t imr
Definition: ns_gige.hh:71
gem5::dp_regs::ier
uint32_t ier
Definition: ns_gige.hh:72
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::NSGigE::dmaReadDelay
Tick dmaReadDelay
Definition: ns_gige.hh:238
gem5::dp_rom::perfectMatch
uint8_t perfectMatch[ETH_ADDR_LEN]
for perfect match memory.
Definition: ns_gige.hh:108
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::NSGigE::recvPacket
bool recvPacket(EthPacketPtr packet)
Definition: ns_gige.cc:1952
gem5::NSGigE::txKick
void txKick()
Definition: ns_gige.cc:1467
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::NSGigE::txReset
void txReset()
Definition: ns_gige.cc:926
gem5::ns_desc64
Definition: ns_gige_reg.h:385
gem5::NSGigE::doRxDmaRead
bool doRxDmaRead()
Definition: ns_gige.cc:979
gem5::NSGigE::cpuIntrClear
void cpuIntrClear()
Definition: ns_gige.cc:903
gem5::NSGigE::rxAdvance
@ rxAdvance
Definition: ns_gige.hh:147
gem5::NSGigE::CTDD
bool CTDD
Current Transmit Descriptor Done.
Definition: ns_gige.hh:202
gem5::NSGigE::acceptPerfect
bool acceptPerfect
Definition: ns_gige.hh:312
gem5::NSGigE::rxKickTick
Tick rxKickTick
Definition: ns_gige.hh:280
gem5::NSGigE::txDesc32
ns_desc32 txDesc32
DescCaches.
Definition: ns_gige.hh:192
gem5::dp_regs::rfcr
uint32_t rfcr
Definition: ns_gige.hh:84
gem5::dp_regs::ccsr
uint32_t ccsr
Definition: ns_gige.hh:93
gem5::EEPROM_PMATCH1_ADDR
const uint8_t EEPROM_PMATCH1_ADDR
Definition: ns_gige.hh:58
gem5::NSGigE::txPacketBufPtr
uint8_t * txPacketBufPtr
Definition: ns_gige.hh:184
gem5::dp_regs::txdp_hi
uint32_t txdp_hi
Definition: ns_gige.hh:75
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::NSGigE::rxDmaWriteEvent
EventFunctionWrapper rxDmaWriteEvent
Definition: ns_gige.hh:260
gem5::NSGigEInt::dev
NSGigE * dev
Definition: ns_gige.hh:365
gem5::NSGigE::rxFifoBlock
@ rxFifoBlock
Definition: ns_gige.hh:144
gem5::NSGigE::cpuPendingIntr
bool cpuPendingIntr
Definition: ns_gige.hh:325
gem5::NSGigE::txIdle
@ txIdle
Definition: ns_gige.hh:129
gem5::NSGigE::rxDesc64
ns_desc64 rxDesc64
Definition: ns_gige.hh:195
gem5::NSGigE::eepromState
EEPROMState eepromState
EEPROM State Machine.
Definition: ns_gige.hh:230
gem5::dp_regs::ihr
uint32_t ihr
Definition: ns_gige.hh:73
gem5::NSGigE::rxDmaLen
int rxDmaLen
Definition: ns_gige.hh:246
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::dp_regs::vtcr
uint32_t vtcr
Definition: ns_gige.hh:91
gem5::NSGigE::txDmaReadEvent
EventFunctionWrapper txDmaReadEvent
Definition: ns_gige.hh:263
gem5::NSGigE::rxDelay
Tick rxDelay
Definition: ns_gige.hh:273
gem5::NSGigE::txEnable
bool txEnable
Definition: ns_gige.hh:199
gem5::NSGigE::doTxDmaWrite
bool doTxDmaWrite()
Definition: ns_gige.cc:1437
gem5::NSGigEInt::recvPacket
virtual bool recvPacket(EthPacketPtr pkt)
Definition: ns_gige.hh:372
gem5::NSGigE::txDmaLen
int txDmaLen
Definition: ns_gige.hh:252
gem5::NSGigE::rxXferLen
uint32_t rxXferLen
Definition: ns_gige.hh:187
gem5::NSGigE::CRDD
bool CRDD
Current Receive Descriptor Done.
Definition: ns_gige.hh:216
gem5::NSGigE::eepromBitsToRx
uint8_t eepromBitsToRx
Definition: ns_gige.hh:232
gem5::NSGigE::intrEvent
EventFunctionWrapper * intrEvent
Definition: ns_gige.hh:330
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::dp_regs::txcfg
uint32_t txcfg
Definition: ns_gige.hh:76
gem5::NSGigE::dmaReadFactor
Tick dmaReadFactor
Definition: ns_gige.hh:241
gem5::NSGigE::transmit
void transmit()
Retransmit event.
Definition: ns_gige.cc:1355
gem5::NSGigE::txDmaFree
bool txDmaFree
Definition: ns_gige.hh:189
gem5::dp_regs::rfdr
uint32_t rfdr
Definition: ns_gige.hh:85
gem5::NSGigE::txDescRead
@ txDescRead
Definition: ns_gige.hh:131
gem5::NSGigE::DmaState
DmaState
Definition: ns_gige.hh:150
gem5::NSGigE::rxFifo
PacketFifo rxFifo
Definition: ns_gige.hh:179
gem5::EEPROM_PMATCH2_ADDR
const uint8_t EEPROM_PMATCH2_ADDR
Definition: ns_gige.hh:57
gem5::NSGigE::rxFragWrite
@ rxFragWrite
Definition: ns_gige.hh:145
gem5::NSGigEInt::sendDone
virtual void sendDone()
Definition: ns_gige.hh:373
gem5::dp_regs::rxdp
uint32_t rxdp
Definition: ns_gige.hh:78
gem5::NSGigE::rxDescRefr
@ rxDescRefr
Definition: ns_gige.hh:142
gem5::NSGigE::transferDone
void transferDone()
Definition: ns_gige.cc:1896
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::NSGigE::ioEnable
bool ioEnable
pci settings
Definition: ns_gige.hh:174
gem5::NSGigE::eepromClk
bool eepromClk
Definition: ns_gige.hh:231
gem5::NSGigE::devIntrPost
void devIntrPost(uint32_t interrupts)
Interrupt management.
Definition: ns_gige.cc:733
gem5::NSGigE::txEvent
EventFunctionWrapper txEvent
Definition: ns_gige.hh:299
gem5::dp_regs::txdp
uint32_t txdp
Definition: ns_gige.hh:74
gem5::NSGigE::PARAMS
PARAMS(NSGigE)
gem5::NSGigE::txEventTransmit
void txEventTransmit()
Definition: ns_gige.hh:293
gem5::dp_regs::tanlpar
uint32_t tanlpar
Definition: ns_gige.hh:97
gem5::NSGigE::eepromKick
void eepromKick()
Advance the EEPROM state machine Called on rising edge of EEPROM clock bit in MEAR.
Definition: ns_gige.cc:1799
gem5::NSGigE::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: ns_gige.cc:2191
gem5::dp_regs::pcr
uint32_t pcr
Definition: ns_gige.hh:83
gem5::NSGigE::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: ns_gige.cc:2018
gem5::NSGigE::txKickTick
Tick txKickTick
Definition: ns_gige.hh:284
gem5::NSGigE::EEPROMState
EEPROMState
EEPROM State Machine States.
Definition: ns_gige.hh:160
gem5::NSGigE::intrDelay
Tick intrDelay
Definition: ns_gige.hh:323
gem5::NSGigE::regsReset
void regsReset()
Definition: ns_gige.cc:956
gem5::NSGigE::rxDesc32
ns_desc32 rxDesc32
Definition: ns_gige.hh:193
pktfifo.hh
gem5::NSGigE::read
Tick read(PacketPtr pkt) override
This reads the device registers, which are detailed in the NS83820 spec sheet.
Definition: ns_gige.cc:187
etherpkt.hh
gem5::NSGigE::txDmaWriteEvent
EventFunctionWrapper txDmaWriteEvent
Definition: ns_gige.hh:266
gem5::NSGigE::cpuIntrPending
bool cpuIntrPending() const
Definition: ns_gige.cc:922
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::dp_regs::brdr
uint32_t brdr
Definition: ns_gige.hh:87
gem5::NSGigE::devIntrChangeMask
void devIntrChangeMask()
Definition: ns_gige.cc:832
etherdevice.hh
gem5::NSGigE::cpuIntrPost
void cpuIntrPost(Tick when)
Definition: ns_gige.cc:844
gem5::NSGigE::eepromRead
@ eepromRead
Definition: ns_gige.hh:165
gem5::NSGigE::rxDmaState
DmaState rxDmaState
Definition: ns_gige.hh:225
gem5::NSGigE::txDelay
Tick txDelay
Definition: ns_gige.hh:272
gem5::dp_regs::vrcr
uint32_t vrcr
Definition: ns_gige.hh:90
gem5::PacketFifo
Definition: pktfifo.hh:79
gem5::NSGigE::rxPktBytes
uint32_t rxPktBytes
num of bytes in the current packet being drained from rxDataFifo
Definition: ns_gige.hh:218
inet.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::dp_regs::tanar
uint32_t tanar
Definition: ns_gige.hh:96
gem5::NSGigE::intrTick
Tick intrTick
Definition: ns_gige.hh:324
gem5::NSGigE::NSGigE
NSGigE(const Params &params)
Definition: ns_gige.cc:97
gem5::EEPROM_READ
const uint8_t EEPROM_READ
Definition: ns_gige.hh:55
gem5::NSGigE::rxPacketBufPtr
uint8_t * rxPacketBufPtr
Definition: ns_gige.hh:185
gem5::NSGigE::txDescWrite
@ txDescWrite
Definition: ns_gige.hh:134
gem5::NSGigE::txDmaWriteDone
void txDmaWriteDone()
Definition: ns_gige.cc:1450
gem5::NSGigE::rxDmaReadEvent
EventFunctionWrapper rxDmaReadEvent
Definition: ns_gige.hh:257
gem5::NSGigE::rxDmaReadDone
void rxDmaReadDone()
Definition: ns_gige.cc:993
gem5::dp_regs::rxcfg
uint32_t rxcfg
Definition: ns_gige.hh:80
gem5::NSGigE::devIntrClear
void devIntrClear(uint32_t interrupts)
Definition: ns_gige.cc:790
gem5::ns_desc32
Definition: ns_gige_reg.h:377
gem5::dp_regs::srr
uint32_t srr
Definition: ns_gige.hh:88
gem5::NSGigE::doTxDmaRead
bool doTxDmaRead()
Definition: ns_gige.cc:1406
gem5::NSGigE::txDmaData
void * txDmaData
Definition: ns_gige.hh:250
gem5::NSGigE::rxDescCnt
uint32_t rxDescCnt
count of bytes remaining in the current descriptor
Definition: ns_gige.hh:224
gem5::dp_regs::isr
uint32_t isr
Definition: ns_gige.hh:70
gem5::NSGigE::eepromStart
@ eepromStart
Definition: ns_gige.hh:162
gem5::dp_regs::ptscr
uint32_t ptscr
Definition: ns_gige.hh:69
gem5::NSGigEInt
Definition: ns_gige.hh:362
gem5::NSGigE::txDmaReadDone
void txDmaReadDone()
Definition: ns_gige.cc:1420
gem5::NSGigE::acceptUnicast
bool acceptUnicast
Definition: ns_gige.hh:311
gem5::NSGigE::rxDmaData
void * rxDmaData
Definition: ns_gige.hh:244
gem5::NSGigE::txFifo
PacketFifo txFifo
Definition: ns_gige.hh:178
eventq.hh

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