gem5  v22.0.0.2
float.hh
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1 /*
2  * Copyright (c) 2013 ARM Limited
3  * Copyright (c) 2014-2015 Sven Karlsson
4  * Copyright (c) 2019 Yifei Liu
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45 
46 #ifndef __ARCH_RISCV_REGS_FLOAT_HH__
47 #define __ARCH_RISCV_REGS_FLOAT_HH__
48 
49 #include <softfloat.h>
50 #include <specialize.h>
51 
52 #include <cstdint>
53 #include <string>
54 #include <vector>
55 
56 #include "base/bitfield.hh"
57 
58 namespace gem5
59 {
60 
61 namespace RiscvISA
62 {
63 
64 /* Conversion functions for working with softfloat. */
65 
66 // Generic floating point value type.
67 using freg_t = float64_t;
68 
69 // Extract a 16 bit float packed into a 64 bit value.
70 static constexpr uint16_t
71 unboxF16(uint64_t v)
72 {
73  // The upper 48 bits should all be ones.
74  if (bits(v, 63, 16) == mask(48))
75  return bits(v, 15, 0);
76  else
77  return defaultNaNF16UI;
78 }
79 
80 // Extract a 32 bit float packed into a 64 bit value.
81 static constexpr uint32_t
82 unboxF32(uint64_t v)
83 {
84  // The upper 32 bits should all be ones.
85  if (bits(v, 63, 32) == mask(32))
86  return bits(v, 31, 0);
87  else
88  return defaultNaNF32UI;
89 }
90 
91 static constexpr uint64_t boxF16(uint16_t v) { return mask(63, 16) | v; }
92 static constexpr uint64_t boxF32(uint32_t v) { return mask(63, 32) | v; }
93 
94 // Create fixed size floats from raw bytes or generic floating point values.
95 static constexpr float16_t f16(uint16_t v) { return {v}; }
96 static constexpr float32_t f32(uint32_t v) { return {v}; }
97 static constexpr float64_t f64(uint64_t v) { return {v}; }
98 static constexpr float16_t f16(freg_t r) { return {unboxF16(r.v)}; }
99 static constexpr float32_t f32(freg_t r) { return {unboxF32(r.v)}; }
100 static constexpr float64_t f64(freg_t r) { return r; }
101 
102 // Create generic floating point values from fixed size floats.
103 static constexpr freg_t freg(float16_t f) { return {boxF16(f.v)}; }
104 static constexpr freg_t freg(float32_t f) { return {boxF32(f.v)}; }
105 static constexpr freg_t freg(float64_t f) { return f; }
106 static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
107 
108 const int NumFloatRegs = 32;
109 
111  "ft0", "ft1", "ft2", "ft3",
112  "ft4", "ft5", "ft6", "ft7",
113  "fs0", "fs1", "fa0", "fa1",
114  "fa2", "fa3", "fa4", "fa5",
115  "fa6", "fa7", "fs2", "fs3",
116  "fs4", "fs5", "fs6", "fs7",
117  "fs8", "fs9", "fs10", "fs11",
118  "ft8", "ft9", "ft10", "ft11"
119 };
120 
121 } // namespace RiscvISA
122 } // namespace gem5
123 
124 #endif // __ARCH_RISCV_REGS_FLOAT_HH__
gem5::RiscvISA::f32
static constexpr float32_t f32(uint32_t v)
Definition: float.hh:96
gem5::VegaISA::f
Bitfield< 56 > f
Definition: pagetable.hh:53
gem5::RiscvISA::unboxF32
static constexpr uint32_t unboxF32(uint64_t v)
Definition: float.hh:82
gem5::RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:108
gem5::RiscvISA::freg_t
float64_t freg_t
Definition: float.hh:67
std::vector< std::string >
bitfield.hh
gem5::RiscvISA::v
Bitfield< 0 > v
Definition: pagetable.hh:76
gem5::RiscvISA::f64
static constexpr float64_t f64(uint64_t v)
Definition: float.hh:97
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::RiscvISA::r
Bitfield< 1 > r
Definition: pagetable.hh:75
gem5::RiscvISA::mask
mask
Definition: pra_constants.hh:73
gem5::RiscvISA::unboxF16
static constexpr uint16_t unboxF16(uint64_t v)
Definition: float.hh:71
gem5::RiscvISA::FloatRegNames
const std::vector< std::string > FloatRegNames
Definition: float.hh:110
gem5::RiscvISA::boxF16
static constexpr uint64_t boxF16(uint16_t v)
Definition: float.hh:91
gem5::RiscvISA::boxF32
static constexpr uint64_t boxF32(uint32_t v)
Definition: float.hh:92
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::freg
static constexpr freg_t freg(float16_t f)
Definition: float.hh:103
gem5::RiscvISA::f16
static constexpr float16_t f16(uint16_t v)
Definition: float.hh:95

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