46 #ifndef __ARCH_RISCV_REGS_FLOAT_HH__
47 #define __ARCH_RISCV_REGS_FLOAT_HH__
49 #include <softfloat.h>
50 #include <specialize.h>
58 #include "debug/FloatRegs.hh"
72 static constexpr uint16_t
77 return bits(
v, 15, 0);
79 return defaultNaNF16UI;
83 static constexpr uint32_t
88 return bits(
v, 31, 0);
90 return defaultNaNF32UI;
93 static constexpr uint64_t
boxF16(uint16_t
v) {
return mask(63, 16) |
v; }
94 static constexpr uint64_t
boxF32(uint32_t
v) {
return mask(63, 32) |
v; }
97 static constexpr float16_t
f16(uint16_t
v) {
return {
v}; }
98 static constexpr float32_t
f32(uint32_t
v) {
return {
v}; }
99 static constexpr float64_t
f64(uint64_t
v) {
return {
v}; }
163 inline constexpr
RegId
202 "ft0",
"ft1",
"ft2",
"ft3",
203 "ft4",
"ft5",
"ft6",
"ft7",
204 "fs0",
"fs1",
"fa0",
"fa1",
205 "fa2",
"fa3",
"fa4",
"fa5",
206 "fa6",
"fa7",
"fs2",
"fs3",
207 "fs4",
"fs5",
"fs6",
"fs7",
208 "fs8",
"fs9",
"fs10",
"fs11",
209 "ft8",
"ft9",
"ft10",
"ft11"
Register ID: describe an architectural register with its class and index.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
const std::vector< std::string > RegNames
constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs)
static constexpr float32_t f32(uint32_t v)
static constexpr freg_t freg(float16_t f)
static constexpr float16_t f16(uint16_t v)
static constexpr uint16_t unboxF16(uint64_t v)
static constexpr uint64_t boxF32(uint32_t v)
static constexpr uint64_t boxF16(uint16_t v)
static constexpr float64_t f64(uint64_t v)
static constexpr uint32_t unboxF32(uint64_t v)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
@ FloatRegClass
Floating-point register.
constexpr char FloatRegClassName[]