gem5  v21.1.0.2
float.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013 ARM Limited
3  * Copyright (c) 2014-2015 Sven Karlsson
4  * Copyright (c) 2019 Yifei Liu
5  * Copyright (c) 2020 Barkhausen Institut
6  * Copyright (c) 2021 StreamComputing Corp
7  * All rights reserved
8  *
9  * The license below extends only to copyright in the software and shall
10  * not be construed as granting a license to any other intellectual
11  * property including but not limited to intellectual property relating
12  * to a hardware implementation of the functionality of the software
13  * licensed hereunder. You may use the software subject to the license
14  * terms below provided that you ensure that this notice is replicated
15  * unmodified and in its entirety in all distributions of the software,
16  * modified or unmodified, in source code or in binary form.
17  *
18  * Copyright (c) 2016 RISC-V Foundation
19  * Copyright (c) 2016 The University of Virginia
20  * All rights reserved.
21  *
22  * Redistribution and use in source and binary forms, with or without
23  * modification, are permitted provided that the following conditions are
24  * met: redistributions of source code must retain the above copyright
25  * notice, this list of conditions and the following disclaimer;
26  * redistributions in binary form must reproduce the above copyright
27  * notice, this list of conditions and the following disclaimer in the
28  * documentation and/or other materials provided with the distribution;
29  * neither the name of the copyright holders nor the names of its
30  * contributors may be used to endorse or promote products derived from
31  * this software without specific prior written permission.
32  *
33  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44  */
45 
46 #ifndef __ARCH_RISCV_REGS_FLOAT_HH__
47 #define __ARCH_RISCV_REGS_FLOAT_HH__
48 
49 #include <softfloat.h>
50 #include <specialize.h>
51 
52 #include <cstdint>
53 #include <string>
54 #include <vector>
55 
56 #include "base/bitfield.hh"
57 
58 namespace gem5
59 {
60 
61 namespace RiscvISA
62 {
63 
64 /* Conversion functions for working with softfloat. */
65 
66 // Generic floating point value type.
67 using freg_t = float64_t;
68 
69 // Extract a 32 bit float packed into a 64 bit value.
70 static constexpr uint32_t
71 unboxF32(uint64_t v)
72 {
73  // The upper 32 bits should all be ones.
74  if (bits(v, 63, 32) == mask(32))
75  return bits(v, 31, 0);
76  else
77  return defaultNaNF32UI;
78 }
79 
80 static constexpr uint64_t boxF32(uint32_t v) { return mask(63, 32) | v; }
81 
82 // Create fixed size floats from raw bytes or generic floating point values.
83 static constexpr float32_t f32(uint32_t v) { return {v}; }
84 static constexpr float64_t f64(uint64_t v) { return {v}; }
85 static constexpr float32_t f32(freg_t r) { return {unboxF32(r.v)}; }
86 static constexpr float64_t f64(freg_t r) { return r; }
87 
88 // Create generic floating point values from fixed size floats.
89 static constexpr freg_t freg(float32_t f) { return {boxF32(f.v)}; }
90 static constexpr freg_t freg(float64_t f) { return f; }
91 static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
92 
93 const int NumFloatRegs = 32;
94 
96  "ft0", "ft1", "ft2", "ft3",
97  "ft4", "ft5", "ft6", "ft7",
98  "fs0", "fs1", "fa0", "fa1",
99  "fa2", "fa3", "fa4", "fa5",
100  "fa6", "fa7", "fs2", "fs3",
101  "fs4", "fs5", "fs6", "fs7",
102  "fs8", "fs9", "fs10", "fs11",
103  "ft8", "ft9", "ft10", "ft11"
104 };
105 
106 } // namespace RiscvISA
107 } // namespace gem5
108 
109 #endif // __ARCH_RISCV_REGS_FLOAT_HH__
gem5::RiscvISA::f32
static constexpr float32_t f32(uint32_t v)
Definition: float.hh:83
gem5::RiscvISA::unboxF32
static constexpr uint32_t unboxF32(uint64_t v)
Definition: float.hh:71
gem5::RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:93
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:67
gem5::RiscvISA::freg_t
float64_t freg_t
Definition: float.hh:67
std::vector< std::string >
gem5::RiscvISA::freg
static constexpr freg_t freg(float32_t f)
Definition: float.hh:89
bitfield.hh
gem5::RiscvISA::v
Bitfield< 0 > v
Definition: pagetable.hh:76
gem5::RiscvISA::f64
static constexpr float64_t f64(uint64_t v)
Definition: float.hh:84
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::RiscvISA::r
Bitfield< 1 > r
Definition: pagetable.hh:75
gem5::RiscvISA::mask
mask
Definition: pra_constants.hh:73
gem5::RiscvISA::FloatRegNames
const std::vector< std::string > FloatRegNames
Definition: float.hh:95
gem5::RiscvISA::boxF32
static constexpr uint64_t boxF32(uint32_t v)
Definition: float.hh:80
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

Generated on Tue Sep 21 2021 12:24:51 for gem5 by doxygen 1.8.17