gem5  v21.1.0.2
rtc_pl031.cc
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37 
38 #include "dev/arm/rtc_pl031.hh"
39 
40 #include "base/intmath.hh"
41 #include "base/time.hh"
42 #include "base/trace.hh"
43 #include "debug/Checkpoint.hh"
44 #include "debug/Timer.hh"
45 #include "dev/arm/amba_device.hh"
46 #include "mem/packet.hh"
47 #include "mem/packet_access.hh"
48 
49 namespace gem5
50 {
51 
53  : AmbaIntDevice(p, 0x1000), lastWrittenTick(0), loadVal(0), matchVal(0),
54  rawInt(false), maskInt(false), pendingInt(false),
55  matchEvent([this]{ counterMatch(); }, name())
56 {
57  // Make a temporary copy so mkutctime can modify it.
58  struct tm local_time = p.time;
59  timeVal = mkutctime(&local_time);
60 }
61 
62 
63 Tick
65 {
66  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
67  assert(pkt->getSize() <= 4);
68  Addr daddr = pkt->getAddr() - pioAddr;
69  uint32_t data;
70 
71  DPRINTF(Timer, "Reading from RTC at offset: %#x\n", daddr);
72 
73  switch (daddr) {
74  case DataReg:
75  data = timeVal +
77  break;
78  case MatchReg:
79  data = matchVal;
80  break;
81  case LoadReg:
82  data = loadVal;
83  break;
84  case ControlReg:
85  data = 1; // Always enabled otherwise there is no point
86  break;
87  case IntMask:
88  data = maskInt;
89  break;
90  case RawISR:
91  data = rawInt;
92  break;
93  case MaskedISR:
94  data = pendingInt;
95  break;
96  default:
97  if (readId(pkt, ambaId, pioAddr)) {
98  // Hack for variable sized access
99  data = pkt->getUintX(ByteOrder::little);
100  break;
101  }
102  panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
103  break;
104  }
105 
106  pkt->setUintX(data, ByteOrder::little);
107  pkt->makeAtomicResponse();
108  return pioDelay;
109 }
110 
111 Tick
113 {
114  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
115  assert(pkt->getSize() <= 4);
116  Addr daddr = pkt->getAddr() - pioAddr;
117  DPRINTF(Timer, "Writing to RTC at offset: %#x\n", daddr);
118 
119  switch (daddr) {
120  case DataReg:
121  break;
122  case MatchReg:
123  matchVal = pkt->getLE<uint32_t>();
124  resyncMatch();
125  break;
126  case LoadReg:
128  timeVal = pkt->getLE<uint32_t>();
129  loadVal = timeVal;
130  resyncMatch();
131  break;
132  case ControlReg:
133  break; // Can't stop when started
134  case IntMask:
135  maskInt = pkt->getLE<uint32_t>();
136  break;
137  case IntClear:
138  if (pkt->getLE<uint32_t>()) {
139  rawInt = false;
140  pendingInt = false;
141  }
142  break;
143  default:
144  if (readId(pkt, ambaId, pioAddr))
145  break;
146  panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
147  break;
148  }
149 
150  pkt->makeAtomicResponse();
151  return pioDelay;
152 }
153 
154 void
156 {
157  DPRINTF(Timer, "Setting up new match event match=%d time=%d\n", matchVal,
158  timeVal);
159 
160  uint32_t seconds_until = matchVal - timeVal;
161  Tick ticks_until = sim_clock::as_int::s * seconds_until;
162 
163  if (matchEvent.scheduled()) {
164  DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
166  }
167  schedule(matchEvent, curTick() + ticks_until);
168  DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + ticks_until);
169 }
170 
171 void
173 {
174  DPRINTF(Timer, "Counter reached zero\n");
175 
176  rawInt = true;
177  bool old_pending = pendingInt;
179  if (pendingInt && !old_pending) {
180  DPRINTF(Timer, "-- Causing interrupt\n");
181  interrupt->raise();
182  }
183 }
184 
185 void
187 {
188  DPRINTF(Checkpoint, "Serializing Arm PL031\n");
196 
197  bool is_in_event = matchEvent.scheduled();
198  SERIALIZE_SCALAR(is_in_event);
199 
200  Tick event_time;
201  if (is_in_event){
202  event_time = matchEvent.when();
203  SERIALIZE_SCALAR(event_time);
204  }
205 }
206 
207 void
209 {
210  DPRINTF(Checkpoint, "Unserializing Arm PL031\n");
211 
219 
220  bool is_in_event;
221  UNSERIALIZE_SCALAR(is_in_event);
222 
223  Tick event_time;
224  if (is_in_event){
225  UNSERIALIZE_SCALAR(event_time);
226  schedule(matchEvent, event_time);
227  }
228 }
229 
230 } // namespace gem5
gem5::AmbaPioDevice::ambaId
uint64_t ambaId
Definition: amba_device.hh:81
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Event::when
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:508
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
gem5::PL031::LoadReg
@ LoadReg
Definition: rtc_pl031.hh:58
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:334
gem5::PL031::lastWrittenTick
Tick lastWrittenTick
Definition: rtc_pl031.hh:71
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::PL031::MaskedISR
@ MaskedISR
Definition: rtc_pl031.hh:62
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::PL031::PL031
PL031(const Params &p)
The constructor for RealView just registers itself with the MMU.
Definition: rtc_pl031.cc:52
amba_device.hh
gem5::CheckpointIn
Definition: serialize.hh:68
time.hh
gem5::PL031::pendingInt
bool pendingInt
If an interrupt is currently pending.
Definition: rtc_pl031.hh:92
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::PL031::loadVal
uint32_t loadVal
Definition: rtc_pl031.hh:74
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::PL031::maskInt
bool maskInt
If the timer interrupt mask that is anded with the raw interrupt to generate a pending interrupt.
Definition: rtc_pl031.hh:88
gem5::sim_clock::as_int::s
Tick s
second
Definition: core.cc:68
gem5::AmbaPioDevice::Params
AmbaPioDeviceParams Params
Definition: amba_device.hh:84
gem5::PL031::rawInt
bool rawInt
If timer has caused an interrupt.
Definition: rtc_pl031.hh:83
packet.hh
gem5::PL031::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: rtc_pl031.cc:208
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PL031::IntClear
@ IntClear
Definition: rtc_pl031.hh:63
gem5::PL031::matchEvent
EventFunctionWrapper matchEvent
Definition: rtc_pl031.hh:96
rtc_pl031.hh
gem5::PL031::counterMatch
void counterMatch()
Called when the counter reaches matches.
Definition: rtc_pl031.cc:172
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::PowerISA::tm
Bitfield< 32 > tm
Definition: misc.hh:107
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::PL031::timeVal
uint32_t timeVal
Definition: rtc_pl031.hh:68
packet_access.hh
gem5::PL031::ControlReg
@ ControlReg
Definition: rtc_pl031.hh:59
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
gem5::PL031::DataReg
@ DataReg
Definition: rtc_pl031.hh:56
gem5::AmbaIntDevice
Definition: amba_device.hh:88
gem5::AmbaIntDevice::interrupt
ArmInterruptPin *const interrupt
Definition: amba_device.hh:91
gem5::mkutctime
time_t mkutctime(struct tm *time)
Definition: time.cc:154
gem5::PL031::IntMask
@ IntMask
Definition: rtc_pl031.hh:60
gem5::PL031::RawISR
@ RawISR
Definition: rtc_pl031.hh:61
gem5::PL031::MatchReg
@ MatchReg
Definition: rtc_pl031.hh:57
gem5::PL031::matchVal
uint32_t matchVal
Definition: rtc_pl031.hh:79
gem5::PL031::read
Tick read(PacketPtr pkt) override
Handle a read to the device.
Definition: rtc_pl031.cc:64
gem5::PL031::resyncMatch
void resyncMatch()
Called to update the matchEvent when the load Value or match value are written.
Definition: rtc_pl031.cc:155
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
gem5::AmbaDevice::readId
bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
Definition: amba_device.cc:75
trace.hh
gem5::PL031::write
Tick write(PacketPtr pkt) override
Handle writes to the device.
Definition: rtc_pl031.cc:112
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
intmath.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Packet::setUintX
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition: packet.cc:351
gem5::PL031::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: rtc_pl031.cc:186
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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