gem5 v24.0.0.0
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decoder.hh
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1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
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7 * met: redistributions of source code must retain the above copyright
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14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27 */
28
29#ifndef __ARCH_SPARC_DECODER_HH__
30#define __ARCH_SPARC_DECODER_HH__
31
34#include "arch/sparc/types.hh"
35#include "cpu/static_inst.hh"
36#include "debug/Decode.hh"
37#include "params/SparcDecoder.hh"
38
39namespace gem5
40{
41
42class BaseISA;
43
44namespace SparcISA
45{
46
47class Decoder : public InstDecoder
48{
49 protected:
50 // The extended machine instruction being generated
52 uint32_t machInst;
54
55 public:
56 Decoder(const SparcDecoderParams &p) : InstDecoder(p, &machInst) {}
57
58 // Use this to give data to the predecoder. This should be used
59 // when there is control flow.
60 void
61 moreBytes(const PCStateBase &pc, Addr fetchPC) override
62 {
64 // The I bit, bit 13, is used to figure out where the ASI
65 // should come from. Use that in the ExtMachInst. This is
66 // slightly redundant, but it removes the need to put a condition
67 // into all the execute functions
68 if (emi & (1 << 13)) {
69 emi |= (static_cast<ExtMachInst>(
70 asi << (sizeof(machInst) * 8)));
71 } else {
72 emi |= (static_cast<ExtMachInst>(bits(emi, 12, 5))
73 << (sizeof(machInst) * 8));
74 }
75 instDone = true;
76 }
77
78 void
80 {
81 asi = _asi;
82 }
83
84 protected:
88
90
96 {
97 StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
98 DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
99 si->getName(), mach_inst);
100 return si;
101 }
102
103 public:
105 decode(PCStateBase &next_pc) override
106 {
107 if (!instDone)
108 return NULL;
109 instDone = false;
110 return decode(emi, next_pc.instAddr());
111 }
112};
113
114} // namespace SparcISA
115} // namespace gem5
116
117#endif // __ARCH_SPARC_DECODER_HH__
#define DPRINTF(x,...)
Definition trace.hh:210
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition decoder.hh:86
void setContext(RegVal _asi)
Definition decoder.hh:79
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition decoder.hh:61
StaticInstPtr decode(PCStateBase &next_pc) override
Decode an instruction or fetch it from the code cache.
Definition decoder.hh:105
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Decoder(const SparcDecoderParams &p)
Definition decoder.hh:56
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition decoder.hh:95
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
Bitfield< 6 > si
Bitfield< 4 > pc
Bitfield< 0 > p
uint64_t ExtMachInst
Definition types.hh:42
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t RegVal
Definition types.hh:173
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
T betoh(T value)
Definition byteswap.hh:175

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