gem5  v21.1.0.2
timer_cpulocal.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2011,2018 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __DEV_ARM_LOCALTIMER_HH__
39 #define __DEV_ARM_LOCALTIMER_HH__
40 
41 #include <cstdint>
42 #include <memory>
43 #include <vector>
44 
45 #include "base/bitunion.hh"
46 #include "base/types.hh"
47 #include "dev/io_device.hh"
48 #include "params/CpuLocalTimer.hh"
49 #include "sim/serialize.hh"
50 
56 namespace gem5
57 {
58 
59 class BaseGic;
60 class ArmInterruptPin;
61 
63 {
64  protected:
65  class Timer : public Serializable
66  {
67 
68  public:
69  enum
70  {
71  TimerLoadReg = 0x00,
81  Size = 0x38
82  };
83 
84  BitUnion32(TimerCtrl)
85  Bitfield<0> enable;
86  Bitfield<1> autoReload;
87  Bitfield<2> intEnable;
88  Bitfield<7,3> reserved;
89  Bitfield<15,8> prescalar;
90  EndBitUnion(TimerCtrl)
91 
92  BitUnion32(WatchdogCtrl)
93  Bitfield<0> enable;
94  Bitfield<1> autoReload;
95  Bitfield<2> intEnable;
96  Bitfield<3> watchdogMode;
97  Bitfield<7,4> reserved;
98  Bitfield<15,8> prescalar;
99  EndBitUnion(WatchdogCtrl)
100 
101  protected:
102  std::string _name;
103 
106 
110 
112  TimerCtrl timerControl;
113  WatchdogCtrl watchdogControl;
114 
121 
126 
128  uint32_t timerLoadValue;
130 
132  void timerAtZero();
134 
135  void watchdogAtZero();
137  public:
140  void restartTimerCounter(uint32_t val);
141  void restartWatchdogCounter(uint32_t val);
142 
143  Timer(const std::string &name,
144  CpuLocalTimer* _parent,
145  ArmInterruptPin* int_timer,
146  ArmInterruptPin* int_watchdog);
147 
148  std::string name() const { return _name; }
149 
151  void read(PacketPtr pkt, Addr daddr);
152 
154  void write(PacketPtr pkt, Addr daddr);
155 
156  void serialize(CheckpointOut &cp) const override;
157  void unserialize(CheckpointIn &cp) override;
158 
159  friend class CpuLocalTimer;
160  };
161 
164 
167 
168  public:
170 
175  CpuLocalTimer(const Params &p);
176 
178  void init() override;
179 
185  Tick read(PacketPtr pkt) override;
186 
192  Tick write(PacketPtr pkt) override;
193 
194  void serialize(CheckpointOut &cp) const override;
195  void unserialize(CheckpointIn &cp) override;
196 };
197 
198 } // namespace gem5
199 
200 #endif // __DEV_ARM_SP804_HH__
io_device.hh
gem5::CpuLocalTimer::Timer::Size
@ Size
Definition: timer_cpulocal.hh:81
gem5::CpuLocalTimer::Timer::timerControl
TimerCtrl timerControl
Control register as specified above.
Definition: timer_cpulocal.hh:112
serialize.hh
gem5::CpuLocalTimer::init
void init() override
Inits the local timers.
Definition: timer_cpulocal.cc:61
gem5::CpuLocalTimer::Timer::WatchdogIntStatusReg
@ WatchdogIntStatusReg
Definition: timer_cpulocal.hh:78
gem5::CpuLocalTimer
Definition: timer_cpulocal.hh:62
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::CpuLocalTimer::Timer::EndBitUnion
EndBitUnion(TimerCtrl) BitUnion32(WatchdogCtrl) Bitfield< 0 > enable
gem5::CpuLocalTimer::Timer::rawResetWatchdog
bool rawResetWatchdog
Definition: timer_cpulocal.hh:119
gem5::CpuLocalTimer::Timer::timerLoadValue
uint32_t timerLoadValue
Value to load into counters when periodic mode reaches 0.
Definition: timer_cpulocal.hh:128
gem5::CpuLocalTimer::PARAMS
PARAMS(CpuLocalTimer)
gem5::CpuLocalTimer::Timer::WatchdogResetStatusReg
@ WatchdogResetStatusReg
Definition: timer_cpulocal.hh:79
gem5::CpuLocalTimer::Timer::pendingIntTimer
bool pendingIntTimer
If an interrupt is currently pending.
Definition: timer_cpulocal.hh:124
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::CpuLocalTimer::Timer::Timer
Timer(const std::string &name, CpuLocalTimer *_parent, ArmInterruptPin *int_timer, ArmInterruptPin *int_watchdog)
Definition: timer_cpulocal.cc:79
gem5::CpuLocalTimer::Timer::TimerCounterReg
@ TimerCounterReg
Definition: timer_cpulocal.hh:72
gem5::CpuLocalTimer::Timer::WatchdogLoadReg
@ WatchdogLoadReg
Definition: timer_cpulocal.hh:75
gem5::CpuLocalTimer::Timer::WatchdogCounterReg
@ WatchdogCounterReg
Definition: timer_cpulocal.hh:76
std::vector
STL vector class.
Definition: stl.hh:37
gem5::CpuLocalTimer::Timer::name
std::string name() const
Definition: timer_cpulocal.hh:148
gem5::CpuLocalTimer::Timer::rawIntTimer
bool rawIntTimer
If timer has caused an interrupt.
Definition: timer_cpulocal.hh:117
gem5::CpuLocalTimer::Timer::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: timer_cpulocal.cc:395
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::CpuLocalTimer::Timer::TimerIntStatusReg
@ TimerIntStatusReg
Definition: timer_cpulocal.hh:74
gem5::CpuLocalTimer::Timer::watchdogMode
Bitfield< 3 > watchdogMode
Definition: timer_cpulocal.hh:96
gem5::CpuLocalTimer::localTimer
std::vector< std::unique_ptr< Timer > > localTimer
Timers that do the actual work.
Definition: timer_cpulocal.hh:166
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::BaseGic
Definition: base_gic.hh:72
gem5::CpuLocalTimer::gic
BaseGic * gic
Pointer to the GIC for causing an interrupt.
Definition: timer_cpulocal.hh:163
gem5::CpuLocalTimer::Timer::restartWatchdogCounter
void restartWatchdogCounter(uint32_t val)
Definition: timer_cpulocal.cc:286
gem5::CpuLocalTimer::write
Tick write(PacketPtr pkt) override
Handle a write to the device.
Definition: timer_cpulocal.cc:172
gem5::X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1057
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::CpuLocalTimer::Timer::TimerControlReg
@ TimerControlReg
Definition: timer_cpulocal.hh:73
gem5::CpuLocalTimer::Timer::intTimer
ArmInterruptPin * intTimer
Interrupt to cause/clear.
Definition: timer_cpulocal.hh:108
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::CpuLocalTimer::Timer::prescalar
Bitfield< 15, 8 > prescalar
Definition: timer_cpulocal.hh:89
bitunion.hh
gem5::CpuLocalTimer::read
Tick read(PacketPtr pkt) override
Handle a read to the device.
Definition: timer_cpulocal.cc:95
gem5::CpuLocalTimer::Timer::watchdogControl
WatchdogCtrl watchdogControl
Definition: timer_cpulocal.hh:113
gem5::CpuLocalTimer::Timer::watchdogZeroEvent
EventFunctionWrapper watchdogZeroEvent
Definition: timer_cpulocal.hh:136
gem5::CpuLocalTimer::Timer::write
void write(PacketPtr pkt, Addr daddr)
Handle write for a single timer.
Definition: timer_cpulocal.cc:191
gem5::CpuLocalTimer::Timer::intWatchdog
ArmInterruptPin * intWatchdog
Definition: timer_cpulocal.hh:109
gem5::CpuLocalTimer::Timer::restartTimerCounter
void restartTimerCounter(uint32_t val)
Restart the counter ticking at val.
Definition: timer_cpulocal.cc:268
gem5::CpuLocalTimer::Timer::watchdogAtZero
void watchdogAtZero()
Definition: timer_cpulocal.cc:328
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::CpuLocalTimer::Timer::reserved
Bitfield< 7, 4 > reserved
Definition: timer_cpulocal.hh:97
gem5::CpuLocalTimer::Timer::watchdogLoadValue
uint32_t watchdogLoadValue
Definition: timer_cpulocal.hh:129
gem5::CpuLocalTimer::Timer
Definition: timer_cpulocal.hh:65
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::CpuLocalTimer::Timer::pendingIntWatchdog
bool pendingIntWatchdog
Definition: timer_cpulocal.hh:125
gem5::CpuLocalTimer::Timer::parent
EndBitUnion(WatchdogCtrl) protected CpuLocalTimer * parent
Pointer to parent class.
Definition: timer_cpulocal.hh:99
gem5::CpuLocalTimer::Timer::intEnable
Bitfield< 2 > intEnable
Definition: timer_cpulocal.hh:87
gem5::CpuLocalTimer::Timer::timerAtZero
void timerAtZero()
Called when the counter reaches 0.
Definition: timer_cpulocal.cc:305
types.hh
gem5::CpuLocalTimer::CpuLocalTimer
CpuLocalTimer(const Params &p)
The constructor for RealView just registers itself with the MMU.
Definition: timer_cpulocal.cc:55
gem5::CpuLocalTimer::Timer::rawIntWatchdog
bool rawIntWatchdog
Definition: timer_cpulocal.hh:118
gem5::CpuLocalTimer::Timer::TimerLoadReg
@ TimerLoadReg
Definition: timer_cpulocal.hh:71
gem5::CpuLocalTimer::Timer::timerZeroEvent
EventFunctionWrapper timerZeroEvent
Definition: timer_cpulocal.hh:133
gem5::CpuLocalTimer::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: timer_cpulocal.cc:435
gem5::CpuLocalTimer::Timer::reserved
Bitfield< 7, 3 > reserved
Definition: timer_cpulocal.hh:88
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:200
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::CpuLocalTimer::Timer::BitUnion32
BitUnion32(TimerCtrl) Bitfield< 0 > enable
gem5::CpuLocalTimer::Timer::WatchdogControlReg
@ WatchdogControlReg
Definition: timer_cpulocal.hh:77
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::CpuLocalTimer::Timer::read
void read(PacketPtr pkt, Addr daddr)
Handle read for a single timer.
Definition: timer_cpulocal.cc:115
gem5::CpuLocalTimer::Timer::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: timer_cpulocal.cc:359
gem5::CpuLocalTimer::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: timer_cpulocal.cc:442
gem5::CpuLocalTimer::Timer::autoReload
Bitfield< 1 > autoReload
Definition: timer_cpulocal.hh:86
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::CpuLocalTimer::Timer::WatchdogDisableReg
@ WatchdogDisableReg
Definition: timer_cpulocal.hh:80
gem5::CpuLocalTimer::Timer::watchdogDisableReg
uint32_t watchdogDisableReg
Definition: timer_cpulocal.hh:120

Generated on Tue Sep 21 2021 12:25:15 for gem5 by doxygen 1.8.17