fetch1.hh

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 * Copyright (c) 2013-2014 ARM Limited
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 * to a hardware implementation of the functionality of the software
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 * Authors: Andrew Bardsley
 */

#ifndef __CPU_MINOR_FETCH1_HH__
#define __CPU_MINOR_FETCH1_HH__

#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "cpu/base.hh"
#include "mem/packet.hh"

namespace Minor
{

class Fetch1 : public Named
{
  protected:
    class IcachePort : public MinorCPU::MinorCPUPort
    {
      protected:
        Fetch1 &fetch;

      public:
        IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) :
            MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_)
        { }

      protected:
        bool recvTimingResp(PacketPtr pkt)
        { return fetch.recvTimingResp(pkt); }

        void recvReqRetry() { fetch.recvReqRetry(); }
    };

    class FetchRequest :
        public BaseTLB::Translation, /* For TLB lookups */
        public Packet::SenderState /* For packing into a Packet */
    {
      protected:
        Fetch1 &fetch;

      public:
        enum FetchRequestState
        {
            NotIssued, /* Just been made */
            InTranslation, /* Issued to ITLB, must wait for reqply */
            Translated, /* Translation complete */
            RequestIssuing, /* Issued to memory, must wait for response */
            Complete /* Complete.  Either a fault, or a fetched line */
        };

        FetchRequestState state;

        InstId id;

        PacketPtr packet;

        RequestPtr request;

        TheISA::PCState pc;

        Fault fault;

        void makePacket();

        void reportData(std::ostream &os) const;

        bool isDiscardable() const;

        bool isComplete() const { return state == Complete; }

      protected:
        void markDelayed() { }

        void finish(const Fault &fault_, const RequestPtr &request_,
                    ThreadContext *tc, BaseTLB::Mode mode);

      public:
        FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
            SenderState(),
            fetch(fetch_),
            state(NotIssued),
            id(id_),
            packet(NULL),
            request(),
            pc(pc_),
            fault(NoFault)
        {
            request = std::make_shared<Request>();
        }

        ~FetchRequest();
    };

    typedef FetchRequest *FetchRequestPtr;

  protected:
    MinorCPU &cpu;

    Latch<BranchData>::Output inp;
    Latch<ForwardLineData>::Input out;
    Latch<BranchData>::Output prediction;

    std::vector<InputBuffer<ForwardLineData>> &nextStageReserve;

    IcachePort icachePort;

    unsigned int lineSnap;

    unsigned int maxLineWidth;

    unsigned int fetchLimit;

  protected:
    enum FetchState
    {
        FetchHalted, /* Not fetching, waiting to be woken by transition
            to FetchWaitingForPC.  The PC is not valid in this state */
        FetchWaitingForPC, /* Not fetching, waiting for stream change.
            This doesn't stop issued fetches from being returned and
            processed or for branches to change the state to Running. */
        FetchRunning /* Try to fetch, when possible */
    };

    struct Fetch1ThreadInfo {

        Fetch1ThreadInfo() :
            state(FetchWaitingForPC),
            pc(TheISA::PCState(0)),
            streamSeqNum(InstId::firstStreamSeqNum),
            predictionSeqNum(InstId::firstPredictionSeqNum),
            blocked(false),
            wakeupGuard(false)
        { }

        Fetch1ThreadInfo(const Fetch1ThreadInfo& other) :
            state(other.state),
            pc(other.pc),
            streamSeqNum(other.streamSeqNum),
            predictionSeqNum(other.predictionSeqNum),
            blocked(other.blocked)
        { }

        FetchState state;

        TheISA::PCState pc;

        InstSeqNum streamSeqNum;

        InstSeqNum predictionSeqNum;

        bool blocked;

        bool wakeupGuard;
    };

    std::vector<Fetch1ThreadInfo> fetchInfo;
    ThreadID threadPriority;

    enum IcacheState
    {
        IcacheRunning, /* Default. Step icache queues when possible */
        IcacheNeedsRetry /* Request rejected, will be asked to retry */
    };

    typedef Queue<FetchRequestPtr,
        ReportTraitsPtrAdaptor<FetchRequestPtr>,
        NoBubbleTraits<FetchRequestPtr> >
        FetchQueue;

    FetchQueue requests;

    FetchQueue transfers;

    IcacheState icacheState;

    InstSeqNum lineSeqNum;

    unsigned int numFetchesInMemorySystem;
    unsigned int numFetchesInITLB;

  protected:
    friend std::ostream &operator <<(std::ostream &os,
        Fetch1::FetchState state);

    void changeStream(const BranchData &branch);

    void updateExpectedSeqNums(const BranchData &branch);

    void processResponse(FetchRequestPtr response,
        ForwardLineData &line);

    friend std::ostream &operator <<(std::ostream &os,
        IcacheState state);


    ThreadID getScheduledThread();

    void fetchLine(ThreadID tid);

    void tryToSendToTransfers(FetchRequestPtr request);

    bool tryToSend(FetchRequestPtr request);

    void moveFromRequestsToTransfers(FetchRequestPtr request);

    void stepQueues();

    void popAndDiscard(FetchQueue &queue);

    void handleTLBResponse(FetchRequestPtr response);

    unsigned int numInFlightFetches();

    void minorTraceResponseLine(const std::string &name,
        FetchRequestPtr response) const;

    virtual bool recvTimingResp(PacketPtr pkt);
    virtual void recvReqRetry();

  public:
    Fetch1(const std::string &name_,
        MinorCPU &cpu_,
        MinorCPUParams &params,
        Latch<BranchData>::Output inp_,
        Latch<ForwardLineData>::Input out_,
        Latch<BranchData>::Output prediction_,
        std::vector<InputBuffer<ForwardLineData>> &next_stage_input_buffer);

  public:
    MinorCPU::MinorCPUPort &getIcachePort() { return icachePort; }

    void evaluate();

    void wakeupFetch(ThreadID tid);

    void minorTrace() const;

    bool isDrained();
};

}

#endif /* __CPU_MINOR_FETCH1_HH__ */