thread_context.hh

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/*
 * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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 * All rights reserved.
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#ifndef __CPU_O3_THREAD_CONTEXT_HH__
#define __CPU_O3_THREAD_CONTEXT_HH__
 
#include "config/the_isa.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/thread_context.hh"
 
template <class Impl>
class O3ThreadContext : public ThreadContext
{
  public:
    typedef typename Impl::O3CPU O3CPU;
 
    O3CPU *cpu;
 
    bool
    schedule(PCEvent *e) override
    {
        return thread->pcEventQueue.schedule(e);
    }
    bool
    remove(PCEvent *e) override
    {
        return thread->pcEventQueue.remove(e);
    }
 
    void
    scheduleInstCountEvent(Event *event, Tick count) override
    {
        thread->comInstEventQueue.schedule(event, count);
    }
    void
    descheduleInstCountEvent(Event *event) override
    {
        thread->comInstEventQueue.deschedule(event);
    }
    Tick
    getCurrentInstCount() override
    {
        return thread->comInstEventQueue.getCurTick();
    }
 
    O3ThreadState<Impl> *thread;
 
    BaseTLB *getITBPtr() override { return cpu->itb; }
 
    BaseTLB *getDTBPtr() override { return cpu->dtb; }
 
    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
 
    BaseISA *
    getIsaPtr() override
    {
        return cpu->isa[thread->threadId()];
    }
 
    TheISA::Decoder *
    getDecoderPtr() override
    {
        return cpu->fetch.decoder[thread->threadId()];
    }
 
    BaseCPU *getCpuPtr() override { return cpu; }
 
    int cpuId() const override { return cpu->cpuId(); }
 
    uint32_t socketId() const override { return cpu->socketId(); }
 
    ContextID contextId() const override { return thread->contextId(); }
 
    void setContextId(ContextID id) override { thread->setContextId(id); }
 
    int threadId() const override { return thread->threadId(); }
    void setThreadId(int id) override { return thread->setThreadId(id); }
 
    System *getSystemPtr() override { return cpu->system; }
 
    Process *getProcessPtr() override { return thread->getProcessPtr(); }
 
    void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
 
    PortProxy &getPhysProxy() override { return thread->getPhysProxy(); }
 
    PortProxy &getVirtProxy() override;
 
    void
    initMemProxies(ThreadContext *tc) override
    {
        thread->initMemProxies(tc);
    }
 
    Status status() const override { return thread->status(); }
 
    void
    setStatus(Status new_status) override
    {
        thread->setStatus(new_status);
    }
 
    void activate() override;
 
    void suspend() override;
 
    void halt() override;
 
    void takeOverFrom(ThreadContext *old_context) override;
 
    Tick readLastActivate() override;
    Tick readLastSuspend() override;
 
    void copyArchRegs(ThreadContext *tc) override;
 
    void clearArchRegs() override;
 
    RegVal
    readReg(RegIndex reg_idx)
    {
        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                 reg_idx)).index());
    }
    RegVal
    readIntReg(RegIndex reg_idx) const override
    {
        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                 reg_idx)).index());
    }
 
    RegVal
    readFloatReg(RegIndex reg_idx) const override
    {
        return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                             reg_idx)).index());
    }
 
    const VecRegContainer &
    readVecReg(const RegId& id) const override
    {
        return readVecRegFlat(flattenRegId(id).index());
    }
 
    VecRegContainer &
    getWritableVecReg(const RegId& id) override
    {
        return getWritableVecRegFlat(flattenRegId(id).index());
    }
 
    ConstVecLane8
    readVec8BitLaneReg(const RegId& id) const override
    {
        return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
                    id.elemIndex());
    }
 
    ConstVecLane16
    readVec16BitLaneReg(const RegId& id) const override
    {
        return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
                    id.elemIndex());
    }
 
    ConstVecLane32
    readVec32BitLaneReg(const RegId& id) const override
    {
        return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
                    id.elemIndex());
    }
 
    ConstVecLane64
    readVec64BitLaneReg(const RegId& id) const override
    {
        return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
                    id.elemIndex());
    }
 
    void
    setVecLane(const RegId& reg,
               const LaneData<LaneSize::Byte>& val) override
    {
        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
    }
    void
    setVecLane(const RegId& reg,
               const LaneData<LaneSize::TwoByte>& val) override
    {
        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
    }
    void
    setVecLane(const RegId& reg,
               const LaneData<LaneSize::FourByte>& val) override
    {
        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
    }
    void
    setVecLane(const RegId& reg,
               const LaneData<LaneSize::EightByte>& val) override
    {
        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
    }
    const VecElem &
    readVecElem(const RegId& reg) const override
    {
        return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
    }
 
    const VecPredRegContainer &
    readVecPredReg(const RegId& id) const override
    {
        return readVecPredRegFlat(flattenRegId(id).index());
    }
 
    VecPredRegContainer&
    getWritableVecPredReg(const RegId& id) override
    {
        return getWritableVecPredRegFlat(flattenRegId(id).index());
    }
 
    RegVal
    readCCReg(RegIndex reg_idx) const override
    {
        return readCCRegFlat(flattenRegId(RegId(CCRegClass,
                                                 reg_idx)).index());
    }
 
    void
    setIntReg(RegIndex reg_idx, RegVal val) override
    {
        setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
    }
 
    void
    setFloatReg(RegIndex reg_idx, RegVal val) override
    {
        setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                           reg_idx)).index(), val);
    }
 
    void
    setVecReg(const RegId& reg, const VecRegContainer& val) override
    {
        setVecRegFlat(flattenRegId(reg).index(), val);
    }
 
    void
    setVecElem(const RegId& reg, const VecElem& val) override
    {
        setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
    }
 
    void
    setVecPredReg(const RegId& reg,
                  const VecPredRegContainer& val) override
    {
        setVecPredRegFlat(flattenRegId(reg).index(), val);
    }
 
    void
    setCCReg(RegIndex reg_idx, RegVal val) override
    {
        setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
    }
 
    TheISA::PCState
    pcState() const override
    {
        return cpu->pcState(thread->threadId());
    }
 
    void pcState(const TheISA::PCState &val) override;
 
    void pcStateNoRecord(const TheISA::PCState &val) override;
 
    Addr
    instAddr() const override
    {
        return cpu->instAddr(thread->threadId());
    }
 
    Addr
    nextInstAddr() const override
    {
        return cpu->nextInstAddr(thread->threadId());
    }
 
    MicroPC
    microPC() const override
    {
        return cpu->microPC(thread->threadId());
    }
 
    RegVal
    readMiscRegNoEffect(RegIndex misc_reg) const override
    {
        return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
    }
 
    RegVal
    readMiscReg(RegIndex misc_reg) override
    {
        return cpu->readMiscReg(misc_reg, thread->threadId());
    }
 
    void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
 
    void setMiscReg(RegIndex misc_reg, RegVal val) override;
 
    RegId flattenRegId(const RegId& regId) const override;
 
    // @todo: Figure out where these store cond failures should go.
    unsigned
    readStCondFailures() const override
    {
        return thread->storeCondFailures;
    }
 
    void
    setStCondFailures(unsigned sc_failures) override
    {
        thread->storeCondFailures = sc_failures;
    }
 
    void
    syscall() override
    {
        return cpu->syscall(thread->threadId());
    }
 
    Counter readFuncExeInst() const override { return thread->funcExeInst; }
 
    inline void
    conditionalSquash()
    {
        if (!thread->trapPending && !thread->noSquashFromTC)
            cpu->squashFromTC(thread->threadId());
    }
 
    RegVal readIntRegFlat(RegIndex idx) const override;
    void setIntRegFlat(RegIndex idx, RegVal val) override;
 
    RegVal readFloatRegFlat(RegIndex idx) const override;
    void setFloatRegFlat(RegIndex idx, RegVal val) override;
 
    const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
    VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
    void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
 
    template <typename VecElem>
    VecLaneT<VecElem, true>
    readVecLaneFlat(RegIndex idx, int lId) const
    {
        return cpu->template readArchVecLane<VecElem>(idx, lId,
                thread->threadId());
    }
 
    template <typename LD>
    void
    setVecLaneFlat(int idx, int lId, const LD& val)
    {
        cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
    }
 
    const VecElem &readVecElemFlat(RegIndex idx,
                                   const ElemIndex& elemIndex) const override;
    void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
                        const VecElem& val) override;
 
    const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
    VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override;
    void setVecPredRegFlat(RegIndex idx,
                           const VecPredRegContainer& val) override;
 
    RegVal readCCRegFlat(RegIndex idx) const override;
    void setCCRegFlat(RegIndex idx, RegVal val) override;
 
    // hardware transactional memory
    void htmAbortTransaction(uint64_t htm_uid,
                             HtmFailureFaultCause cause) override;
    BaseHTMCheckpointPtr& getHtmCheckpointPtr() override;
    void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
};
 
#endif