gem5 v24.0.0.0
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GarnetSyntheticTraffic.cc
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1/*
2 * Copyright (c) 2016 Georgia Institute of Technology
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
30
31#include <cmath>
32#include <iomanip>
33#include <set>
34#include <string>
35#include <vector>
36
37#include "base/logging.hh"
38#include "base/random.hh"
39#include "base/statistics.hh"
40#include "debug/GarnetSyntheticTraffic.hh"
41#include "mem/packet.hh"
42#include "mem/port.hh"
43#include "mem/request.hh"
44#include "sim/sim_events.hh"
45#include "sim/stats.hh"
46#include "sim/system.hh"
47
48namespace gem5
49{
50
52
53bool
59
60void
62{
63 tester->doRetry();
64}
65
66void
68{
69 if (!cachePort.sendTimingReq(pkt)) {
70 retryPkt = pkt; // RubyPort will retry sending
71 }
73}
74
77 tickEvent([this]{ tick(); }, "GarnetSyntheticTraffic tick",
78 false, Event::CPU_Tick_Pri),
79 cachePort("GarnetSyntheticTraffic", this),
80 retryPkt(NULL),
81 size(p.memory_size),
82 blockSizeBits(p.block_offset),
83 numDestinations(p.num_dest),
84 simCycles(p.sim_cycles),
85 numPacketsMax(p.num_packets_max),
86 numPacketsSent(0),
87 singleSender(p.single_sender),
88 singleDest(p.single_dest),
89 trafficType(p.traffic_type),
90 injRate(p.inj_rate),
91 injVnet(p.inj_vnet),
92 precision(p.precision),
93 responseLimit(p.response_limit),
94 requestorId(p.system->getRequestorId(this))
95{
96 // set up counters
97 noResponseCycles = 0;
98 schedule(tickEvent, 0);
99
100 initTrafficType();
101 if (trafficStringToEnum.count(trafficType) == 0) {
102 fatal("Unknown Traffic Type: %s!\n", traffic);
103 }
104 traffic = trafficStringToEnum[trafficType];
105
106 id = TESTER_NETWORK++;
107 DPRINTF(GarnetSyntheticTraffic,"Config Created: Name = %s , and id = %d\n",
108 name(), id);
109}
110
111Port &
112GarnetSyntheticTraffic::getPort(const std::string &if_name, PortID idx)
113{
114 if (if_name == "test")
115 return cachePort;
116 else
117 return ClockedObject::getPort(if_name, idx);
118}
119
120void
125
126
127void
129{
131 "Completed injection of %s packet for address %x\n",
132 pkt->isWrite() ? "write" : "read\n",
133 pkt->req->getPaddr());
134
135 assert(pkt->isResponse());
137 delete pkt;
138}
139
140
141void
143{
145 fatal("%s deadlocked at cycle %d\n", name(), curTick());
146 }
147
148 // make new request based on injection rate
149 // (injection rate's range depends on precision)
150 // - generate a random number between 0 and 10^precision
151 // - send pkt if this number is < injRate*(10^precision)
152 bool sendAllowedThisCycle;
153 double injRange = pow((double) 10, (double) precision);
154 unsigned trySending = random_mt.random<unsigned>(0, (int) injRange);
155 if (trySending < injRate*injRange)
156 sendAllowedThisCycle = true;
157 else
158 sendAllowedThisCycle = false;
159
160 // always generatePkt unless fixedPkts or singleSender is enabled
161 if (sendAllowedThisCycle) {
162 bool senderEnable = true;
163
165 senderEnable = false;
166
167 if (singleSender >= 0 && id != singleSender)
168 senderEnable = false;
169
170 if (senderEnable)
171 generatePkt();
172 }
173
174 // Schedule wakeup
175 if (curTick() >= simCycles)
176 exitSimLoop("Network Tester completed simCycles");
177 else {
178 if (!tickEvent.scheduled())
180 }
181}
182
183void
185{
186 int num_destinations = numDestinations;
187 int radix = (int) sqrt(num_destinations);
188 unsigned destination = id;
189 int dest_x = -1;
190 int dest_y = -1;
191 int source = id;
192 int src_x = id%radix;
193 int src_y = id/radix;
194
195 if (singleDest >= 0)
196 {
198 } else if (traffic == UNIFORM_RANDOM_) {
199 destination = random_mt.random<unsigned>(0, num_destinations - 1);
200 } else if (traffic == BIT_COMPLEMENT_) {
201 dest_x = radix - src_x - 1;
202 dest_y = radix - src_y - 1;
203 destination = dest_y*radix + dest_x;
204 } else if (traffic == BIT_REVERSE_) {
205 unsigned int straight = source;
206 unsigned int reverse = source & 1; // LSB
207
208 int num_bits = (int) log2(num_destinations);
209
210 for (int i = 1; i < num_bits; i++)
211 {
212 reverse <<= 1;
213 straight >>= 1;
214 reverse |= (straight & 1); // LSB
215 }
216 destination = reverse;
217 } else if (traffic == BIT_ROTATION_) {
218 if (source%2 == 0)
219 destination = source/2;
220 else // (source%2 == 1)
221 destination = ((source/2) + (num_destinations/2));
222 } else if (traffic == NEIGHBOR_) {
223 dest_x = (src_x + 1) % radix;
224 dest_y = src_y;
225 destination = dest_y*radix + dest_x;
226 } else if (traffic == SHUFFLE_) {
227 if (source < num_destinations/2)
228 destination = source*2;
229 else
230 destination = (source*2 - num_destinations + 1);
231 } else if (traffic == TRANSPOSE_) {
232 dest_x = src_y;
233 dest_y = src_x;
234 destination = dest_y*radix + dest_x;
235 } else if (traffic == TORNADO_) {
236 dest_x = (src_x + (int) ceil(radix/2) - 1) % radix;
237 dest_y = src_y;
238 destination = dest_y*radix + dest_x;
239 }
240 else {
241 fatal("Unknown Traffic Type: %s!\n", traffic);
242 }
243
244 // The source of the packets is a cache.
245 // The destination of the packets is a directory.
246 // The destination bits are embedded in the address after byte-offset.
247 Addr paddr = destination;
248 paddr <<= blockSizeBits;
249 unsigned access_size = 1; // Does not affect Ruby simulation
250
251 // Modeling different coherence msg types over different msg classes.
252 //
253 // GarnetSyntheticTraffic assumes the Garnet_standalone coherence protocol
254 // which models three message classes/virtual networks.
255 // These are: request, forward, response.
256 // requests and forwards are "control" packets (typically 8 bytes),
257 // while responses are "data" packets (typically 72 bytes).
258 //
259 // Life of a packet from the tester into the network:
260 // (1) This function generatePkt() generates packets of one of the
261 // following 3 types (randomly) : ReadReq, INST_FETCH, WriteReq
262 // (2) mem/ruby/system/RubyPort.cc converts these to RubyRequestType_LD,
263 // RubyRequestType_IFETCH, RubyRequestType_ST respectively
264 // (3) mem/ruby/system/Sequencer.cc sends these to the cache controllers
265 // in the coherence protocol.
266 // (4) Network_test-cache.sm tags RubyRequestType:LD,
267 // RubyRequestType:IFETCH and RubyRequestType:ST as
268 // Request, Forward, and Response events respectively;
269 // and injects them into virtual networks 0, 1 and 2 respectively.
270 // It immediately calls back the sequencer.
271 // (5) The packet traverses the network (simple/garnet) and reaches its
272 // destination (Directory), and network stats are updated.
273 // (6) Network_test-dir.sm simply drops the packet.
274 //
275 MemCmd::Command requestType;
276
277 RequestPtr req = nullptr;
279
280 // Inject in specific Vnet
281 // Vnet 0 and 1 are for control packets (1-flit)
282 // Vnet 2 is for data packets (5-flit)
283 int injReqType = injVnet;
284
285 if (injReqType < 0 || injReqType > 2)
286 {
287 // randomly inject in any vnet
288 injReqType = random_mt.random(0, 2);
289 }
290
291 if (injReqType == 0) {
292 // generate packet for virtual network 0
293 requestType = MemCmd::ReadReq;
294 req = std::make_shared<Request>(paddr, access_size, flags,
296 } else if (injReqType == 1) {
297 // generate packet for virtual network 1
298 requestType = MemCmd::ReadReq;
300 req = std::make_shared<Request>(
301 0x0, access_size, flags, requestorId, 0x0, 0);
302 req->setPaddr(paddr);
303 } else { // if (injReqType == 2)
304 // generate packet for virtual network 2
305 requestType = MemCmd::WriteReq;
306 req = std::make_shared<Request>(paddr, access_size, flags,
308 }
309
310 req->setContext(id);
311
312 //No need to do functional simulation
313 //We just do timing simulation of the network
314
316 "Generated packet with destination %d, embedded in address %x\n",
317 destination, req->getPaddr());
318
319 PacketPtr pkt = new Packet(req, requestType);
320 pkt->dataDynamic(new uint8_t[req->getSize()]);
321 pkt->senderState = NULL;
322
323 sendPkt(pkt);
324}
325
326void
328{
329 trafficStringToEnum["bit_complement"] = BIT_COMPLEMENT_;
330 trafficStringToEnum["bit_reverse"] = BIT_REVERSE_;
331 trafficStringToEnum["bit_rotation"] = BIT_ROTATION_;
332 trafficStringToEnum["neighbor"] = NEIGHBOR_;
333 trafficStringToEnum["shuffle"] = SHUFFLE_;
334 trafficStringToEnum["tornado"] = TORNADO_;
335 trafficStringToEnum["transpose"] = TRANSPOSE_;
336 trafficStringToEnum["uniform_random"] = UNIFORM_RANDOM_;
337}
338
339void
346
347void
352
353} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:210
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
GarnetSyntheticTrafficParams Params
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
std::map< std::string, TrafficType > trafficStringToEnum
void printAddr(Addr a)
Print state of address in memory system via PrintReq (for debugging).
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Command
List of all commands associated with a packet.
Definition packet.hh:85
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isResponse() const
Definition packet.hh:598
SenderState * senderState
This packet's sender state.
Definition packet.hh:545
bool isWrite() const
Definition packet.hh:594
RequestPtr req
A pointer to the original request.
Definition packet.hh:377
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
Definition packet.hh:1213
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition port.hh:603
void printAddr(Addr a)
Inject a PrintReq for the given address to print the state of that address throughout the memory syst...
Definition port.cc:178
@ INST_FETCH
The request was an instruction fetch.
Definition request.hh:115
Random random_mt
Definition random.cc:99
std::enable_if_t< std::is_integral_v< T >, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition random.hh:90
bool scheduled() const
Determine if the current event is scheduled.
Definition eventq.hh:458
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition eventq.hh:207
#define fatal(...)
This implements a cprintf based fatal() function.
Definition logging.hh:200
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
uint8_t flags
Definition helpers.cc:87
Port Object Declaration.
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 8 > a
Definition misc_types.hh:66
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition sim_events.cc:88
Declaration of the Packet class.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Declaration of Statistics objects.
const std::string & name()
Definition trace.cc:48

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