gem5  v21.1.0.2
misc.cc
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1 /*
2  * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
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38 
39 #include "arch/arm/insts/misc.hh"
40 
41 #include "cpu/reg_class.hh"
42 
43 namespace gem5
44 {
45 
46 using namespace ArmISA;
47 
48 std::string
50 {
51  std::stringstream ss;
52  printMnemonic(ss);
53  printIntReg(ss, dest);
54  ss << ", ";
55  bool foundPsr = false;
56  for (unsigned i = 0; i < numSrcRegs(); i++) {
57  const RegId& reg = srcRegIdx(i);
58  if (!reg.is(MiscRegClass)) {
59  continue;
60  }
61  if (reg.index() == MISCREG_CPSR) {
62  ss << "cpsr";
63  foundPsr = true;
64  break;
65  }
66  if (reg.index() == MISCREG_SPSR) {
67  ss << "spsr";
68  foundPsr = true;
69  break;
70  }
71  }
72  if (!foundPsr) {
73  ss << "????";
74  }
75  return ss.str();
76 }
77 
78 void
79 MsrBase::printMsrBase(std::ostream &os) const
80 {
81  printMnemonic(os);
82  bool apsr = false;
83  bool foundPsr = false;
84  for (unsigned i = 0; i < numDestRegs(); i++) {
85  const RegId& reg = destRegIdx(i);
86  if (!reg.is(MiscRegClass)) {
87  continue;
88  }
89  if (reg.index() == MISCREG_CPSR) {
90  os << "cpsr_";
91  foundPsr = true;
92  break;
93  }
94  if (reg.index() == MISCREG_SPSR) {
95  if (bits(byteMask, 1, 0)) {
96  os << "spsr_";
97  } else {
98  os << "apsr_";
99  apsr = true;
100  }
101  foundPsr = true;
102  break;
103  }
104  }
105  if (!foundPsr) {
106  os << "????";
107  return;
108  }
109  if (bits(byteMask, 3)) {
110  if (apsr) {
111  os << "nzcvq";
112  } else {
113  os << "f";
114  }
115  }
116  if (bits(byteMask, 2)) {
117  if (apsr) {
118  os << "g";
119  } else {
120  os << "s";
121  }
122  }
123  if (bits(byteMask, 1)) {
124  os << "x";
125  }
126  if (bits(byteMask, 0)) {
127  os << "c";
128  }
129 }
130 
131 std::string
133 {
134  std::stringstream ss;
135  printMsrBase(ss);
136  ccprintf(ss, ", #%#x", imm);
137  return ss.str();
138 }
139 
140 std::string
142 {
143  std::stringstream ss;
144  printMsrBase(ss);
145  ss << ", ";
146  printIntReg(ss, op1);
147  return ss.str();
148 }
149 
150 std::string
152 {
153  std::stringstream ss;
154  printMnemonic(ss);
155  printIntReg(ss, dest);
156  ss << ", ";
157  printIntReg(ss, dest2);
158  ss << ", ";
159  printMiscReg(ss, op1);
160  return ss.str();
161 }
162 
163 std::string
165 {
166  std::stringstream ss;
167  printMnemonic(ss);
168  printMiscReg(ss, dest);
169  ss << ", ";
170  printIntReg(ss, op1);
171  ss << ", ";
172  printIntReg(ss, op2);
173  return ss.str();
174 }
175 
176 std::string
178 {
179  std::stringstream ss;
180  printMnemonic(ss);
181  ccprintf(ss, "#%d", imm);
182  return ss.str();
183 }
184 
185 std::string
187 {
188  std::stringstream ss;
189  printMnemonic(ss);
190  printIntReg(ss, dest);
191  ccprintf(ss, ", #%d", imm);
192  return ss.str();
193 }
194 
195 std::string
197 {
198  std::stringstream ss;
199  printMnemonic(ss);
200  printIntReg(ss, dest);
201  ss << ", ";
202  printIntReg(ss, op1);
203  return ss.str();
204 }
205 
206 std::string
208 {
209  std::stringstream ss;
210  printMnemonic(ss);
211  printIntReg(ss, dest);
212  return ss.str();
213 }
214 
215 std::string
217  Addr pc, const loader::SymbolTable *symtab) const
218 {
219  std::stringstream ss;
220  printMnemonic(ss);
221  printIntReg(ss, dest);
222  ss << ", ";
223  printIntReg(ss, op1);
224  ss << ", ";
225  printIntReg(ss, op2);
226  ccprintf(ss, ", #%d", imm);
227  return ss.str();
228 }
229 
230 std::string
232  Addr pc, const loader::SymbolTable *symtab) const
233 {
234  std::stringstream ss;
235  printMnemonic(ss);
236  printIntReg(ss, dest);
237  ss << ", ";
238  printIntReg(ss, op1);
239  ss << ", ";
240  printIntReg(ss, op2);
241  ss << ", ";
242  printIntReg(ss, op3);
243  return ss.str();
244 }
245 
246 std::string
248  Addr pc, const loader::SymbolTable *symtab) const
249 {
250  std::stringstream ss;
251  printMnemonic(ss);
252  printIntReg(ss, dest);
253  ss << ", ";
254  printIntReg(ss, op1);
255  ss << ", ";
256  printIntReg(ss, op2);
257  return ss.str();
258 }
259 
260 std::string
262  Addr pc, const loader::SymbolTable *symtab) const
263 {
264  std::stringstream ss;
265  printMnemonic(ss);
266  printIntReg(ss, dest);
267  ss << ", ";
268  printIntReg(ss, op1);
269  ccprintf(ss, ", #%d", imm);
270  return ss.str();
271 }
272 
273 std::string
275  Addr pc, const loader::SymbolTable *symtab) const
276 {
277  std::stringstream ss;
278  printMnemonic(ss);
279  printMiscReg(ss, dest);
280  ss << ", ";
281  printIntReg(ss, op1);
282  return ss.str();
283 }
284 
285 std::string
287  Addr pc, const loader::SymbolTable *symtab) const
288 {
289  std::stringstream ss;
290  printMnemonic(ss);
291  printIntReg(ss, dest);
292  ss << ", ";
293  printMiscReg(ss, op1);
294  return ss.str();
295 }
296 
297 std::string
299  Addr pc, const loader::SymbolTable *symtab) const
300 {
301  std::stringstream ss;
302  printMnemonic(ss);
303  printIntReg(ss, dest);
304  ccprintf(ss, ", #%d, #%d", imm1, imm2);
305  return ss.str();
306 }
307 
308 std::string
310  Addr pc, const loader::SymbolTable *symtab) const
311 {
312  std::stringstream ss;
313  printMnemonic(ss);
314  printIntReg(ss, dest);
315  ss << ", ";
316  printIntReg(ss, op1);
317  ccprintf(ss, ", #%d, #%d", imm1, imm2);
318  return ss.str();
319 }
320 
321 std::string
323  Addr pc, const loader::SymbolTable *symtab) const
324 {
325  std::stringstream ss;
326  printMnemonic(ss);
327  printIntReg(ss, dest);
328  ccprintf(ss, ", #%d, ", imm);
329  printIntReg(ss, op1);
330  return ss.str();
331 }
332 
333 std::string
335  Addr pc, const loader::SymbolTable *symtab) const
336 {
337  std::stringstream ss;
338  printMnemonic(ss);
339  printIntReg(ss, dest);
340  ccprintf(ss, ", #%d, ", imm);
341  printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
342  printIntReg(ss, op1);
343  return ss.str();
344 }
345 
346 std::string
348  Addr pc, const loader::SymbolTable *symtab) const
349 {
350  return csprintf("%-10s (inst %#08x)", "unknown", encoding());
351 }
352 
353 McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
354  uint64_t _iss, MiscRegIndex _miscReg)
355  : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
356 {
357  flags[IsNonSpeculative] = true;
358  iss = _iss;
359  miscReg = _miscReg;
360 }
361 
362 Fault
364 {
365  bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
366 
367  if (hypTrap) {
368  return std::make_shared<HypervisorTrap>(machInst, iss,
370  } else {
371  return NoFault;
372  }
373 }
374 
375 std::string
377  Addr pc, const loader::SymbolTable *symtab) const
378 {
379  return csprintf("%-10s (pipe flush)", mnemonic);
380 }
381 
383  ExtMachInst _machInst, uint64_t _iss,
384  MiscRegIndex _miscReg)
385  : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg)
386 {}
387 
388 Fault
390 {
391  bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
392 
393  if (hypTrap) {
394  return std::make_shared<HypervisorTrap>(machInst, iss,
396  } else {
397  return std::make_shared<UndefinedInstruction>(machInst, false,
398  mnemonic);
399  }
400 }
401 
402 std::string
404  Addr pc, const loader::SymbolTable *symtab) const
405 {
406  return csprintf("%-10s (implementation defined)", mnemonic);
407 }
408 
409 } // namespace gem5
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::RegImmRegShiftOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:334
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
misc.hh
gem5::UnknownOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:347
gem5::McrMrcMiscInst::iss
uint64_t iss
Definition: misc.hh:409
gem5::RegMiscRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:286
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::MsrRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:141
gem5::MsrBase::printMsrBase
void printMsrBase(std::ostream &os) const
Definition: misc.cc:79
gem5::ArmISA::EC_TRAPPED_CP15_MCR_MRC
@ EC_TRAPPED_CP15_MCR_MRC
Definition: types.hh:298
gem5::RegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:247
gem5::RegImmRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:322
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:512
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:207
gem5::ArmISA::encoding
Bitfield< 27, 25 > encoding
Definition: types.hh:90
gem5::RegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:261
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::McrrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:164
gem5::RegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:196
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::RegImmImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:298
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::RegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:186
gem5::ImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:177
gem5::McrMrcImplDefined::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc.cc:389
gem5::McrMrcMiscInst::McrMrcMiscInst
McrMrcMiscInst(const char *_mnemonic, ArmISA::ExtMachInst _machInst, uint64_t _iss, ArmISA::MiscRegIndex _miscReg)
Definition: misc.cc:353
gem5::McrMrcMiscInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:376
gem5::RegRegImmImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:309
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::RegRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:216
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::MiscRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:274
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::McrMrcImplDefined::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:403
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::MsrImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:132
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::McrMrcMiscInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc.cc:363
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
reg_class.hh
gem5::McrMrcImplDefined::McrMrcImplDefined
McrMrcImplDefined(const char *_mnemonic, ArmISA::ExtMachInst _machInst, uint64_t _iss, ArmISA::MiscRegIndex _miscReg)
Definition: misc.cc:382
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::RegRegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:231
gem5::MrrcOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:151
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::MrsOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:49
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::McrMrcMiscInst::miscReg
ArmISA::MiscRegIndex miscReg
Definition: misc.hh:410
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::McrMrcMiscInst
Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is ...
Definition: misc.hh:406

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