gem5  v22.0.0.2
misc.cc
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38 
39 #include "arch/arm/insts/misc.hh"
40 #include "arch/arm/tlbi_op.hh"
41 
42 #include "cpu/reg_class.hh"
43 
44 namespace gem5
45 {
46 
47 using namespace ArmISA;
48 
49 std::string
51 {
52  std::stringstream ss;
53  printMnemonic(ss);
54  printIntReg(ss, dest);
55  ss << ", ";
56  bool foundPsr = false;
57  for (unsigned i = 0; i < numSrcRegs(); i++) {
58  const RegId& reg = srcRegIdx(i);
59  if (!reg.is(MiscRegClass)) {
60  continue;
61  }
62  if (reg.index() == MISCREG_CPSR) {
63  ss << "cpsr";
64  foundPsr = true;
65  break;
66  }
67  if (reg.index() == MISCREG_SPSR) {
68  ss << "spsr";
69  foundPsr = true;
70  break;
71  }
72  }
73  if (!foundPsr) {
74  ss << "????";
75  }
76  return ss.str();
77 }
78 
79 void
80 MsrBase::printMsrBase(std::ostream &os) const
81 {
82  printMnemonic(os);
83  bool apsr = false;
84  bool foundPsr = false;
85  for (unsigned i = 0; i < numDestRegs(); i++) {
86  const RegId& reg = destRegIdx(i);
87  if (!reg.is(MiscRegClass)) {
88  continue;
89  }
90  if (reg.index() == MISCREG_CPSR) {
91  os << "cpsr_";
92  foundPsr = true;
93  break;
94  }
95  if (reg.index() == MISCREG_SPSR) {
96  if (bits(byteMask, 1, 0)) {
97  os << "spsr_";
98  } else {
99  os << "apsr_";
100  apsr = true;
101  }
102  foundPsr = true;
103  break;
104  }
105  }
106  if (!foundPsr) {
107  os << "????";
108  return;
109  }
110  if (bits(byteMask, 3)) {
111  if (apsr) {
112  os << "nzcvq";
113  } else {
114  os << "f";
115  }
116  }
117  if (bits(byteMask, 2)) {
118  if (apsr) {
119  os << "g";
120  } else {
121  os << "s";
122  }
123  }
124  if (bits(byteMask, 1)) {
125  os << "x";
126  }
127  if (bits(byteMask, 0)) {
128  os << "c";
129  }
130 }
131 
132 std::string
134 {
135  std::stringstream ss;
136  printMsrBase(ss);
137  ccprintf(ss, ", #%#x", imm);
138  return ss.str();
139 }
140 
141 std::string
143 {
144  std::stringstream ss;
145  printMsrBase(ss);
146  ss << ", ";
147  printIntReg(ss, op1);
148  return ss.str();
149 }
150 
151 std::string
153 {
154  std::stringstream ss;
155  printMnemonic(ss);
156  printIntReg(ss, dest);
157  ss << ", ";
158  printIntReg(ss, dest2);
159  ss << ", ";
160  printMiscReg(ss, op1);
161  return ss.str();
162 }
163 
164 std::string
166 {
167  std::stringstream ss;
168  printMnemonic(ss);
169  printMiscReg(ss, dest);
170  ss << ", ";
171  printIntReg(ss, op1);
172  ss << ", ";
173  printIntReg(ss, op2);
174  return ss.str();
175 }
176 
177 std::string
179 {
180  std::stringstream ss;
181  printMnemonic(ss);
182  ccprintf(ss, "#%d", imm);
183  return ss.str();
184 }
185 
186 std::string
188 {
189  std::stringstream ss;
190  printMnemonic(ss);
191  printIntReg(ss, dest);
192  ccprintf(ss, ", #%d", imm);
193  return ss.str();
194 }
195 
196 std::string
198 {
199  std::stringstream ss;
200  printMnemonic(ss);
201  printIntReg(ss, dest);
202  ss << ", ";
203  printIntReg(ss, op1);
204  return ss.str();
205 }
206 
207 std::string
209 {
210  std::stringstream ss;
211  printMnemonic(ss);
212  printIntReg(ss, dest);
213  return ss.str();
214 }
215 
216 std::string
218  Addr pc, const loader::SymbolTable *symtab) const
219 {
220  std::stringstream ss;
221  printMnemonic(ss);
222  printIntReg(ss, dest);
223  ss << ", ";
224  printIntReg(ss, op1);
225  ss << ", ";
226  printIntReg(ss, op2);
227  ccprintf(ss, ", #%d", imm);
228  return ss.str();
229 }
230 
231 std::string
233  Addr pc, const loader::SymbolTable *symtab) const
234 {
235  std::stringstream ss;
236  printMnemonic(ss);
237  printIntReg(ss, dest);
238  ss << ", ";
239  printIntReg(ss, op1);
240  ss << ", ";
241  printIntReg(ss, op2);
242  ss << ", ";
243  printIntReg(ss, op3);
244  return ss.str();
245 }
246 
247 std::string
249  Addr pc, const loader::SymbolTable *symtab) const
250 {
251  std::stringstream ss;
252  printMnemonic(ss);
253  printIntReg(ss, dest);
254  ss << ", ";
255  printIntReg(ss, op1);
256  ss << ", ";
257  printIntReg(ss, op2);
258  return ss.str();
259 }
260 
261 std::string
263  Addr pc, const loader::SymbolTable *symtab) const
264 {
265  std::stringstream ss;
266  printMnemonic(ss);
267  printIntReg(ss, dest);
268  ss << ", ";
269  printIntReg(ss, op1);
270  ccprintf(ss, ", #%d", imm);
271  return ss.str();
272 }
273 
274 std::string
276  Addr pc, const loader::SymbolTable *symtab) const
277 {
278  std::stringstream ss;
279  printMnemonic(ss);
280  printMiscReg(ss, dest);
281  ss << ", ";
282  printIntReg(ss, op1);
283  return ss.str();
284 }
285 
286 std::string
288  Addr pc, const loader::SymbolTable *symtab) const
289 {
290  std::stringstream ss;
291  printMnemonic(ss);
292  printIntReg(ss, dest);
293  ss << ", ";
294  printMiscReg(ss, op1);
295  return ss.str();
296 }
297 
298 std::string
300  Addr pc, const loader::SymbolTable *symtab) const
301 {
302  std::stringstream ss;
303  printMnemonic(ss);
304  printIntReg(ss, dest);
305  ccprintf(ss, ", #%d, #%d", imm1, imm2);
306  return ss.str();
307 }
308 
309 std::string
311  Addr pc, const loader::SymbolTable *symtab) const
312 {
313  std::stringstream ss;
314  printMnemonic(ss);
315  printIntReg(ss, dest);
316  ss << ", ";
317  printIntReg(ss, op1);
318  ccprintf(ss, ", #%d, #%d", imm1, imm2);
319  return ss.str();
320 }
321 
322 std::string
324  Addr pc, const loader::SymbolTable *symtab) const
325 {
326  std::stringstream ss;
327  printMnemonic(ss);
328  printIntReg(ss, dest);
329  ccprintf(ss, ", #%d, ", imm);
330  printIntReg(ss, op1);
331  return ss.str();
332 }
333 
334 std::string
336  Addr pc, const loader::SymbolTable *symtab) const
337 {
338  std::stringstream ss;
339  printMnemonic(ss);
340  printIntReg(ss, dest);
341  ccprintf(ss, ", #%d, ", imm);
342  printShiftOperand(ss, op1, true, shiftAmt, int_reg::Zero, shiftType);
343  printIntReg(ss, op1);
344  return ss.str();
345 }
346 
347 std::string
349  Addr pc, const loader::SymbolTable *symtab) const
350 {
351  return csprintf("%-10s (inst %#08x)", "unknown", encoding());
352 }
353 
354 McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
355  uint64_t _iss, MiscRegIndex _miscReg)
356  : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
357 {
358  flags[IsNonSpeculative] = true;
359  iss = _iss;
360  miscReg = _miscReg;
361 }
362 
363 Fault
365 {
366  return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
367 }
368 
369 std::string
371  Addr pc, const loader::SymbolTable *symtab) const
372 {
373  return csprintf("%-10s (pipe flush)", mnemonic);
374 }
375 
377  ExtMachInst _machInst, uint64_t _iss,
378  MiscRegIndex _miscReg)
379  : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg)
380 {}
381 
382 Fault
384 {
385  Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
386  if (fault != NoFault) {
387  return fault;
388  } else {
389  return std::make_shared<UndefinedInstruction>(machInst, false,
390  mnemonic);
391  }
392 }
393 
394 std::string
396  Addr pc, const loader::SymbolTable *symtab) const
397 {
398  return csprintf("%-10s (implementation defined)", mnemonic);
399 }
400 
401 void
403 {
404  ThreadContext* tc = xc->tcBase();
405  auto isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
406  auto release = isa->getRelease();
407 
408  switch (dest_idx) {
409  case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
410  {
411  SCR scr = tc->readMiscReg(MISCREG_SCR);
412 
413  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
414  TLBIALL tlbiOp(EL1, secure);
415  tlbiOp(tc);
416  return;
417  }
418  // TLB Invalidate All, Inner Shareable
419  case MISCREG_TLBIALLIS:
420  {
421  SCR scr = tc->readMiscReg(MISCREG_SCR);
422 
423  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
424  TLBIALL tlbiOp(EL1, secure);
425  tlbiOp.broadcast(tc);
426  return;
427  }
428  // Instruction TLB Invalidate All
429  case MISCREG_ITLBIALL:
430  {
431  SCR scr = tc->readMiscReg(MISCREG_SCR);
432 
433  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
434  ITLBIALL tlbiOp(EL1, secure);
435  tlbiOp(tc);
436  return;
437  }
438  // Data TLB Invalidate All
439  case MISCREG_DTLBIALL:
440  {
441  SCR scr = tc->readMiscReg(MISCREG_SCR);
442 
443  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
444  DTLBIALL tlbiOp(EL1, secure);
445  tlbiOp(tc);
446  return;
447  }
448  // TLB Invalidate by VA
449  // mcr tlbimval(is) is invalidating all matching entries
450  // regardless of the level of lookup, since in gem5 we cache
451  // in the tlb the last level of lookup only.
452  case MISCREG_TLBIMVA:
453  case MISCREG_TLBIMVAL:
454  {
455  SCR scr = tc->readMiscReg(MISCREG_SCR);
456 
457  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
458  TLBIMVA tlbiOp(EL1,
459  secure,
460  mbits(value, 31, 12),
461  bits(value, 7,0));
462 
463  tlbiOp(tc);
464  return;
465  }
466  // TLB Invalidate by VA, Inner Shareable
467  case MISCREG_TLBIMVAIS:
468  case MISCREG_TLBIMVALIS:
469  {
470  SCR scr = tc->readMiscReg(MISCREG_SCR);
471 
472  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
473  TLBIMVA tlbiOp(EL1,
474  secure,
475  mbits(value, 31, 12),
476  bits(value, 7,0));
477 
478  tlbiOp.broadcast(tc);
479  return;
480  }
481  // TLB Invalidate by ASID match
482  case MISCREG_TLBIASID:
483  {
484  SCR scr = tc->readMiscReg(MISCREG_SCR);
485 
486  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
487  TLBIASID tlbiOp(EL1,
488  secure,
489  bits(value, 7,0));
490 
491  tlbiOp(tc);
492  return;
493  }
494  // TLB Invalidate by ASID match, Inner Shareable
495  case MISCREG_TLBIASIDIS:
496  {
497  SCR scr = tc->readMiscReg(MISCREG_SCR);
498 
499  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
500  TLBIASID tlbiOp(EL1,
501  secure,
502  bits(value, 7,0));
503 
504  tlbiOp.broadcast(tc);
505  return;
506  }
507  // mcr tlbimvaal(is) is invalidating all matching entries
508  // regardless of the level of lookup, since in gem5 we cache
509  // in the tlb the last level of lookup only.
510  // TLB Invalidate by VA, All ASID
511  case MISCREG_TLBIMVAA:
512  case MISCREG_TLBIMVAAL:
513  {
514  SCR scr = tc->readMiscReg(MISCREG_SCR);
515 
516  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
517  TLBIMVAA tlbiOp(EL1, secure,
518  mbits(value, 31,12));
519 
520  tlbiOp(tc);
521  return;
522  }
523  // TLB Invalidate by VA, All ASID, Inner Shareable
524  case MISCREG_TLBIMVAAIS:
525  case MISCREG_TLBIMVAALIS:
526  {
527  SCR scr = tc->readMiscReg(MISCREG_SCR);
528 
529  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
530  TLBIMVAA tlbiOp(EL1, secure,
531  mbits(value, 31,12));
532 
533  tlbiOp.broadcast(tc);
534  return;
535  }
536  // mcr tlbimvalh(is) is invalidating all matching entries
537  // regardless of the level of lookup, since in gem5 we cache
538  // in the tlb the last level of lookup only.
539  // TLB Invalidate by VA, Hyp mode
540  case MISCREG_TLBIMVAH:
541  case MISCREG_TLBIMVALH:
542  {
543  SCR scr = tc->readMiscReg(MISCREG_SCR);
544 
545  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
546  TLBIMVAA tlbiOp(EL2, secure,
547  mbits(value, 31,12));
548 
549  tlbiOp(tc);
550  return;
551  }
552  // TLB Invalidate by VA, Hyp mode, Inner Shareable
553  case MISCREG_TLBIMVAHIS:
554  case MISCREG_TLBIMVALHIS:
555  {
556  SCR scr = tc->readMiscReg(MISCREG_SCR);
557 
558  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
559  TLBIMVAA tlbiOp(EL2, secure,
560  mbits(value, 31,12));
561 
562  tlbiOp.broadcast(tc);
563  return;
564  }
565  // mcr tlbiipas2l(is) is invalidating all matching entries
566  // regardless of the level of lookup, since in gem5 we cache
567  // in the tlb the last level of lookup only.
568  // TLB Invalidate by Intermediate Physical Address, Stage 2
569  case MISCREG_TLBIIPAS2:
570  case MISCREG_TLBIIPAS2L:
571  {
572  SCR scr = tc->readMiscReg(MISCREG_SCR);
573 
574  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
575  TLBIIPA tlbiOp(EL1,
576  secure,
577  static_cast<Addr>(bits(value, 35, 0)) << 12);
578 
579  tlbiOp(tc);
580  return;
581  }
582  // TLB Invalidate by Intermediate Physical Address, Stage 2,
583  // Inner Shareable
584  case MISCREG_TLBIIPAS2IS:
586  {
587  SCR scr = tc->readMiscReg(MISCREG_SCR);
588 
589  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
590  TLBIIPA tlbiOp(EL1,
591  secure,
592  static_cast<Addr>(bits(value, 35, 0)) << 12);
593 
594  tlbiOp.broadcast(tc);
595  return;
596  }
597  // Instruction TLB Invalidate by VA
598  case MISCREG_ITLBIMVA:
599  {
600  SCR scr = tc->readMiscReg(MISCREG_SCR);
601 
602  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
603  ITLBIMVA tlbiOp(EL1,
604  secure,
605  mbits(value, 31, 12),
606  bits(value, 7,0));
607 
608  tlbiOp(tc);
609  return;
610  }
611  // Data TLB Invalidate by VA
612  case MISCREG_DTLBIMVA:
613  {
614  SCR scr = tc->readMiscReg(MISCREG_SCR);
615 
616  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
617  DTLBIMVA tlbiOp(EL1,
618  secure,
619  mbits(value, 31, 12),
620  bits(value, 7,0));
621 
622  tlbiOp(tc);
623  return;
624  }
625  // Instruction TLB Invalidate by ASID match
626  case MISCREG_ITLBIASID:
627  {
628  SCR scr = tc->readMiscReg(MISCREG_SCR);
629 
630  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
631  ITLBIASID tlbiOp(EL1,
632  secure,
633  bits(value, 7,0));
634 
635  tlbiOp(tc);
636  return;
637  }
638  // Data TLB Invalidate by ASID match
639  case MISCREG_DTLBIASID:
640  {
641  SCR scr = tc->readMiscReg(MISCREG_SCR);
642 
643  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
644  DTLBIASID tlbiOp(EL1,
645  secure,
646  bits(value, 7,0));
647 
648  tlbiOp(tc);
649  return;
650  }
651  // TLB Invalidate All, Non-Secure Non-Hyp
652  case MISCREG_TLBIALLNSNH:
653  {
654  TLBIALLN tlbiOp(EL1);
655  tlbiOp(tc);
656  return;
657  }
658  // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
660  {
661  TLBIALLN tlbiOp(EL1);
662  tlbiOp.broadcast(tc);
663  return;
664  }
665  // TLB Invalidate All, Hyp mode
666  case MISCREG_TLBIALLH:
667  {
668  TLBIALLN tlbiOp(EL2);
669  tlbiOp(tc);
670  return;
671  }
672  // TLB Invalidate All, Hyp mode, Inner Shareable
673  case MISCREG_TLBIALLHIS:
674  {
675  TLBIALLN tlbiOp(EL2);
676  tlbiOp.broadcast(tc);
677  return;
678  }
679  default:
680  panic("Unrecognized TLBIOp\n");
681  }
682 }
683 
684 } // namespace gem5
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:136
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:326
gem5::RegImmRegShiftOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:335
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:334
misc.hh
gem5::UnknownOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:348
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:347
gem5::McrMrcMiscInst::iss
uint64_t iss
Definition: misc.hh:409
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:106
gem5::RegMiscRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:287
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::TlbiOp::performTlbi
void performTlbi(ExecContext *xc, ArmISA::MiscRegIndex dest_idx, RegVal value) const
Definition: misc.cc:402
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:329
gem5::MsrRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:142
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:339
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::MsrBase::printMsrBase
void printMsrBase(std::ostream &os) const
Definition: misc.cc:80
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:345
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: misc.hh:348
gem5::RegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:248
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: misc.hh:346
gem5::RegImmRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:323
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:338
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:322
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: misc.hh:342
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:330
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: misc.hh:351
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:208
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::ArmISA::encoding
Bitfield< 27, 25 > encoding
Definition: types.hh:90
gem5::RegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:262
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::McrrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:165
gem5::ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:245
gem5::ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:232
gem5::RegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:197
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:151
gem5::ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:313
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:501
gem5::RegImmImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:299
gem5::ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:258
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:333
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:332
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:340
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::RegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:187
gem5::ImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:178
gem5::McrMrcImplDefined::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc.cc:383
gem5::McrMrcMiscInst::McrMrcMiscInst
McrMrcMiscInst(const char *_mnemonic, ArmISA::ExtMachInst _machInst, uint64_t _iss, ArmISA::MiscRegIndex _miscReg)
Definition: misc.cc:354
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::McrMrcMiscInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:370
gem5::RegRegImmImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:310
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:344
gem5::RegRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:217
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
tlbi_op.hh
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::MiscRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:275
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:335
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:341
gem5::McrMrcImplDefined::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:395
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:324
gem5::MsrImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:133
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:331
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:343
gem5::McrMrcMiscInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc.cc:364
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:60
gem5::ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:149
gem5::ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:73
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:327
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: misc.hh:349
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:244
reg_class.hh
gem5::McrMrcImplDefined::McrMrcImplDefined
McrMrcImplDefined(const char *_mnemonic, ArmISA::ExtMachInst _machInst, uint64_t _iss, ArmISA::MiscRegIndex _miscReg)
Definition: misc.cc:376
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::RegRegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:232
gem5::MrrcOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:152
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:327
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:323
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:336
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:337
gem5::MrsOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:50
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:259
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:325
gem5::ArmISA::cc_reg::Zero
constexpr RegId Zero(CCRegClass, _ZeroIdx)
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:350
gem5::ArmISA::ISA::getRelease
const ArmRelease * getRelease() const
Definition: isa.hh:641
gem5::McrMrcMiscInst::miscReg
ArmISA::MiscRegIndex miscReg
Definition: misc.hh:410
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:341
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:328
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::McrMrcMiscInst
Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is ...
Definition: misc.hh:406

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