gem5  v22.0.0.1
faults.cc
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1 /*
2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
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10  * redistributions in binary form must reproduce the above copyright
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15  * this software without specific prior written permission.
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28  */
29 
30 #include "arch/mips/faults.hh"
31 
33 #include "base/trace.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "debug/MipsPRA.hh"
37 #include "mem/page_table.hh"
38 #include "sim/process.hh"
39 
40 namespace gem5
41 {
42 
43 namespace MipsISA
44 {
45 
47 
49  { "Syscall", 0x180, ExcCodeSys };
50 
52  { "Reserved Instruction Fault", 0x180, ExcCodeRI };
53 
55  { "Thread Fault", 0x180, ExcCodeDummy };
56 
58  { "Integer Overflow Exception", 0x180, ExcCodeOv };
59 
61  { "Trap", 0x180, ExcCodeTr };
62 
64  { "Breakpoint", 0x180, ExcCodeBp };
65 
67  { "DSP Disabled Fault", 0x180, ExcCodeDummy };
68 
70  { "Machine Check", 0x180, ExcCodeMCheck };
71 
73  { "Reset Fault", 0x000, ExcCodeDummy };
74 
76  { "Soft Reset Fault", 0x000, ExcCodeDummy };
77 
79  { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
80 
82  { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
83 
85  { "Interrupt", 0x000, ExcCodeInt };
86 
88  { "Address Error", 0x180, ExcCodeDummy };
89 
91  { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
92 
94  { "TLB Refill Exception", 0x180, ExcCodeDummy };
95 
97  { "TLB Modified Exception", 0x180, ExcCodeMod };
98 
99 void
101 {
102  // modify SRS Ctl - Save CSS, put ESS into CSS
103  StatusReg status = tc->readMiscReg(MISCREG_STATUS);
104  if (status.exl != 1 && status.bev != 1) {
105  // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
106  SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
107  srsCtl.pss = srsCtl.css;
108  srsCtl.css = srsCtl.ess;
109  tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
110  }
111 
112  // set EXL bit (don't care if it is already set!)
113  status.exl = 1;
115 
116  // write EPC
117  auto pc = tc->pcState().as<PCState>();
118  DPRINTF(MipsPRA, "PC: %s\n", pc);
119  bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
121  pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
122 
123  // Set Cause_EXCCODE field
124  CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
125  cause.excCode = excCode;
126  cause.bd = delay_slot ? 1 : 0;
127  cause.ce = 0;
128  tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
129 }
130 
131 void
133 {
134  if (FullSystem) {
135  DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
136  setExceptionState(tc, code());
137  tc->pcState(vect(tc));
138  } else {
139  panic("Fault %s encountered.\n", name());
140  }
141 }
142 
143 void
145 {
146  if (FullSystem) {
147  DPRINTF(MipsPRA, "%s encountered.\n", name());
148  /* All reset activity must be invoked from here */
149  Addr handler = vect(tc);
150  tc->pcState(handler);
151  DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
152  }
153 
154  // Set Coprocessor 1 (Floating Point) To Usable
155  StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
156  status.cu.cu1 = 1;
158 }
159 
160 void
162 {
163  panic("Soft reset not implemented.\n");
164 }
165 
166 void
168 {
169  panic("Non maskable interrupt not implemented.\n");
170 }
171 
172 } // namespace MipsISA
173 } // namespace gem5
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::MipsISA::ExcCodeMod
@ ExcCodeMod
Definition: faults.hh:55
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::MipsFaultBase::vect
FaultVect vect(ThreadContext *tc) const
Definition: faults.hh:100
gem5::MipsISA::excCode
Bitfield< 6, 2 > excCode
Definition: pra_constants.hh:199
faults.hh
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
pra_constants.hh
gem5::MipsISA::ExcCodeDummy
@ ExcCodeDummy
Definition: faults.hh:52
gem5::MipsISA::ExcCodeTr
@ ExcCodeTr
Definition: faults.hh:67
gem5::GenericISA::DelaySlotPCState< 4 >
gem5::MipsISA::MISCREG_SRSCTL
@ MISCREG_SRSCTL
Definition: misc.hh:98
gem5::FaultBase::name
virtual FaultName name() const =0
gem5::MipsISA::MipsFault
Definition: faults.hh:110
gem5::RefCountingPtr< StaticInst >
gem5::MipsISA::ExcCodeOv
@ ExcCodeOv
Definition: faults.hh:66
gem5::MipsISA::ExcCodeBp
@ ExcCodeBp
Definition: faults.hh:63
gem5::MipsISA::MipsFaultBase::code
virtual ExcCode code() const =0
gem5::MipsISA::ExcCodeCpU
@ ExcCodeCpU
Definition: faults.hh:65
gem5::MipsISA::ExcCodeRI
@ ExcCodeRI
Definition: faults.hh:64
gem5::MipsISA::MipsFaultBase::FaultVals
Definition: faults.hh:79
gem5::MipsISA::MipsFaultBase::setExceptionState
void setExceptionState(ThreadContext *, uint8_t)
Definition: faults.cc:100
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
process.hh
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MipsISA::MipsFaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:132
gem5::MipsISA::MISCREG_EPC
@ MISCREG_EPC
Definition: misc.hh:103
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::MipsISA::FaultVals
MipsFaultBase::FaultVals FaultVals
Definition: faults.cc:46
gem5::MipsISA::MachInst
uint32_t MachInst
Definition: types.hh:42
gem5::MipsISA::ExcCodeInt
@ ExcCodeInt
Definition: faults.hh:54
gem5::MipsISA::ExcCodeMCheck
@ ExcCodeMCheck
Definition: faults.hh:71
base.hh
gem5::MipsISA::ExcCodeSys
@ ExcCodeSys
Definition: faults.hh:62
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
trace.hh
gem5::MipsISA::ResetFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:144
gem5::MipsISA::MISCREG_CAUSE
@ MISCREG_CAUSE
Definition: misc.hh:101
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::MipsFault< ResetFault >::name
FaultName name() const
Definition: faults.hh:115
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::MipsISA::NonMaskableInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:167
gem5::MipsISA::SoftResetFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:161
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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