gem5 v24.0.0.0
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base_cpu.hh
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1/*
2 * Copyright (c) 2012, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __ARCH_ARM_KVM_BASE_CPU_HH__
39#define __ARCH_ARM_KVM_BASE_CPU_HH__
40
41#include <vector>
42
43#include "arch/arm/pcstate.hh"
44#include "cpu/kvm/base.hh"
45#include "dev/arm/base_gic.hh"
46
47struct kvm_reg_list;
48struct kvm_vcpu_init;
49
50namespace gem5
51{
52
53struct BaseArmKvmCPUParams;
54
56{
57 public:
58 BaseArmKvmCPU(const BaseArmKvmCPUParams &params);
59 virtual ~BaseArmKvmCPU();
60
61 void startup() override;
62
63 protected:
64 Tick kvmRun(Tick ticks) override;
65
66 void
67 stutterPC(PCStateBase &pc) const override
68 {
69 pc.as<ArmISA::PCState>().setNPC(pc.instAddr());
70 }
71
73 void ioctlRun() override;
74
79
86
96
97 protected:
99
110 const RegIndexVector &getRegList() const;
111
122 void kvmArmVCpuInit(const kvm_vcpu_init &init);
123
124 private:
125 std::unique_ptr<kvm_reg_list> tryGetRegList(uint64_t nelem) const;
126
134 bool getRegList(kvm_reg_list &regs) const;
135
140};
141
142} // namespace gem5
143
144#endif // __ARCH_ARM_KVM_BASE_CPU_HH__
Base class for ARM GIC implementations.
Generic representation of an Arm interrupt pin.
Definition base_gic.hh:200
std::unique_ptr< kvm_reg_list > tryGetRegList(uint64_t nelem) const
std::vector< uint64_t > RegIndexVector
Definition base_cpu.hh:98
Tick kvmRun(Tick ticks) override
Request KVM to run the guest for a given number of ticks.
Definition base_cpu.cc:117
void ioctlRun() override
Override for synchronizing state in kvm_run.
Definition base_cpu.cc:171
bool fiqAsserted
Cached state of the FIQ line.
Definition base_cpu.hh:78
bool irqAsserted
Cached state of the IRQ line.
Definition base_cpu.hh:76
const RegIndexVector & getRegList() const
Get a list of registers supported by getOneReg() and setOneReg().
Definition base_cpu.cc:191
void startup() override
startup() is the final initialization call before simulation.
Definition base_cpu.cc:94
uint64_t prevDeviceIRQLevel
KVM records whether each in-kernel device IRQ is asserted or disasserted in the kvmRunState->s....
Definition base_cpu.hh:95
BaseArmKvmCPU(const BaseArmKvmCPUParams &params)
Definition base_cpu.cc:82
void stutterPC(PCStateBase &pc) const override
Modify a PCStatePtr's value so that its next PC is the current PC.
Definition base_cpu.hh:67
RegIndexVector _regIndexList
Cached copy of the list of registers supported by KVM.
Definition base_cpu.hh:139
virtual ~BaseArmKvmCPU()
Definition base_cpu.cc:89
ArmInterruptPin * virtTimerPin
If the user-space GIC and the kernel-space timer are used simultaneously, set up this interrupt pin t...
Definition base_cpu.hh:85
void kvmArmVCpuInit(const kvm_vcpu_init &init)
Tell the kernel to initialize this CPU.
Definition base_cpu.cc:220
Base class for KVM based CPU models.
Definition base.hh:88
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition base.cc:128
STL vector class.
Definition stl.hh:37
const Params & params() const
Bitfield< 4 > pc
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Tick
Tick count type.
Definition types.hh:58

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