gem5  v21.1.0.2
base_cpu.cc
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37 
38 #include "arch/arm/kvm/base_cpu.hh"
39 
40 #include <linux/kvm.h>
41 #include <mutex>
42 
43 #include "arch/arm/interrupts.hh"
45 #include "debug/KvmInt.hh"
46 #include "dev/arm/generic_timer.hh"
47 #include "params/BaseArmKvmCPU.hh"
48 #include "params/GenericTimer.hh"
49 
50 namespace gem5
51 {
52 
53 using namespace ArmISA;
54 
55 #define INTERRUPT_ID(type, vcpu, irq) ( \
56  ((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
57  ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \
58  ((irq) << KVM_ARM_IRQ_NUM_SHIFT))
59 
60 #define INTERRUPT_VCPU_IRQ(vcpu) \
61  INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ)
62 
63 #define INTERRUPT_VCPU_FIQ(vcpu) \
64  INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
65 
66 namespace {
67 
76 uint64_t vtime = 0;
77 uint64_t vtime_counter = 0;
78 UncontendedMutex vtime_mutex;
79 
80 } // namespace
81 
82 BaseArmKvmCPU::BaseArmKvmCPU(const BaseArmKvmCPUParams &params)
83  : BaseKvmCPU(params),
84  irqAsserted(false), fiqAsserted(false),
85  virtTimerPin(nullptr), prevDeviceIRQLevel(0)
86 {
87 }
88 
90 {
91 }
92 
93 void
95 {
97 
98  /* TODO: This needs to be moved when we start to support VMs with
99  * multiple threads since kvmArmVCpuInit requires that all CPUs in
100  * the VM have been created.
101  */
102  struct kvm_vcpu_init target_config;
103  memset(&target_config, 0, sizeof(target_config));
104 
105  vm.kvmArmPreferredTarget(target_config);
106  if (!((ArmSystem *)system)->highestELIs64()) {
107  target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
108  }
109  kvmArmVCpuInit(target_config);
110 
111  if (!vm.hasKernelIRQChip())
112  virtTimerPin = static_cast<ArmSystem *>(system)\
113  ->getGenericTimer()->params().int_virt->get(tc);
114 }
115 
116 Tick
118 {
119  auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
120  const bool simFIQ(interrupt->checkRaw(INT_FIQ));
121  const bool simIRQ(interrupt->checkRaw(INT_IRQ));
122 
123  if (!vm.hasKernelIRQChip()) {
124  if (fiqAsserted != simFIQ) {
125  DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
127  }
128  if (irqAsserted != simIRQ) {
129  DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
131  }
132  } else {
133  warn_if(simFIQ && !fiqAsserted,
134  "FIQ raised by the simulated interrupt controller " \
135  "despite in-kernel GIC emulation. This is probably a bug.");
136 
137  warn_if(simIRQ && !irqAsserted,
138  "IRQ raised by the simulated interrupt controller " \
139  "despite in-kernel GIC emulation. This is probably a bug.");
140  }
141 
142  irqAsserted = simIRQ;
143  fiqAsserted = simFIQ;
144 
145  Tick kvmRunTicks = BaseKvmCPU::kvmRun(ticks);
146 
147  if (!vm.hasKernelIRQChip()) {
148  uint64_t device_irq_level =
149  getKvmRunState()->s.regs.device_irq_level;
150 
151  if (!(prevDeviceIRQLevel & KVM_ARM_DEV_EL1_VTIMER) &&
152  (device_irq_level & KVM_ARM_DEV_EL1_VTIMER)) {
153 
154  DPRINTF(KvmInt, "In-kernel vtimer IRQ asserted\n");
155  prevDeviceIRQLevel |= KVM_ARM_DEV_EL1_VTIMER;
156  virtTimerPin->raise();
157 
158  } else if ((prevDeviceIRQLevel & KVM_ARM_DEV_EL1_VTIMER) &&
159  !(device_irq_level & KVM_ARM_DEV_EL1_VTIMER)) {
160 
161  DPRINTF(KvmInt, "In-kernel vtimer IRQ disasserted\n");
162  prevDeviceIRQLevel &= ~KVM_ARM_DEV_EL1_VTIMER;
163  virtTimerPin->clear();
164  }
165  }
166 
167  return kvmRunTicks;
168 }
169 
170 void
172 {
173  // Check if it's the first vcpu going into KVM. If yes, it should restore
174  // the virtual time.
175  {
176  std::lock_guard<UncontendedMutex> l(vtime_mutex);
177  if (vtime_counter++ == 0)
178  setOneReg(KVM_REG_ARM_TIMER_CNT, vtime);
179  }
181  // Check if it's the last vcpu back from KVM. If yes, it should save the
182  // virtual time.
183  {
184  std::lock_guard<UncontendedMutex> l(vtime_mutex);
185  if (--vtime_counter == 0)
186  getOneReg(KVM_REG_ARM_TIMER_CNT, &vtime);
187  }
188 }
189 
192 {
193  // Do we need to request a list of registers from the kernel?
194  if (_regIndexList.size() == 0) {
195  // Start by probing for the size of the list. We do this
196  // calling the ioctl with a struct size of 0. The kernel will
197  // return the number of elements required to hold the list.
198  kvm_reg_list regs_probe;
199  regs_probe.n = 0;
200  getRegList(regs_probe);
201 
202  // Request the actual register list now that we know how many
203  // register we need to allocate space for.
204  std::unique_ptr<kvm_reg_list> regs;
205  const size_t size(sizeof(kvm_reg_list) +
206  regs_probe.n * sizeof(uint64_t));
207  regs.reset((kvm_reg_list *)operator new(size));
208  regs->n = regs_probe.n;
209  if (!getRegList(*regs))
210  panic("Failed to determine register list size.\n");
211 
212  _regIndexList.assign(regs->reg, regs->reg + regs->n);
213  }
214 
215  return _regIndexList;
216 }
217 
218 void
219 BaseArmKvmCPU::kvmArmVCpuInit(const struct kvm_vcpu_init &init)
220 {
221  if (ioctl(KVM_ARM_VCPU_INIT, (void *)&init) == -1)
222  panic("KVM: Failed to initialize vCPU\n");
223 }
224 
225 bool
226 BaseArmKvmCPU::getRegList(kvm_reg_list &regs) const
227 {
228  if (ioctl(KVM_GET_REG_LIST, (void *)&regs) == -1) {
229  if (errno == E2BIG) {
230  return false;
231  } else {
232  panic("KVM: Failed to get vCPU register list (errno: %i)\n",
233  errno);
234  }
235  } else {
236  return true;
237  }
238 }
239 
240 } // namespace gem5
gem5::BaseCPU::interrupts
std::vector< BaseInterrupts * > interrupts
Definition: base.hh:225
gem5::BaseArmKvmCPU::kvmArmVCpuInit
void kvmArmVCpuInit(const kvm_vcpu_init &init)
Tell the kernel to initialize this CPU.
Definition: base_cpu.cc:219
gem5::BaseKvmCPU::ioctl
int ioctl(int request, long p1) const
vCPU ioctl interface.
Definition: base.cc:1150
gem5::BaseArmKvmCPU::BaseArmKvmCPU
BaseArmKvmCPU(const BaseArmKvmCPUParams &params)
Definition: base_cpu.cc:82
gem5::BaseArmKvmCPU::kvmRun
Tick kvmRun(Tick ticks) override
Request KVM to run the guest for a given number of ticks.
Definition: base_cpu.cc:117
gem5::ArmISA::INT_FIQ
@ INT_FIQ
Definition: interrupts.hh:63
gem5::BaseKvmCPU::getKvmRunState
struct kvm_run * getKvmRunState()
Get a pointer to the kvm_run structure containing all the input and output parameters from kvmRun().
Definition: base.hh:308
gem5::BaseArmKvmCPU::irqAsserted
bool irqAsserted
Cached state of the IRQ line.
Definition: base_cpu.hh:69
gem5::BaseCPU::system
System * system
Definition: base.hh:376
base_cpu.hh
std::vector< uint64_t >
gem5::BaseKvmCPU::getOneReg
void getOneReg(uint64_t id, void *addr) const
Definition: base.cc:867
gem5::ArmISA::Interrupts
Definition: interrupts.hh:70
interrupts.hh
gem5::BaseKvmCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:120
gem5::BaseKvmCPU::ioctlRun
virtual void ioctlRun()
Execute the KVM_RUN ioctl.
Definition: base.cc:1311
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::BaseKvmCPU
Base class for KVM based CPU models.
Definition: base.hh:87
gem5::BaseKvmCPU::tc
ThreadContext * tc
ThreadContext object, provides an interface for external objects to modify this thread's state.
Definition: base.hh:158
gem5::BaseArmKvmCPU::fiqAsserted
bool fiqAsserted
Cached state of the FIQ line.
Definition: base_cpu.hh:71
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
INTERRUPT_VCPU_IRQ
#define INTERRUPT_VCPU_IRQ(vcpu)
Definition: base_cpu.cc:60
gem5::BaseKvmCPU::setOneReg
void setOneReg(uint64_t id, const void *addr)
Get/Set single register using the KVM_(SET|GET)_ONE_REG API.
Definition: base.cc:850
gem5::KvmVM::setIRQLine
void setIRQLine(uint32_t irq, bool high)
Set the status of an IRQ line using KVM_IRQ_LINE.
Definition: vm.cc:514
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::BaseKvmCPU::vm
KvmVM & vm
Definition: base.hh:160
gem5::BaseKvmCPU::vcpuID
const long vcpuID
KVM internal ID of the vCPU.
Definition: base.hh:648
gem5::BaseArmKvmCPU::_regIndexList
RegIndexVector _regIndexList
Cached copy of the list of registers supported by KVM.
Definition: base_cpu.hh:132
generic_timer.hh
gem5::BaseArmKvmCPU::prevDeviceIRQLevel
uint64_t prevDeviceIRQLevel
KVM records whether each in-kernel device IRQ is asserted or disasserted in the kvmRunState->s....
Definition: base_cpu.hh:88
uncontended_mutex.hh
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:272
gem5::ArmSystem
Definition: system.hh:62
gem5::BaseArmKvmCPU::virtTimerPin
ArmInterruptPin * virtTimerPin
If the user-space GIC and the kernel-space timer are used simultaneously, set up this interrupt pin t...
Definition: base_cpu.hh:78
gem5::ArmISA::INT_IRQ
@ INT_IRQ
Definition: interrupts.hh:62
gem5::BaseArmKvmCPU::~BaseArmKvmCPU
virtual ~BaseArmKvmCPU()
Definition: base_cpu.cc:89
gem5::BaseArmKvmCPU::getRegList
const RegIndexVector & getRegList() const
Get a list of registers supported by getOneReg() and setOneReg().
Definition: base_cpu.cc:191
gem5::statistics::init
const FlagsType init
This Stat is Initialized.
Definition: info.hh:56
gem5::BaseKvmCPU::kvmRun
virtual Tick kvmRun(Tick ticks)
Request KVM to run the guest for a given number of ticks.
Definition: base.cc:694
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
gem5::BaseKvmCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:109
gem5::BaseArmKvmCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: base_cpu.cc:94
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
INTERRUPT_VCPU_FIQ
#define INTERRUPT_VCPU_FIQ(vcpu)
Definition: base_cpu.cc:63
gem5::BaseArmKvmCPU::ioctlRun
void ioctlRun() override
Override for synchronizing state in kvm_run.
Definition: base_cpu.cc:171
gem5::KvmVM::hasKernelIRQChip
bool hasKernelIRQChip() const
Is in-kernel IRQ chip emulation enabled?
Definition: vm.hh:359
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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