#include <vector_register_file.hh>

Inheritance diagram for gem5::VectorRegisterFile:

Public Types
using	VecRegContainer = TheGpuISA::VecRegContainerU32

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	VectorRegisterFile (const VectorRegisterFileParams &p)

	~VectorRegisterFile ()

virtual bool	operandsReady (Wavefront *w, GPUDynInstPtr ii) const override

virtual void	scheduleWriteOperands (Wavefront *w, GPUDynInstPtr ii) override

virtual void	scheduleWriteOperandsFromLoad (Wavefront *w, GPUDynInstPtr ii) override

virtual void	waveExecuteInst (Wavefront *w, GPUDynInstPtr ii) override

void	setParent (ComputeUnit *_computeUnit) override

VecRegContainer &	readWriteable (int regIdx)

const VecRegContainer &	read (int regIdx) const

void	write (int regIdx, const VecRegContainer &value)

void	printReg (Wavefront *wf, int regIdx) const

Public Member Functions inherited from gem5::RegisterFile
	RegisterFile (const RegisterFileParams &p)

virtual	~RegisterFile ()

int	numRegs () const

virtual bool	regBusy (int idx) const

virtual void	markReg (int regIdx, bool value)

virtual void	enqRegFreeEvent (uint32_t regIdx, uint64_t delay)

virtual void	enqRegBusyEvent (uint32_t regIdx, uint64_t delay)

virtual bool	canScheduleReadOperands (Wavefront *w, GPUDynInstPtr ii)

virtual bool	canScheduleWriteOperands (Wavefront *w, GPUDynInstPtr ii)

virtual void	scheduleReadOperands (Wavefront *w, GPUDynInstPtr ii)

virtual bool	operandReadComplete (Wavefront *w, GPUDynInstPtr ii)

virtual bool	canScheduleWriteOperandsFromLoad (Wavefront *w, GPUDynInstPtr ii)

virtual void	exec ()

virtual std::string	dump () const

virtual void	dispatchInstruction (GPUDynInstPtr ii)

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected.

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbePoints ()
	Register probe points for this object.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index.

virtual void	startup ()
	startup() is the final initialization call before simulation.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters.

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Private Attributes
std::vector< VecRegContainer >	regFile

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain.

void	signalDrainDone () const
	Signal that an object is drained.

Protected Attributes inherited from gem5::RegisterFile
ComputeUnit *	computeUnit

int	simdId

std::vector< bool >	busy

int	_numRegs

gem5::RegisterFile::RegisterFileStats	stats

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Detailed Description

Definition at line 47 of file vector_register_file.hh.

Member Typedef Documentation

◆ VecRegContainer

using gem5::VectorRegisterFile::VecRegContainer = TheGpuISA::VecRegContainerU32

Definition at line 50 of file vector_register_file.hh.

Constructor & Destructor Documentation

◆ VectorRegisterFile()

gem5::VectorRegisterFile::VectorRegisterFile ( const VectorRegisterFileParams & p )

Definition at line 49 of file vector_register_file.cc.

References gem5::RegisterFile::numRegs(), gem5::X86ISA::reg, and regFile.

◆ ~VectorRegisterFile()

gem5::VectorRegisterFile::~VectorRegisterFile ( )

inline

Definition at line 53 of file vector_register_file.hh.

Member Function Documentation

◆ operandsReady()

bool gem5::VectorRegisterFile::operandsReady	(	Wavefront *	w,
		GPUDynInstPtr	ii ) const

overridevirtual

Reimplemented from gem5::RegisterFile.

Definition at line 60 of file vector_register_file.cc.

References gem5::RegisterFile::computeUnit, DPRINTF, gem5::RegisterFile::regBusy(), gem5::ComputeUnit::rfc, gem5::RegisterFile::simdId, and gem5::MipsISA::w.

◆ printReg()

void gem5::VectorRegisterFile::printReg	(	Wavefront *	wf,
		int	regIdx ) const

inline

Definition at line 90 of file vector_register_file.hh.

References DPRINTF, gem5::Wavefront::execMask(), regFile, gem5::Wavefront::simdId, gem5::Wavefront::wfDynId, and gem5::Wavefront::wfSlotId.

◆ read()

const VecRegContainer & gem5::VectorRegisterFile::read ( int regIdx ) const

inline

Definition at line 77 of file vector_register_file.hh.

References regFile.

◆ readWriteable()

VecRegContainer & gem5::VectorRegisterFile::readWriteable ( int regIdx )

inline

Definition at line 70 of file vector_register_file.hh.

References regFile.

◆ scheduleWriteOperands()

void gem5::VectorRegisterFile::scheduleWriteOperands	(	Wavefront *	w,
		GPUDynInstPtr	ii )

overridevirtual

if the instruction is a load with EXEC = 0, then we do not mark the reg. We do this to avoid a deadlock that can occur because a load reserves its destination regs before checking its exec mask, and in the cas it is 0, it will not send/recv any packets, and therefore it will never free its dst reg(s)

Reimplemented from gem5::RegisterFile.

Definition at line 99 of file vector_register_file.cc.

References gem5::RegisterFile::markReg().

◆ scheduleWriteOperandsFromLoad()

void gem5::VectorRegisterFile::scheduleWriteOperandsFromLoad	(	Wavefront *	w,
		GPUDynInstPtr	ii )

overridevirtual

Reimplemented from gem5::RegisterFile.

Definition at line 184 of file vector_register_file.cc.

References gem5::Clocked::clockPeriod(), gem5::RegisterFile::computeUnit, gem5::RegisterFile::enqRegFreeEvent(), gem5::ArmISA::i, gem5::ArmISA::mask, gem5::RegisterFile::RegisterFileStats::registerWrites, gem5::statistics::ScalarBase< Derived, Stor >::size(), gem5::RegisterFile::RegisterFileStats::sramWrites, and gem5::RegisterFile::stats.

◆ setParent()

void gem5::VectorRegisterFile::setParent ( ComputeUnit * _computeUnit )

inlineoverridevirtual

Reimplemented from gem5::RegisterFile.

Definition at line 63 of file vector_register_file.hh.

References gem5::RegisterFile::setParent().

◆ waveExecuteInst()

void gem5::VectorRegisterFile::waveExecuteInst	(	Wavefront *	w,
		GPUDynInstPtr	ii )

overridevirtual

◆ write()

void gem5::VectorRegisterFile::write	(	int	regIdx,
		const VecRegContainer &	value )

inline

Definition at line 84 of file vector_register_file.hh.

References regFile.

Member Data Documentation

◆ regFile

std::vector<VecRegContainer> gem5::VectorRegisterFile::regFile

private

Definition at line 107 of file vector_register_file.hh.

Referenced by printReg(), read(), readWriteable(), VectorRegisterFile(), and write().

The documentation for this class was generated from the following files:

gpu-compute/vector_register_file.hh
gpu-compute/vector_register_file.cc

Public Types

Public Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ VecRegContainer

Constructor & Destructor Documentation

◆ VectorRegisterFile()

◆ ~VectorRegisterFile()

Member Function Documentation

◆ operandsReady()

◆ printReg()

◆ read()

◆ readWriteable()

◆ scheduleWriteOperands()

◆ scheduleWriteOperandsFromLoad()

◆ setParent()

◆ waveExecuteInst()

◆ write()

Member Data Documentation

◆ regFile