gem5  v22.0.0.1
vector_register_file.cc
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31 
33 
34 #include <string>
35 
36 #include "base/logging.hh"
37 #include "base/trace.hh"
38 #include "debug/GPUVRF.hh"
42 #include "gpu-compute/wavefront.hh"
43 #include "params/VectorRegisterFile.hh"
44 
45 namespace gem5
46 {
47 
48 VectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams &p)
49  : RegisterFile(p)
50 {
51  regFile.resize(numRegs());
52 
53  for (auto &reg : regFile) {
54  reg.zero();
55  }
56 }
57 
58 bool
60 {
61  for (const auto& srcVecOp : ii->srcVecRegOperands()) {
62  for (const auto& physIdx : srcVecOp.physIndices()) {
63  if (regBusy(physIdx)) {
64  DPRINTF(GPUVRF, "RAW stall: WV[%d]: %s: physReg[%d]\n",
65  w->wfDynId, ii->disassemble(), physIdx);
66  w->stats.numTimesBlockedDueRAWDependencies++;
67  return false;
68  }
69  }
70  }
71 
72  for (const auto& dstVecOp : ii->dstVecRegOperands()) {
73  for (const auto& physIdx : dstVecOp.physIndices()) {
74  if (regBusy(physIdx)) {
75  DPRINTF(GPUVRF, "WAX stall: WV[%d]: %s: physReg[%d]\n",
76  w->wfDynId, ii->disassemble(), physIdx);
77  w->stats.numTimesBlockedDueWAXDependencies++;
78  return false;
79  }
80  }
81  }
82 
83  return true;
84 }
85 
86 void
88 {
89  for (const auto& dstVecOp : ii->dstVecRegOperands()) {
90  for (const auto& physIdx : dstVecOp.physIndices()) {
91  // If the instruction is atomic instruciton and the atomics do
92  // not return value, then do not mark this reg as busy.
93  if (!(ii->isAtomic() && !ii->isAtomicRet())) {
102  if (ii->exec_mask.any()) {
103  markReg(physIdx, true);
104  }
105  }
106  }
107  }
108 }
109 
110 void
112 {
113  // increment count of number of DWords read from VRF
114  int DWords = ii->numSrcVecDWords();
115  stats.registerReads += (DWords * w->execMask().count());
116 
117  uint64_t mask = w->execMask().to_ullong();
118  int srams = w->execMask().size() / 4;
119  for (int i = 0; i < srams; i++) {
120  if (mask & 0xF) {
121  stats.sramReads += DWords;
122  }
123  mask = mask >> 4;
124  }
125 
126  if (!ii->isLoad()
127  && !(ii->isAtomic() || ii->isMemSync())) {
128  // TODO: compute proper delay
129  // For now, it is based on largest operand size
130  int opSize = ii->maxOperandSize();
131  Cycles delay(opSize <= 4 ? computeUnit->spBypassLength()
133  Tick tickDelay = computeUnit->cyclesToTicks(delay);
134 
135  for (const auto& dstVecOp : ii->dstVecRegOperands()) {
136  for (const auto& physIdx : dstVecOp.physIndices()) {
137  enqRegFreeEvent(physIdx, tickDelay);
138  }
139  }
140  // increment count of number of DWords written to VRF
141  DWords = ii->numDstVecDWords();
142  stats.registerWrites += (DWords * w->execMask().count());
143 
144  mask = w->execMask().to_ullong();
145  srams = w->execMask().size() / 4;
146  for (int i = 0; i < srams; i++) {
147  if (mask & 0xF) {
148  stats.sramWrites += DWords;
149  }
150  mask = mask >> 4;
151  }
152  }
153 }
154 
155 void
158 {
159  assert(ii->isLoad() || ii->isAtomicRet());
160  for (const auto& dstVecOp : ii->dstVecRegOperands()) {
161  for (const auto& physIdx : dstVecOp.physIndices()) {
163  }
164  }
165  // increment count of number of DWords written to VRF
166  int DWords = ii->numDstVecDWords();
167  stats.registerWrites += (DWords * ii->exec_mask.count());
168 
169  uint64_t mask = ii->exec_mask.to_ullong();
170  int srams = ii->exec_mask.size() / 4;
171  for (int i = 0; i < srams; i++) {
172  if (mask & 0xF) {
173  stats.sramWrites += DWords;
174  }
175  mask = mask >> 4;
176  }
177 }
178 
179 } // namespace gem5
gem5::RegisterFile
Definition: register_file.hh:56
simple_pool_manager.hh
gem5::RegisterFile::enqRegFreeEvent
virtual void enqRegFreeEvent(uint32_t regIdx, uint64_t delay)
Definition: register_file.cc:104
gem5::VectorRegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii) override
Definition: vector_register_file.cc:87
gem5::VectorRegisterFile::regFile
std::vector< VecRegContainer > regFile
Definition: vector_register_file.hh:107
gem5::Wavefront
Definition: wavefront.hh:60
compute_unit.hh
gem5::RegisterFile::stats
gem5::RegisterFile::RegisterFileStats stats
gem5::RegisterFile::markReg
virtual void markReg(int regIdx, bool value)
Definition: register_file.cc:96
gem5::VegaISA::w
Bitfield< 6 > w
Definition: pagetable.hh:59
gem5::RegisterFile::RegisterFileStats::registerWrites
statistics::Scalar registerWrites
Definition: register_file.hh:162
gem5::VectorRegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii) override
Definition: vector_register_file.cc:156
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
wavefront.hh
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
vector_register_file.hh
gem5::VectorRegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override
Definition: vector_register_file.cc:111
gem5::RegisterFile::regBusy
virtual bool regBusy(int idx) const
Definition: register_file.cc:90
gem5::RegisterFile::RegisterFileStats::registerReads
statistics::Scalar registerReads
Definition: register_file.hh:160
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gpu_dyn_inst.hh
gem5::ComputeUnit::dpBypassLength
int dpBypassLength() const
Definition: compute_unit.hh:390
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::VectorRegisterFile::VectorRegisterFile
VectorRegisterFile(const VectorRegisterFileParams &p)
Definition: vector_register_file.cc:48
gem5::RegisterFile::numRegs
int numRegs() const
Definition: register_file.hh:62
gem5::VectorRegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override
Definition: vector_register_file.cc:59
logging.hh
gem5::RegisterFile::computeUnit
ComputeUnit * computeUnit
Definition: register_file.hh:146
trace.hh
gem5::RegisterFile::RegisterFileStats::sramWrites
statistics::Scalar sramWrites
Definition: register_file.hh:169
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RegisterFile::RegisterFileStats::sramReads
statistics::Scalar sramReads
Definition: register_file.hh:167
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217

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