gem5  v22.0.0.1
vector_register_file.hh
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31 
32 #ifndef __VECTOR_REGISTER_FILE_HH__
33 #define __VECTOR_REGISTER_FILE_HH__
34 
35 #include "arch/gpu_isa.hh"
36 #include "config/the_gpu_isa.hh"
37 #include "debug/GPUVRF.hh"
39 #include "gpu-compute/wavefront.hh"
40 
41 namespace gem5
42 {
43 
44 struct VectorRegisterFileParams;
45 
46 // Vector Register File
48 {
49  public:
51 
52  VectorRegisterFile(const VectorRegisterFileParams &p);
54 
55  virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override;
56  virtual void scheduleWriteOperands(Wavefront *w,
57  GPUDynInstPtr ii) override;
59  GPUDynInstPtr ii) override;
60  virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override;
61 
62  void
63  setParent(ComputeUnit *_computeUnit) override
64  {
65  RegisterFile::setParent(_computeUnit);
66  }
67 
68  // Read a register that is writeable (e.g., a DST operand)
70  readWriteable(int regIdx)
71  {
72  return regFile[regIdx];
73  }
74 
75  // Read a register that is not writeable (e.g., src operand)
76  const VecRegContainer&
77  read(int regIdx) const
78  {
79  return regFile[regIdx];
80  }
81 
82  // Write a register
83  void
84  write(int regIdx, const VecRegContainer &value)
85  {
86  regFile[regIdx] = value;
87  }
88 
89  void
90  printReg(Wavefront *wf, int regIdx) const
91  {
92 #ifndef NDEBUG
93  const auto &vec_reg_cont = regFile[regIdx];
94  auto vgpr = vec_reg_cont.as<TheGpuISA::VecElemU32>();
95 
96  for (int lane = 0; lane < TheGpuISA::NumVecElemPerVecReg; ++lane) {
97  if (wf->execMask(lane)) {
98  DPRINTF(GPUVRF, "WF[%d][%d]: WV[%d] v[%d][%d] = %#x\n",
99  wf->simdId, wf->wfSlotId, wf->wfDynId, regIdx, lane,
100  vgpr[lane]);
101  }
102  }
103 #endif
104  }
105 
106  private:
108 };
109 
110 } // namespace gem5
111 
112 #endif // __VECTOR_REGISTER_FILE_HH__
gem5::RegisterFile
Definition: register_file.hh:56
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::VectorRegisterFile::VecRegContainer
TheGpuISA::VecRegContainerU32 VecRegContainer
Definition: vector_register_file.hh:50
gem5::VectorRegisterFile::scheduleWriteOperands
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii) override
Definition: vector_register_file.cc:87
gem5::Gcn3ISA::VecElemU32
uint32_t VecElemU32
Definition: gpu_registers.hh:165
gem5::VectorRegisterFile::regFile
std::vector< VecRegContainer > regFile
Definition: vector_register_file.hh:107
gem5::Wavefront
Definition: wavefront.hh:60
gem5::VectorRegisterFile::printReg
void printReg(Wavefront *wf, int regIdx) const
Definition: vector_register_file.hh:90
gem5::VectorRegisterFile
Definition: vector_register_file.hh:47
gem5::VectorRegisterFile::readWriteable
VecRegContainer & readWriteable(int regIdx)
Definition: vector_register_file.hh:70
gem5::VegaISA::w
Bitfield< 6 > w
Definition: pagetable.hh:59
std::vector< VecRegContainer >
gem5::VectorRegisterFile::scheduleWriteOperandsFromLoad
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii) override
Definition: vector_register_file.cc:156
wavefront.hh
gem5::Gcn3ISA::VecRegContainerU32
VecRegContainer< sizeof(VecElemU32) *NumVecElemPerVecReg > VecRegContainerU32
Definition: gpu_registers.hh:179
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::VectorRegisterFile::~VectorRegisterFile
~VectorRegisterFile()
Definition: vector_register_file.hh:53
gem5::VectorRegisterFile::waveExecuteInst
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override
Definition: vector_register_file.cc:111
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
register_file.hh
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Wavefront::wfSlotId
const int wfSlotId
Definition: wavefront.hh:96
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:226
gem5::Wavefront::execMask
VectorMask & execMask()
Definition: wavefront.cc:1375
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::VectorRegisterFile::write
void write(int regIdx, const VecRegContainer &value)
Definition: vector_register_file.hh:84
gem5::VectorRegisterFile::VectorRegisterFile
VectorRegisterFile(const VectorRegisterFileParams &p)
Definition: vector_register_file.cc:48
gem5::VectorRegisterFile::operandsReady
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override
Definition: vector_register_file.cc:59
gem5::VectorRegisterFile::read
const VecRegContainer & read(int regIdx) const
Definition: vector_register_file.hh:77
gem5::RegisterFile::setParent
virtual void setParent(ComputeUnit *_computeUnit)
Definition: register_file.cc:64
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::VectorRegisterFile::setParent
void setParent(ComputeUnit *_computeUnit) override
Definition: vector_register_file.hh:63
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:99

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