32 #ifndef __VECTOR_REGISTER_FILE_HH__
33 #define __VECTOR_REGISTER_FILE_HH__
35 #include "arch/gpu_isa.hh"
36 #include "config/the_gpu_isa.hh"
37 #include "debug/GPUVRF.hh"
44 struct VectorRegisterFileParams;
93 const auto &vec_reg_cont =
regFile[regIdx];
98 DPRINTF(GPUVRF,
"WF[%d][%d]: WV[%d] v[%d][%d] = %#x\n",
virtual void setParent(ComputeUnit *_computeUnit)
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
virtual void scheduleWriteOperands(Wavefront *w, GPUDynInstPtr ii) override
void printReg(Wavefront *wf, int regIdx) const
VecRegContainer & readWriteable(int regIdx)
VectorRegisterFile(const VectorRegisterFileParams &p)
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override
void write(int regIdx, const VecRegContainer &value)
std::vector< VecRegContainer > regFile
TheGpuISA::VecRegContainerU32 VecRegContainer
void setParent(ComputeUnit *_computeUnit) override
virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override
const VecRegContainer & read(int regIdx) const
virtual void scheduleWriteOperandsFromLoad(Wavefront *w, GPUDynInstPtr ii) override
constexpr unsigned NumVecElemPerVecReg
VecRegContainer< sizeof(VecElemU32) *NumVecElemPerVecReg > VecRegContainerU32
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< GPUDynInst > GPUDynInstPtr