gem5  v21.1.0.2
simple_thread.hh
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41 
42 #ifndef __CPU_SIMPLE_THREAD_HH__
43 #define __CPU_SIMPLE_THREAD_HH__
44 
45 #include <algorithm>
46 #include <vector>
47 
48 #include "arch/decoder.hh"
49 #include "arch/generic/htm.hh"
50 #include "arch/generic/mmu.hh"
51 #include "arch/generic/tlb.hh"
52 #include "arch/isa.hh"
53 #include "arch/pcstate.hh"
54 #include "arch/vecregs.hh"
55 #include "base/types.hh"
56 #include "config/the_isa.hh"
57 #include "cpu/thread_context.hh"
58 #include "cpu/thread_state.hh"
59 #include "debug/CCRegs.hh"
60 #include "debug/FloatRegs.hh"
61 #include "debug/IntRegs.hh"
62 #include "debug/VecPredRegs.hh"
63 #include "debug/VecRegs.hh"
64 #include "mem/htm.hh"
65 #include "mem/page_table.hh"
66 #include "mem/request.hh"
67 #include "sim/byteswap.hh"
68 #include "sim/eventq.hh"
69 #include "sim/full_system.hh"
70 #include "sim/process.hh"
71 #include "sim/serialize.hh"
72 #include "sim/system.hh"
73 
74 namespace gem5
75 {
76 
77 class BaseCPU;
78 class CheckerCPU;
79 
94 class SimpleThread : public ThreadState, public ThreadContext
95 {
96  public:
98 
99  protected:
105  TheISA::ISA *const isa; // one "instance" of the current ISA.
106 
108 
109  // hardware transactional memory
110  std::unique_ptr<BaseHTMCheckpoint> _htmCheckpoint;
111 
113  bool predicate;
114 
117 
118  public:
119  std::string
120  name() const
121  {
122  return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
123  }
124 
131 
133 
135 
136  TheISA::Decoder decoder;
137 
138  // hardware transactional memory
141 
142  // constructor: initialize SimpleThread from given process structure
143  // FS
144  SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
145  BaseMMU *_mmu, BaseISA *_isa);
146  // SE
147  SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
148  Process *_process, BaseMMU *_mmu,
149  BaseISA *_isa);
150 
151  virtual ~SimpleThread() {}
152 
153  void takeOverFrom(ThreadContext *oldContext) override;
154 
155  void copyState(ThreadContext *oldContext);
156 
157  void serialize(CheckpointOut &cp) const override;
158  void unserialize(CheckpointIn &cp) override;
159 
160  /***************************************************************
161  * SimpleThread functions to provide CPU with access to various
162  * state.
163  **************************************************************/
164 
169  ThreadContext *getTC() { return this; }
170 
171  void
172  demapPage(Addr vaddr, uint64_t asn)
173  {
174  mmu->demapPage(vaddr, asn);
175  }
176 
177  /*******************************************
178  * ThreadContext interface functions.
179  ******************************************/
180 
181  bool schedule(PCEvent *e) override { return pcEventQueue.schedule(e); }
182  bool remove(PCEvent *e) override { return pcEventQueue.remove(e); }
183 
184  void
186  {
188  }
189  void
191  {
193  }
194  Tick
196  {
197  return comInstEventQueue.getCurTick();
198  }
199 
200  BaseCPU *getCpuPtr() override { return baseCpu; }
201 
202  int cpuId() const override { return ThreadState::cpuId(); }
203  uint32_t socketId() const override { return ThreadState::socketId(); }
204  int threadId() const override { return ThreadState::threadId(); }
205  void setThreadId(int id) override { ThreadState::setThreadId(id); }
206  ContextID contextId() const override { return ThreadState::contextId(); }
208 
209  BaseMMU *getMMUPtr() override { return mmu; }
210 
211  CheckerCPU *getCheckerCpuPtr() override { return NULL; }
212 
213  BaseISA *getIsaPtr() override { return isa; }
214 
215  TheISA::Decoder *getDecoderPtr() override { return &decoder; }
216 
217  System *getSystemPtr() override { return system; }
218 
220 
221  void
223  {
225  }
226 
229 
230  Status status() const override { return _status; }
231 
232  void setStatus(Status newStatus) override { _status = newStatus; }
233 
235  void activate() override;
236 
238  void suspend() override;
239 
241  void halt() override;
242 
243  Tick
244  readLastActivate() override
245  {
247  }
248  Tick
249  readLastSuspend() override
250  {
252  }
253 
254  void copyArchRegs(ThreadContext *tc) override;
255 
256  void
257  clearArchRegs() override
258  {
259  _pcState = 0;
260  std::fill(intRegs.begin(), intRegs.end(), 0);
261  std::fill(floatRegs.begin(), floatRegs.end(), 0);
262  for (auto &vec_reg: vecRegs)
263  vec_reg.zero();
264  for (auto &pred_reg: vecPredRegs)
265  pred_reg.reset();
266  std::fill(ccRegs.begin(), ccRegs.end(), 0);
267  isa->clear();
268  }
269 
270  //
271  // New accessors for new decoder.
272  //
273  RegVal
274  readIntReg(RegIndex reg_idx) const override
275  {
276  int flatIndex = isa->flattenIntIndex(reg_idx);
277  assert(flatIndex < intRegs.size());
278  uint64_t regVal = readIntRegFlat(flatIndex);
279  DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
280  reg_idx, flatIndex, regVal);
281  return regVal;
282  }
283 
284  RegVal
285  readFloatReg(RegIndex reg_idx) const override
286  {
287  int flatIndex = isa->flattenFloatIndex(reg_idx);
288  assert(flatIndex < floatRegs.size());
289  RegVal regVal = readFloatRegFlat(flatIndex);
290  DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
291  reg_idx, flatIndex, regVal);
292  return regVal;
293  }
294 
296  readVecReg(const RegId& reg) const override
297  {
298  int flatIndex = isa->flattenVecIndex(reg.index());
299  assert(flatIndex < vecRegs.size());
300  const TheISA::VecRegContainer& regVal = readVecRegFlat(flatIndex);
301  DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
302  reg.index(), flatIndex, regVal);
303  return regVal;
304  }
305 
307  getWritableVecReg(const RegId& reg) override
308  {
309  int flatIndex = isa->flattenVecIndex(reg.index());
310  assert(flatIndex < vecRegs.size());
311  TheISA::VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
312  DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
313  reg.index(), flatIndex, regVal);
314  return regVal;
315  }
316 
317  const TheISA::VecElem &
318  readVecElem(const RegId &reg) const override
319  {
320  int flatIndex = isa->flattenVecElemIndex(reg.index());
321  assert(flatIndex < vecRegs.size());
322  const TheISA::VecElem& regVal =
323  readVecElemFlat(flatIndex, reg.elemIndex());
324  DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
325  " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
326  return regVal;
327  }
328 
330  readVecPredReg(const RegId &reg) const override
331  {
332  int flatIndex = isa->flattenVecPredIndex(reg.index());
333  assert(flatIndex < vecPredRegs.size());
334  const TheISA::VecPredRegContainer& regVal =
335  readVecPredRegFlat(flatIndex);
336  DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
337  reg.index(), flatIndex, regVal);
338  return regVal;
339  }
340 
342  getWritableVecPredReg(const RegId &reg) override
343  {
344  int flatIndex = isa->flattenVecPredIndex(reg.index());
345  assert(flatIndex < vecPredRegs.size());
347  getWritableVecPredRegFlat(flatIndex);
348  DPRINTF(VecPredRegs,
349  "Reading predicate reg %d (%d) as %s for modify.\n",
350  reg.index(), flatIndex, regVal);
351  return regVal;
352  }
353 
354  RegVal
355  readCCReg(RegIndex reg_idx) const override
356  {
357  int flatIndex = isa->flattenCCIndex(reg_idx);
358  assert(0 <= flatIndex);
359  assert(flatIndex < ccRegs.size());
360  uint64_t regVal(readCCRegFlat(flatIndex));
361  DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
362  reg_idx, flatIndex, regVal);
363  return regVal;
364  }
365 
366  void
367  setIntReg(RegIndex reg_idx, RegVal val) override
368  {
369  int flatIndex = isa->flattenIntIndex(reg_idx);
370  assert(flatIndex < intRegs.size());
371  DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
372  reg_idx, flatIndex, val);
373  setIntRegFlat(flatIndex, val);
374  }
375 
376  void
377  setFloatReg(RegIndex reg_idx, RegVal val) override
378  {
379  int flatIndex = isa->flattenFloatIndex(reg_idx);
380  assert(flatIndex < floatRegs.size());
381  // XXX: Fix array out of bounds compiler error for gem5.fast
382  // when checkercpu enabled
383  if (flatIndex < floatRegs.size())
384  setFloatRegFlat(flatIndex, val);
385  DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
386  reg_idx, flatIndex, val);
387  }
388 
389  void
390  setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
391  {
392  int flatIndex = isa->flattenVecIndex(reg.index());
393  assert(flatIndex < vecRegs.size());
394  setVecRegFlat(flatIndex, val);
395  DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
396  reg.index(), flatIndex, val);
397  }
398 
399  void
400  setVecElem(const RegId &reg, const TheISA::VecElem &val) override
401  {
402  int flatIndex = isa->flattenVecElemIndex(reg.index());
403  assert(flatIndex < vecRegs.size());
404  setVecElemFlat(flatIndex, reg.elemIndex(), val);
405  DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
406  " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
407  }
408 
409  void
411  const TheISA::VecPredRegContainer &val) override
412  {
413  int flatIndex = isa->flattenVecPredIndex(reg.index());
414  assert(flatIndex < vecPredRegs.size());
415  setVecPredRegFlat(flatIndex, val);
416  DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
417  reg.index(), flatIndex, val);
418  }
419 
420  void
421  setCCReg(RegIndex reg_idx, RegVal val) override
422  {
423  int flatIndex = isa->flattenCCIndex(reg_idx);
424  assert(flatIndex < ccRegs.size());
425  DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
426  reg_idx, flatIndex, val);
427  setCCRegFlat(flatIndex, val);
428  }
429 
430  TheISA::PCState pcState() const override { return _pcState; }
431  void pcState(const TheISA::PCState &val) override { _pcState = val; }
432 
433  void
435  {
436  _pcState = val;
437  }
438 
439  Addr instAddr() const override { return _pcState.instAddr(); }
440  Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
441  MicroPC microPC() const override { return _pcState.microPC(); }
442  bool readPredicate() const { return predicate; }
443  void setPredicate(bool val) { predicate = val; }
444 
445  RegVal
446  readMiscRegNoEffect(RegIndex misc_reg) const override
447  {
448  return isa->readMiscRegNoEffect(misc_reg);
449  }
450 
451  RegVal
452  readMiscReg(RegIndex misc_reg) override
453  {
454  return isa->readMiscReg(misc_reg);
455  }
456 
457  void
458  setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
459  {
460  return isa->setMiscRegNoEffect(misc_reg, val);
461  }
462 
463  void
464  setMiscReg(RegIndex misc_reg, RegVal val) override
465  {
466  return isa->setMiscReg(misc_reg, val);
467  }
468 
469  RegId
470  flattenRegId(const RegId& regId) const override
471  {
472  return isa->flattenRegId(regId);
473  }
474 
475  unsigned readStCondFailures() const override { return storeCondFailures; }
476 
477  bool
479  {
480  return memAccPredicate;
481  }
482 
483  void
485  {
487  }
488 
489  void
490  setStCondFailures(unsigned sc_failures) override
491  {
492  storeCondFailures = sc_failures;
493  }
494 
495  RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
496  void
498  {
499  intRegs[idx] = val;
500  }
501 
502  RegVal
503  readFloatRegFlat(RegIndex idx) const override
504  {
505  return floatRegs[idx];
506  }
507  void
509  {
510  floatRegs[idx] = val;
511  }
512 
514  readVecRegFlat(RegIndex reg) const override
515  {
516  return vecRegs[reg];
517  }
518 
521  {
522  return vecRegs[reg];
523  }
524 
525  void
527  {
528  vecRegs[reg] = val;
529  }
530 
531  const TheISA::VecElem &
532  readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
533  {
534  return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
535  }
536 
537  void
539  const TheISA::VecElem &val) override
540  {
541  vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
542  }
543 
546  {
547  return vecPredRegs[reg];
548  }
549 
552  {
553  return vecPredRegs[reg];
554  }
555 
556  void
558  const TheISA::VecPredRegContainer &val) override
559  {
560  vecPredRegs[reg] = val;
561  }
562 
563  RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
564  void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
565 
566  // hardware transactional memory
567  void htmAbortTransaction(uint64_t htm_uid,
568  HtmFailureFaultCause cause) override;
569 
571  void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
572 };
573 
574 } // namespace gem5
575 
576 #endif // __CPU_SIMPLE_THREAD_HH__
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:452
gem5::SimpleThread::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:274
htm.hh
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::SimpleThread::readVecElem
const TheISA::VecElem & readVecElem(const RegId &reg) const override
Definition: simple_thread.hh:318
gem5::ThreadState::initMemProxies
void initMemProxies(ThreadContext *tc)
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
Definition: thread_state.cc:72
thread_state.hh
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:140
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:367
system.hh
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::SimpleThread::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: simple_thread.hh:296
gem5::SimpleThread::getProcessPtr
Process * getProcessPtr() override
Definition: simple_thread.hh:227
gem5::SimpleThread::setVecElemFlat
void setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex, const TheISA::VecElem &val) override
Definition: simple_thread.hh:538
serialize.hh
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::SimpleThread::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: simple_thread.hh:211
gem5::ThreadState
Struct for holding general thread state that is needed across CPU models.
Definition: thread_state.hh:47
gem5::SimpleThread::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: simple_thread.cc:165
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SimpleThread::readLastSuspend
Tick readLastSuspend() override
Definition: simple_thread.hh:249
gem5::SimpleThread::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: simple_thread.hh:564
gem5::SimpleThread::instAddr
Addr instAddr() const override
Definition: simple_thread.hh:439
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
tlb.hh
htm.hh
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::PCEventQueue::remove
bool remove(PCEvent *event) override
Definition: pc_event.cc:51
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:464
gem5::SimpleThread::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: simple_thread.hh:490
gem5::SimpleThread::getWritableVecRegFlat
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex reg) override
Definition: simple_thread.hh:520
gem5::SimpleThread::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: simple_thread.cc:124
gem5::SimpleThread::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: simple_thread.hh:209
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:104
gem5::PCEventQueue::schedule
bool schedule(PCEvent *event) override
Definition: pc_event.cc:71
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:390
gem5::SimpleThread::SimpleThread
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, BaseMMU *_mmu, BaseISA *_isa)
Definition: simple_thread.cc:88
std::vector< RegVal >
gem5::SimpleThread::remove
bool remove(PCEvent *e) override
Definition: simple_thread.hh:182
gem5::SimpleThread::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:355
gem5::SimpleThread::pcStateNoRecord
void pcStateNoRecord(const TheISA::PCState &val) override
Definition: simple_thread.hh:434
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::SimpleThread::clearArchRegs
void clearArchRegs() override
Definition: simple_thread.hh:257
gem5::SimpleThread::system
System * system
Definition: simple_thread.hh:132
gem5::SimpleThread::setContextId
void setContextId(ContextID id) override
Definition: simple_thread.hh:207
gem5::SimpleThread::_htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > _htmCheckpoint
Definition: simple_thread.hh:110
gem5::SimpleThread::activate
void activate() override
Set the status to Active.
Definition: simple_thread.cc:131
gem5::SimpleThread::setVecPredRegFlat
void setVecPredRegFlat(RegIndex reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:557
gem5::SimpleThread::getWritableVecPredRegFlat
TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex reg) override
Definition: simple_thread.hh:551
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:139
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::SimpleThread::getVirtProxy
PortProxy & getVirtProxy() override
Definition: simple_thread.hh:219
request.hh
gem5::SimpleThread::setThreadId
void setThreadId(int id) override
Definition: simple_thread.hh:205
gem5::SimpleThread::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: simple_thread.hh:563
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, const TheISA::VecElem &val) override
Definition: simple_thread.hh:400
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:410
gem5::ThreadState::getVirtProxy
PortProxy & getVirtProxy()
Definition: thread_state.cc:88
gem5::BaseMMU
Definition: mmu.hh:50
gem5::SimpleThread::microPC
MicroPC microPC() const override
Definition: simple_thread.hh:441
gem5::SimpleThread::cpuId
int cpuId() const override
Definition: simple_thread.hh:202
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:475
gem5::SimpleThread::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: simple_thread.hh:497
gem5::SimpleThread::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: simple_thread.cc:172
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:478
gem5::SimpleThread::decoder
TheISA::Decoder decoder
Definition: simple_thread.hh:136
gem5::SimpleThread::getSystemPtr
System * getSystemPtr() override
Definition: simple_thread.hh:217
gem5::System
Definition: system.hh:77
gem5::ThreadState::cpuId
int cpuId() const
Definition: thread_state.hh:59
gem5::SimpleThread::copyState
void copyState(ThreadContext *oldContext)
Definition: simple_thread.cc:105
gem5::SimpleThread::pcState
void pcState(const TheISA::PCState &val) override
Definition: simple_thread.hh:431
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::SimpleThread::isa
TheISA::ISA *const isa
Definition: simple_thread.hh:105
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:442
gem5::SimpleThread::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: simple_thread.cc:191
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:446
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Definition: eventq.hh:251
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count
Definition: misc.hh:709
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Deschedule the specified event.
Definition: eventq.hh:797
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uint32_t socketId() const override
Definition: simple_thread.hh:203
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Definition: thread_state.hh:152
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Definition: pcstate.hh:40
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Definition: pra_constants.hh:326
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Tick count type.
Definition: types.hh:58
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Definition: pc_event.hh:45
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CheckerCPU class.
Definition: cpu.hh:84
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Definition: simple_thread.hh:107
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:458
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Definition: simple_thread.hh:484
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Definition: simple_thread.hh:526
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Definition: pc_event.hh:74
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This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
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Definition: thread_state.hh:67
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Queue of events sorted in time order.
Definition: eventq.hh:622
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Definition: mmu.cc:58
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Definition: simple_thread.hh:204
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BaseISA * getIsaPtr() override
Definition: simple_thread.hh:213
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Definition: simple_thread.cc:94
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True if the memory access should be skipped for this instruction.
Definition: simple_thread.hh:116
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Definition: base.hh:107
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Definition: simple_thread.hh:545
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Definition: vec.hh:62
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Definition: simple_thread.hh:100
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Definition: simple_thread.hh:430
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Definition: simple_thread.hh:181
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Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
Definition: simple_thread.hh:222
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Definition: thread_state.hh:69
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Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
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Set the status to Halted.
Definition: simple_thread.cc:155
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Definition: simple_thread.hh:377
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Logical vector register elem index type.
Definition: types.hh:179
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Definition: simple_thread.cc:185
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Definition: simple_thread.hh:232
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While curTick() is useful for any object assigned to this event queue, if an object that is assigned ...
Definition: eventq.hh:857
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RegVal readFloatReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:285
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Definition: thread_state.hh:63
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Definition: simple_thread.hh:125
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Definition: simple_thread.hh:206
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Definition: thread_state.hh:65
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Definition: types.hh:92
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Definition: process.hh:67
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Tick readLastActivate() override
Definition: simple_thread.hh:244
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
gem5::SimpleThread::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: simple_thread.hh:342
gem5::SimpleThread::name
std::string name() const
Definition: simple_thread.hh:120
gem5::SimpleThread::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: simple_thread.hh:185
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std::vector< RegVal > ccRegs
Definition: simple_thread.hh:104
gem5::SimpleThread::nextInstAddr
Addr nextInstAddr() const override
Definition: simple_thread.hh:440
gem5::SimpleThread::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: simple_thread.hh:307
gem5::SimpleThread::setProcessPtr
void setProcessPtr(Process *p) override
Definition: simple_thread.hh:228
gem5::SimpleThread::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: simple_thread.hh:330
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Definition: thread_state.hh:87
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TheISA::Decoder * getDecoderPtr() override
Definition: simple_thread.hh:215
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void suspend() override
Set the status to Suspended.
Definition: simple_thread.cc:142
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ThreadContext::Status _status
Definition: thread_state.hh:122
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Definition: vec.hh:60
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gem5::SimpleThread::~SimpleThread
virtual ~SimpleThread()
Definition: simple_thread.hh:151
gem5::SimpleThread::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: simple_thread.hh:172
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::SimpleThread::vecPredRegs
std::vector< TheISA::VecPredRegContainer > vecPredRegs
Definition: simple_thread.hh:103
gem5::SimpleThread::readVecRegFlat
const TheISA::VecRegContainer & readVecRegFlat(RegIndex reg) const override
Definition: simple_thread.hh:514
gem5::SimpleThread::vecRegs
std::vector< TheISA::VecRegContainer > vecRegs
Definition: simple_thread.hh:102
gem5::SimpleThread::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const override
Definition: simple_thread.hh:503
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void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
Definition: eventq.hh:764
gem5::SimpleThread::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: simple_thread.hh:190
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std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SimpleThread::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: simple_thread.hh:195
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vaddr
Definition: pra_constants.hh:278
gem5::SimpleThread::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: simple_thread.hh:495
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uint32_t socketId() const
Definition: thread_state.hh:61
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SimpleThread::readVecElemFlat
const TheISA::VecElem & readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
Definition: simple_thread.hh:532
gem5::SimpleThread::Status
ThreadContext::Status Status
Definition: simple_thread.hh:97
gem5::SimpleThread::intRegs
std::vector< RegVal > intRegs
Definition: simple_thread.hh:101
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BaseCPU * baseCpu
Definition: thread_state.hh:125
gem5::SimpleThread::getCpuPtr
BaseCPU * getCpuPtr() override
Definition: simple_thread.hh:200
gem5::ThreadState::readLastActivate
Tick readLastActivate() const
Definition: thread_state.hh:71
gem5::SimpleThread::status
Status status() const override
Definition: simple_thread.hh:230
gem5::ThreadState::readLastSuspend
Tick readLastSuspend() const
Definition: thread_state.hh:73
thread_context.hh
gem5::SimpleThread::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: simple_thread.hh:508
gem5::SimpleThread::comInstEventQueue
EventQueue comInstEventQueue
An instruction-based event queue.
Definition: simple_thread.hh:130
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:443
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:421
byteswap.hh
gem5::SimpleThread::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: simple_thread.cc:116
gem5::SimpleThread::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: simple_thread.hh:470
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::SimpleThread::predicate
bool predicate
Did this instruction execute or is it predicated false.
Definition: simple_thread.hh:113
gem5::ThreadState::getProcessPtr
Process * getProcessPtr()
Definition: thread_state.hh:85
eventq.hh

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