gem5  v22.0.0.2
simple_thread.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2001-2006 The Regents of The University of Michigan
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
42 #ifndef __CPU_SIMPLE_THREAD_HH__
43 #define __CPU_SIMPLE_THREAD_HH__
44 
45 #include <algorithm>
46 #include <vector>
47 
48 #include "arch/generic/htm.hh"
49 #include "arch/generic/mmu.hh"
50 #include "arch/generic/pcstate.hh"
51 #include "arch/generic/tlb.hh"
52 #include "arch/isa.hh"
53 #include "arch/vecregs.hh"
54 #include "base/logging.hh"
55 #include "base/types.hh"
56 #include "config/the_isa.hh"
57 #include "cpu/regfile.hh"
58 #include "cpu/thread_context.hh"
59 #include "cpu/thread_state.hh"
60 #include "debug/CCRegs.hh"
61 #include "debug/FloatRegs.hh"
62 #include "debug/IntRegs.hh"
63 #include "debug/VecPredRegs.hh"
64 #include "debug/VecRegs.hh"
65 #include "mem/htm.hh"
66 #include "mem/page_table.hh"
67 #include "mem/request.hh"
68 #include "sim/byteswap.hh"
69 #include "sim/eventq.hh"
70 #include "sim/full_system.hh"
71 #include "sim/process.hh"
72 #include "sim/serialize.hh"
73 #include "sim/system.hh"
74 
75 namespace gem5
76 {
77 
78 class BaseCPU;
79 class CheckerCPU;
80 
95 class SimpleThread : public ThreadState, public ThreadContext
96 {
97  public:
99 
100  protected:
101  std::array<RegFile, CCRegClass + 1> regFiles;
102 
103  TheISA::ISA *const isa; // one "instance" of the current ISA.
104 
105  std::unique_ptr<PCStateBase> _pcState;
106 
107  // hardware transactional memory
108  std::unique_ptr<BaseHTMCheckpoint> _htmCheckpoint;
109 
111  bool predicate;
112 
115 
116  public:
117  std::string
118  name() const
119  {
120  return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
121  }
122 
129 
131 
133 
135 
136  // hardware transactional memory
139 
140  // constructor: initialize SimpleThread from given process structure
141  // FS
142  SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
143  BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder);
144  // SE
145  SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
146  Process *_process, BaseMMU *_mmu,
147  BaseISA *_isa, InstDecoder *_decoder);
148 
149  virtual ~SimpleThread() {}
150 
151  void takeOverFrom(ThreadContext *oldContext) override;
152 
153  void copyState(ThreadContext *oldContext);
154 
155  void serialize(CheckpointOut &cp) const override;
156  void unserialize(CheckpointIn &cp) override;
157 
158  /***************************************************************
159  * SimpleThread functions to provide CPU with access to various
160  * state.
161  **************************************************************/
162 
167  ThreadContext *getTC() { return this; }
168 
169  void
170  demapPage(Addr vaddr, uint64_t asn)
171  {
172  mmu->demapPage(vaddr, asn);
173  }
174 
175  /*******************************************
176  * ThreadContext interface functions.
177  ******************************************/
178 
179  bool schedule(PCEvent *e) override { return pcEventQueue.schedule(e); }
180  bool remove(PCEvent *e) override { return pcEventQueue.remove(e); }
181 
182  void
184  {
186  }
187  void
189  {
191  }
192  Tick
194  {
195  return comInstEventQueue.getCurTick();
196  }
197 
198  BaseCPU *getCpuPtr() override { return baseCpu; }
199 
200  int cpuId() const override { return ThreadState::cpuId(); }
201  uint32_t socketId() const override { return ThreadState::socketId(); }
202  int threadId() const override { return ThreadState::threadId(); }
203  void setThreadId(int id) override { ThreadState::setThreadId(id); }
204  ContextID contextId() const override { return ThreadState::contextId(); }
206 
207  BaseMMU *getMMUPtr() override { return mmu; }
208 
209  CheckerCPU *getCheckerCpuPtr() override { return NULL; }
210 
211  BaseISA *getIsaPtr() const override { return isa; }
212 
213  InstDecoder *getDecoderPtr() override { return decoder; }
214 
215  System *getSystemPtr() override { return system; }
216 
219 
220  Status status() const override { return _status; }
221 
222  void setStatus(Status newStatus) override { _status = newStatus; }
223 
225  void activate() override;
226 
228  void suspend() override;
229 
231  void halt() override;
232 
233  Tick
234  readLastActivate() override
235  {
237  }
238  Tick
239  readLastSuspend() override
240  {
242  }
243 
244  void copyArchRegs(ThreadContext *tc) override;
245 
246  void
247  clearArchRegs() override
248  {
249  set(_pcState, isa->newPCState());
250  for (auto &rf: regFiles)
251  rf.clear();
252  isa->clear();
253  }
254 
255  //
256  // New accessors for new decoder.
257  //
258  const PCStateBase &pcState() const override { return *_pcState; }
259  void pcState(const PCStateBase &val) override { set(_pcState, val); }
260 
261  void
262  pcStateNoRecord(const PCStateBase &val) override
263  {
264  set(_pcState, val);
265  }
266 
267  bool readPredicate() const { return predicate; }
268  void setPredicate(bool val) { predicate = val; }
269 
270  RegVal
271  readMiscRegNoEffect(RegIndex misc_reg) const override
272  {
273  return isa->readMiscRegNoEffect(misc_reg);
274  }
275 
276  RegVal
277  readMiscReg(RegIndex misc_reg) override
278  {
279  return isa->readMiscReg(misc_reg);
280  }
281 
282  void
283  setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
284  {
285  return isa->setMiscRegNoEffect(misc_reg, val);
286  }
287 
288  void
289  setMiscReg(RegIndex misc_reg, RegVal val) override
290  {
291  return isa->setMiscReg(misc_reg, val);
292  }
293 
294  RegId
295  flattenRegId(const RegId& regId) const override
296  {
297  return isa->flattenRegId(regId);
298  }
299 
300  unsigned readStCondFailures() const override { return storeCondFailures; }
301 
302  bool
304  {
305  return memAccPredicate;
306  }
307 
308  void
310  {
312  }
313 
314  void
315  setStCondFailures(unsigned sc_failures) override
316  {
317  storeCondFailures = sc_failures;
318  }
319 
320  RegVal
321  getReg(const RegId &arch_reg) const override
322  {
323  const RegId reg = flattenRegId(arch_reg);
324 
325  const RegIndex idx = reg.index();
326 
327  const auto &reg_file = regFiles[reg.classValue()];
328  const auto &reg_class = reg_file.regClass;
329 
330  RegVal val = reg_file.reg(idx);
331  DPRINTFV(reg_class.debug(), "Reading %s reg %s (%d) as %#x.\n",
332  reg.className(), reg_class.regName(arch_reg), idx, val);
333  return val;
334  }
335 
336  RegVal
337  getRegFlat(const RegId &reg) const override
338  {
339  const RegIndex idx = reg.index();
340 
341  const auto &reg_file = regFiles[reg.classValue()];
342  const auto &reg_class = reg_file.regClass;
343 
344  RegVal val = reg_file.reg(idx);
345  DPRINTFV(reg_class.debug(), "Reading %s reg %d as %#x.\n",
346  reg.className(), idx, val);
347  return val;
348  }
349 
350  void
351  getReg(const RegId &arch_reg, void *val) const override
352  {
353  const RegId reg = flattenRegId(arch_reg);
354 
355  const RegIndex idx = reg.index();
356 
357  const auto &reg_file = regFiles[reg.classValue()];
358  const auto &reg_class = reg_file.regClass;
359 
360  reg_file.get(idx, val);
361  DPRINTFV(reg_class.debug(), "Reading %s register %s (%d) as %s.\n",
362  reg.className(), reg_class.regName(arch_reg), idx,
363  reg_class.valString(val));
364  }
365 
366  void
367  getRegFlat(const RegId &reg, void *val) const override
368  {
369  const RegIndex idx = reg.index();
370 
371  const auto &reg_file = regFiles[reg.classValue()];
372  const auto &reg_class = reg_file.regClass;
373 
374  reg_file.get(idx, val);
375  DPRINTFV(reg_class.debug(), "Reading %s register %d as %s.\n",
376  reg.className(), idx, reg_class.valString(val));
377  }
378 
379  void *
380  getWritableReg(const RegId &arch_reg) override
381  {
382  const RegId reg = flattenRegId(arch_reg);
383  const RegIndex idx = reg.index();
384  auto &reg_file = regFiles[reg.classValue()];
385 
386  return reg_file.ptr(idx);
387  }
388 
389  void *
390  getWritableRegFlat(const RegId &reg) override
391  {
392  const RegIndex idx = reg.index();
393  auto &reg_file = regFiles[reg.classValue()];
394 
395  return reg_file.ptr(idx);
396  }
397 
398  void
399  setReg(const RegId &arch_reg, RegVal val) override
400  {
401  const RegId reg = flattenRegId(arch_reg);
402 
403  if (reg.is(InvalidRegClass))
404  return;
405 
406  const RegIndex idx = reg.index();
407 
408  auto &reg_file = regFiles[reg.classValue()];
409  const auto &reg_class = reg_file.regClass;
410 
411  DPRINTFV(reg_class.debug(), "Setting %s register %s (%d) to %#x.\n",
412  reg.className(), reg_class.regName(arch_reg), idx, val);
413  reg_file.reg(idx) = val;
414  }
415 
416  void
417  setRegFlat(const RegId &reg, RegVal val) override
418  {
419  if (reg.is(InvalidRegClass))
420  return;
421 
422  const RegIndex idx = reg.index();
423 
424  auto &reg_file = regFiles[reg.classValue()];
425  const auto &reg_class = reg_file.regClass;
426 
427  DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
428  reg.className(), idx, val);
429  reg_file.reg(idx) = val;
430  }
431 
432  void
433  setReg(const RegId &arch_reg, const void *val) override
434  {
435  const RegId reg = flattenRegId(arch_reg);
436 
437  const RegIndex idx = reg.index();
438 
439  auto &reg_file = regFiles[reg.classValue()];
440  const auto &reg_class = reg_file.regClass;
441 
442  DPRINTFV(reg_class.debug(), "Setting %s register %s (%d) to %s.\n",
443  reg.className(), reg_class.regName(arch_reg), idx,
444  reg_class.valString(val));
445  reg_file.set(idx, val);
446  }
447 
448  void
449  setRegFlat(const RegId &reg, const void *val) override
450  {
451  const RegIndex idx = reg.index();
452 
453  auto &reg_file = regFiles[reg.classValue()];
454  const auto &reg_class = reg_file.regClass;
455 
456  DPRINTFV(reg_class.debug(), "Setting %s register %d to %s.\n",
457  reg.className(), idx, reg_class.valString(val));
458  reg_file.set(idx, val);
459  }
460 
461  // hardware transactional memory
462  void htmAbortTransaction(uint64_t htm_uid,
463  HtmFailureFaultCause cause) override;
464 
466  void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
467 };
468 
469 } // namespace gem5
470 
471 #endif // __CPU_SIMPLE_THREAD_HH__
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:277
htm.hh
gem5::SimpleThread::getWritableReg
void * getWritableReg(const RegId &arch_reg) override
Definition: simple_thread.hh:380
thread_state.hh
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::SimpleThread::getReg
RegVal getReg(const RegId &arch_reg) const override
Definition: simple_thread.hh:321
gem5::SimpleThread::setRegFlat
void setRegFlat(const RegId &reg, RegVal val) override
Definition: simple_thread.hh:417
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:138
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
system.hh
gem5::SimpleThread::setReg
void setReg(const RegId &arch_reg, const void *val) override
Definition: simple_thread.hh:433
gem5::SimpleThread::getProcessPtr
Process * getProcessPtr() override
Definition: simple_thread.hh:217
serialize.hh
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::SimpleThread::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: simple_thread.hh:209
gem5::ThreadState
Struct for holding general thread state that is needed across CPU models.
Definition: thread_state.hh:47
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::SimpleThread::setRegFlat
void setRegFlat(const RegId &reg, const void *val) override
Definition: simple_thread.hh:449
gem5::SimpleThread::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: simple_thread.cc:167
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::set
Bitfield< 12, 11 > set
Definition: misc_types.hh:703
gem5::SimpleThread::readLastSuspend
Tick readLastSuspend() override
Definition: simple_thread.hh:239
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
tlb.hh
htm.hh
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::PCEventQueue::remove
bool remove(PCEvent *event) override
Definition: pc_event.cc:51
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:289
gem5::SimpleThread::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: simple_thread.hh:315
gem5::SimpleThread::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: simple_thread.cc:126
gem5::SimpleThread::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: simple_thread.hh:207
gem5::SimpleThread::getWritableRegFlat
void * getWritableRegFlat(const RegId &reg) override
Definition: simple_thread.hh:390
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::PCEventQueue::schedule
bool schedule(PCEvent *event) override
Definition: pc_event.cc:71
gem5::SimpleThread::remove
bool remove(PCEvent *e) override
Definition: simple_thread.hh:180
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::SimpleThread::clearArchRegs
void clearArchRegs() override
Definition: simple_thread.hh:247
gem5::SimpleThread::system
System * system
Definition: simple_thread.hh:130
gem5::SimpleThread::setContextId
void setContextId(ContextID id) override
Definition: simple_thread.hh:205
gem5::X86ISA::rf
Bitfield< 16 > rf
Definition: misc.hh:563
gem5::SimpleThread::_htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > _htmCheckpoint
Definition: simple_thread.hh:108
gem5::SimpleThread::activate
void activate() override
Set the status to Active.
Definition: simple_thread.cc:133
gem5::SimpleThread::setReg
void setReg(const RegId &arch_reg, RegVal val) override
Definition: simple_thread.hh:399
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:137
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:95
request.hh
gem5::SimpleThread::setThreadId
void setThreadId(int id) override
Definition: simple_thread.hh:203
gem5::BaseMMU
Definition: mmu.hh:53
gem5::SimpleThread::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: simple_thread.hh:213
gem5::SimpleThread::cpuId
int cpuId() const override
Definition: simple_thread.hh:200
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:300
gem5::SimpleThread::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: simple_thread.cc:174
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:132
gem5::SimpleThread::_pcState
std::unique_ptr< PCStateBase > _pcState
Definition: simple_thread.hh:105
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:303
gem5::SimpleThread::getSystemPtr
System * getSystemPtr() override
Definition: simple_thread.hh:215
gem5::System
Definition: system.hh:75
gem5::ThreadState::cpuId
int cpuId() const
Definition: thread_state.hh:59
gem5::SimpleThread::copyState
void copyState(ThreadContext *oldContext)
Definition: simple_thread.cc:107
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SimpleThread::isa
TheISA::ISA *const isa
Definition: simple_thread.hh:103
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:267
gem5::SimpleThread::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: simple_thread.cc:190
gem5::InstDecoder
Definition: decoder.hh:42
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:271
gem5::Event
Definition: eventq.hh:251
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::EventQueue::deschedule
void deschedule(Event *event)
Deschedule the specified event.
Definition: eventq.hh:797
gem5::SimpleThread::socketId
uint32_t socketId() const override
Definition: simple_thread.hh:201
gem5::ThreadState::storeCondFailures
unsigned storeCondFailures
Definition: thread_state.hh:138
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SimpleThread::getReg
void getReg(const RegId &arch_reg, void *val) const override
Definition: simple_thread.hh:351
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:283
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:309
process.hh
mmu.hh
gem5::PCEventQueue
Definition: pc_event.hh:74
gem5::ThreadState::setThreadId
void setThreadId(ThreadID id)
Definition: thread_state.hh:67
gem5::EventQueue
Queue of events sorted in time order.
Definition: eventq.hh:622
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:97
gem5::SimpleThread::threadId
int threadId() const override
Definition: simple_thread.hh:202
gem5::SimpleThread::takeOverFrom
void takeOverFrom(ThreadContext *oldContext) override
Definition: simple_thread.cc:96
gem5::SimpleThread::memAccPredicate
bool memAccPredicate
True if the memory access should be skipped for this instruction.
Definition: simple_thread.hh:114
gem5::SimpleThread::schedule
bool schedule(PCEvent *e) override
Definition: simple_thread.hh:179
gem5::SimpleThread::decoder
InstDecoder * decoder
Definition: simple_thread.hh:134
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:258
gem5::ThreadState::threadId
ThreadID threadId() const
Definition: thread_state.hh:69
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
regfile.hh
gem5::SimpleThread::halt
void halt() override
Set the status to Halted.
Definition: simple_thread.cc:157
gem5::SimpleThread::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: simple_thread.cc:184
gem5::SimpleThread::getIsaPtr
BaseISA * getIsaPtr() const override
Definition: simple_thread.hh:211
gem5::SimpleThread::setStatus
void setStatus(Status newStatus) override
Definition: simple_thread.hh:222
gem5::EventQueue::getCurTick
Tick getCurTick() const
While curTick() is useful for any object assigned to this event queue, if an object that is assigned ...
Definition: eventq.hh:857
gem5::ThreadState::contextId
ContextID contextId() const
Definition: thread_state.hh:63
full_system.hh
gem5::SimpleThread::pcEventQueue
PCEventQueue pcEventQueue
Definition: simple_thread.hh:123
gem5::SimpleThread::contextId
ContextID contextId() const override
Definition: simple_thread.hh:204
gem5::ThreadState::setContextId
void setContextId(ContextID id)
Definition: thread_state.hh:65
gem5::SimpleThread::regFiles
std::array< RegFile, CCRegClass+1 > regFiles
Definition: simple_thread.hh:101
gem5::SimpleThread::getRegFlat
RegVal getRegFlat(const RegId &reg) const override
Flat register interfaces.
Definition: simple_thread.hh:337
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:68
gem5::SimpleThread::readLastActivate
Tick readLastActivate() override
Definition: simple_thread.hh:234
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:167
gem5::SimpleThread::name
std::string name() const
Definition: simple_thread.hh:118
gem5::SimpleThread::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: simple_thread.hh:183
pcstate.hh
gem5::SimpleThread::setProcessPtr
void setProcessPtr(Process *p) override
Definition: simple_thread.hh:218
gem5::ThreadState::setProcessPtr
void setProcessPtr(Process *p)
Definition: thread_state.hh:77
gem5::SimpleThread::suspend
void suspend() override
Set the status to Suspended.
Definition: simple_thread.cc:144
gem5::ThreadState::_status
ThreadContext::Status _status
Definition: thread_state.hh:112
types.hh
gem5::SimpleThread::~SimpleThread
virtual ~SimpleThread()
Definition: simple_thread.hh:149
gem5::SimpleThread::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: simple_thread.hh:170
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
logging.hh
gem5::EventQueue::schedule
void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
Definition: eventq.hh:764
gem5::SimpleThread::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: simple_thread.hh:188
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SimpleThread::pcStateNoRecord
void pcStateNoRecord(const PCStateBase &val) override
Definition: simple_thread.hh:262
gem5::SimpleThread::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: simple_thread.hh:193
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ThreadState::socketId
uint32_t socketId() const
Definition: thread_state.hh:61
DPRINTFV
#define DPRINTFV(x,...)
Definition: trace.hh:207
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
page_table.hh
gem5::SimpleThread::pcState
void pcState(const PCStateBase &val) override
Definition: simple_thread.hh:259
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::SimpleThread::Status
ThreadContext::Status Status
Definition: simple_thread.hh:98
gem5::ThreadState::baseCpu
BaseCPU * baseCpu
Definition: thread_state.hh:115
gem5::SimpleThread::getCpuPtr
BaseCPU * getCpuPtr() override
Definition: simple_thread.hh:198
gem5::ThreadState::readLastActivate
Tick readLastActivate() const
Definition: thread_state.hh:71
gem5::SimpleThread::status
Status status() const override
Definition: simple_thread.hh:220
gem5::ThreadState::readLastSuspend
Tick readLastSuspend() const
Definition: thread_state.hh:73
gem5::SimpleThread::getRegFlat
void getRegFlat(const RegId &reg, void *val) const override
Definition: simple_thread.hh:367
gem5::SimpleThread::SimpleThread
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder)
Definition: simple_thread.cc:90
thread_context.hh
gem5::SimpleThread::comInstEventQueue
EventQueue comInstEventQueue
An instruction-based event queue.
Definition: simple_thread.hh:128
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:268
byteswap.hh
gem5::SimpleThread::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: simple_thread.cc:118
gem5::SimpleThread::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: simple_thread.hh:295
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::SimpleThread::predicate
bool predicate
Did this instruction execute or is it predicated false.
Definition: simple_thread.hh:111
gem5::ThreadState::getProcessPtr
Process * getProcessPtr()
Definition: thread_state.hh:75
eventq.hh

Generated on Thu Jul 28 2022 13:32:29 for gem5 by doxygen 1.8.17