gem5  v21.2.1.1
simple_thread.hh
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41 
42 #ifndef __CPU_SIMPLE_THREAD_HH__
43 #define __CPU_SIMPLE_THREAD_HH__
44 
45 #include <algorithm>
46 #include <vector>
47 
48 #include "arch/generic/htm.hh"
49 #include "arch/generic/mmu.hh"
50 #include "arch/generic/pcstate.hh"
51 #include "arch/generic/tlb.hh"
52 #include "arch/isa.hh"
53 #include "arch/vecregs.hh"
54 #include "base/types.hh"
55 #include "config/the_isa.hh"
56 #include "cpu/thread_context.hh"
57 #include "cpu/thread_state.hh"
58 #include "debug/CCRegs.hh"
59 #include "debug/FloatRegs.hh"
60 #include "debug/IntRegs.hh"
61 #include "debug/VecPredRegs.hh"
62 #include "debug/VecRegs.hh"
63 #include "mem/htm.hh"
64 #include "mem/page_table.hh"
65 #include "mem/request.hh"
66 #include "sim/byteswap.hh"
67 #include "sim/eventq.hh"
68 #include "sim/full_system.hh"
69 #include "sim/process.hh"
70 #include "sim/serialize.hh"
71 #include "sim/system.hh"
72 
73 namespace gem5
74 {
75 
76 class BaseCPU;
77 class CheckerCPU;
78 
93 class SimpleThread : public ThreadState, public ThreadContext
94 {
95  public:
97 
98  protected:
105  TheISA::ISA *const isa; // one "instance" of the current ISA.
106 
107  std::unique_ptr<PCStateBase> _pcState;
108 
109  // hardware transactional memory
110  std::unique_ptr<BaseHTMCheckpoint> _htmCheckpoint;
111 
113  bool predicate;
114 
117 
118  public:
119  std::string
120  name() const
121  {
122  return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
123  }
124 
131 
133 
135 
137 
138  // hardware transactional memory
141 
142  // constructor: initialize SimpleThread from given process structure
143  // FS
144  SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
145  BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder);
146  // SE
147  SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
148  Process *_process, BaseMMU *_mmu,
149  BaseISA *_isa, InstDecoder *_decoder);
150 
151  virtual ~SimpleThread() {}
152 
153  void takeOverFrom(ThreadContext *oldContext) override;
154 
155  void copyState(ThreadContext *oldContext);
156 
157  void serialize(CheckpointOut &cp) const override;
158  void unserialize(CheckpointIn &cp) override;
159 
160  /***************************************************************
161  * SimpleThread functions to provide CPU with access to various
162  * state.
163  **************************************************************/
164 
169  ThreadContext *getTC() { return this; }
170 
171  void
172  demapPage(Addr vaddr, uint64_t asn)
173  {
174  mmu->demapPage(vaddr, asn);
175  }
176 
177  /*******************************************
178  * ThreadContext interface functions.
179  ******************************************/
180 
181  bool schedule(PCEvent *e) override { return pcEventQueue.schedule(e); }
182  bool remove(PCEvent *e) override { return pcEventQueue.remove(e); }
183 
184  void
186  {
188  }
189  void
191  {
193  }
194  Tick
196  {
197  return comInstEventQueue.getCurTick();
198  }
199 
200  BaseCPU *getCpuPtr() override { return baseCpu; }
201 
202  int cpuId() const override { return ThreadState::cpuId(); }
203  uint32_t socketId() const override { return ThreadState::socketId(); }
204  int threadId() const override { return ThreadState::threadId(); }
205  void setThreadId(int id) override { ThreadState::setThreadId(id); }
206  ContextID contextId() const override { return ThreadState::contextId(); }
208 
209  BaseMMU *getMMUPtr() override { return mmu; }
210 
211  CheckerCPU *getCheckerCpuPtr() override { return NULL; }
212 
213  BaseISA *getIsaPtr() override { return isa; }
214 
215  InstDecoder *getDecoderPtr() override { return decoder; }
216 
217  System *getSystemPtr() override { return system; }
218 
221 
222  Status status() const override { return _status; }
223 
224  void setStatus(Status newStatus) override { _status = newStatus; }
225 
227  void activate() override;
228 
230  void suspend() override;
231 
233  void halt() override;
234 
235  Tick
236  readLastActivate() override
237  {
239  }
240  Tick
241  readLastSuspend() override
242  {
244  }
245 
246  void copyArchRegs(ThreadContext *tc) override;
247 
248  void
249  clearArchRegs() override
250  {
251  set(_pcState, isa->newPCState());
252  std::fill(intRegs.begin(), intRegs.end(), 0);
253  std::fill(floatRegs.begin(), floatRegs.end(), 0);
254  for (auto &vec_reg: vecRegs)
255  vec_reg.zero();
256  std::fill(vecElemRegs.begin(), vecElemRegs.end(), 0);
257  for (auto &pred_reg: vecPredRegs)
258  pred_reg.reset();
259  std::fill(ccRegs.begin(), ccRegs.end(), 0);
260  isa->clear();
261  }
262 
263  //
264  // New accessors for new decoder.
265  //
266  RegVal
267  readIntReg(RegIndex reg_idx) const override
268  {
269  int flatIndex = isa->flattenIntIndex(reg_idx);
270  assert(flatIndex < intRegs.size());
271  uint64_t regVal = readIntRegFlat(flatIndex);
272  DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
273  reg_idx, flatIndex, regVal);
274  return regVal;
275  }
276 
277  RegVal
278  readFloatReg(RegIndex reg_idx) const override
279  {
280  int flatIndex = isa->flattenFloatIndex(reg_idx);
281  assert(flatIndex < floatRegs.size());
282  RegVal regVal = readFloatRegFlat(flatIndex);
283  DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
284  reg_idx, flatIndex, regVal);
285  return regVal;
286  }
287 
289  readVecReg(const RegId& reg) const override
290  {
291  int flatIndex = isa->flattenVecIndex(reg.index());
292  assert(flatIndex < vecRegs.size());
293  const TheISA::VecRegContainer& regVal = readVecRegFlat(flatIndex);
294  DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
295  reg.index(), flatIndex, regVal);
296  return regVal;
297  }
298 
300  getWritableVecReg(const RegId& reg) override
301  {
302  int flatIndex = isa->flattenVecIndex(reg.index());
303  assert(flatIndex < vecRegs.size());
304  TheISA::VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
305  DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
306  reg.index(), flatIndex, regVal);
307  return regVal;
308  }
309 
310  RegVal
311  readVecElem(const RegId &reg) const override
312  {
313  int flatIndex = isa->flattenVecElemIndex(reg.index());
314  assert(flatIndex < vecRegs.size());
315  RegVal regVal = readVecElemFlat(flatIndex, reg.elemIndex());
316  DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
317  " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
318  return regVal;
319  }
320 
322  readVecPredReg(const RegId &reg) const override
323  {
324  int flatIndex = isa->flattenVecPredIndex(reg.index());
325  assert(flatIndex < vecPredRegs.size());
326  const TheISA::VecPredRegContainer& regVal =
327  readVecPredRegFlat(flatIndex);
328  DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
329  reg.index(), flatIndex, regVal);
330  return regVal;
331  }
332 
334  getWritableVecPredReg(const RegId &reg) override
335  {
336  int flatIndex = isa->flattenVecPredIndex(reg.index());
337  assert(flatIndex < vecPredRegs.size());
339  getWritableVecPredRegFlat(flatIndex);
340  DPRINTF(VecPredRegs,
341  "Reading predicate reg %d (%d) as %s for modify.\n",
342  reg.index(), flatIndex, regVal);
343  return regVal;
344  }
345 
346  RegVal
347  readCCReg(RegIndex reg_idx) const override
348  {
349  int flatIndex = isa->flattenCCIndex(reg_idx);
350  assert(0 <= flatIndex);
351  assert(flatIndex < ccRegs.size());
352  uint64_t regVal(readCCRegFlat(flatIndex));
353  DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
354  reg_idx, flatIndex, regVal);
355  return regVal;
356  }
357 
358  void
359  setIntReg(RegIndex reg_idx, RegVal val) override
360  {
361  int flatIndex = isa->flattenIntIndex(reg_idx);
362  assert(flatIndex < intRegs.size());
363  DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
364  reg_idx, flatIndex, val);
365  setIntRegFlat(flatIndex, val);
366  }
367 
368  void
369  setFloatReg(RegIndex reg_idx, RegVal val) override
370  {
371  int flatIndex = isa->flattenFloatIndex(reg_idx);
372  assert(flatIndex < floatRegs.size());
373  // XXX: Fix array out of bounds compiler error for gem5.fast
374  // when checkercpu enabled
375  if (flatIndex < floatRegs.size())
376  setFloatRegFlat(flatIndex, val);
377  DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
378  reg_idx, flatIndex, val);
379  }
380 
381  void
382  setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
383  {
384  int flatIndex = isa->flattenVecIndex(reg.index());
385  assert(flatIndex < vecRegs.size());
386  setVecRegFlat(flatIndex, val);
387  DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
388  reg.index(), flatIndex, val);
389  }
390 
391  void
392  setVecElem(const RegId &reg, RegVal val) override
393  {
394  int flatIndex = isa->flattenVecElemIndex(reg.index());
395  assert(flatIndex < vecRegs.size());
396  setVecElemFlat(flatIndex, reg.elemIndex(), val);
397  DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
398  " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
399  }
400 
401  void
403  const TheISA::VecPredRegContainer &val) override
404  {
405  int flatIndex = isa->flattenVecPredIndex(reg.index());
406  assert(flatIndex < vecPredRegs.size());
407  setVecPredRegFlat(flatIndex, val);
408  DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
409  reg.index(), flatIndex, val);
410  }
411 
412  void
413  setCCReg(RegIndex reg_idx, RegVal val) override
414  {
415  int flatIndex = isa->flattenCCIndex(reg_idx);
416  assert(flatIndex < ccRegs.size());
417  DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
418  reg_idx, flatIndex, val);
419  setCCRegFlat(flatIndex, val);
420  }
421 
422  const PCStateBase &pcState() const override { return *_pcState; }
423  void pcState(const PCStateBase &val) override { set(_pcState, val); }
424 
425  void
426  pcStateNoRecord(const PCStateBase &val) override
427  {
428  set(_pcState, val);
429  }
430 
431  bool readPredicate() const { return predicate; }
432  void setPredicate(bool val) { predicate = val; }
433 
434  RegVal
435  readMiscRegNoEffect(RegIndex misc_reg) const override
436  {
437  return isa->readMiscRegNoEffect(misc_reg);
438  }
439 
440  RegVal
441  readMiscReg(RegIndex misc_reg) override
442  {
443  return isa->readMiscReg(misc_reg);
444  }
445 
446  void
447  setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
448  {
449  return isa->setMiscRegNoEffect(misc_reg, val);
450  }
451 
452  void
453  setMiscReg(RegIndex misc_reg, RegVal val) override
454  {
455  return isa->setMiscReg(misc_reg, val);
456  }
457 
458  RegId
459  flattenRegId(const RegId& regId) const override
460  {
461  return isa->flattenRegId(regId);
462  }
463 
464  unsigned readStCondFailures() const override { return storeCondFailures; }
465 
466  bool
468  {
469  return memAccPredicate;
470  }
471 
472  void
474  {
476  }
477 
478  void
479  setStCondFailures(unsigned sc_failures) override
480  {
481  storeCondFailures = sc_failures;
482  }
483 
484  RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
485  void
487  {
488  intRegs[idx] = val;
489  }
490 
491  RegVal
492  readFloatRegFlat(RegIndex idx) const override
493  {
494  return floatRegs[idx];
495  }
496  void
498  {
499  floatRegs[idx] = val;
500  }
501 
503  readVecRegFlat(RegIndex reg) const override
504  {
505  return vecRegs[reg];
506  }
507 
510  {
511  return vecRegs[reg];
512  }
513 
514  void
516  {
517  vecRegs[reg] = val;
518  }
519 
520  RegVal
521  readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
522  {
523  return vecElemRegs[reg * TheISA::NumVecElemPerVecReg + elemIndex];
524  }
525 
526  void
528  RegVal val) override
529  {
531  }
532 
535  {
536  return vecPredRegs[reg];
537  }
538 
541  {
542  return vecPredRegs[reg];
543  }
544 
545  void
547  const TheISA::VecPredRegContainer &val) override
548  {
549  vecPredRegs[reg] = val;
550  }
551 
552  RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
553  void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
554 
555  // hardware transactional memory
556  void htmAbortTransaction(uint64_t htm_uid,
557  HtmFailureFaultCause cause) override;
558 
560  void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
561 };
562 
563 } // namespace gem5
564 
565 #endif // __CPU_SIMPLE_THREAD_HH__
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:441
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::SimpleThread::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:267
htm.hh
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
thread_state.hh
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:140
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:359
system.hh
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::SimpleThread::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: simple_thread.hh:289
gem5::SimpleThread::setVecElemFlat
void setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex, RegVal val) override
Definition: simple_thread.hh:527
gem5::SimpleThread::getProcessPtr
Process * getProcessPtr() override
Definition: simple_thread.hh:219
serialize.hh
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::SimpleThread::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: simple_thread.hh:211
gem5::ThreadState
Struct for holding general thread state that is needed across CPU models.
Definition: thread_state.hh:47
gem5::SimpleThread::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: simple_thread.cc:167
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SimpleThread::readLastSuspend
Tick readLastSuspend() override
Definition: simple_thread.hh:241
gem5::SimpleThread::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: simple_thread.hh:553
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
tlb.hh
htm.hh
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::PCEventQueue::remove
bool remove(PCEvent *event) override
Definition: pc_event.cc:51
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:453
gem5::SimpleThread::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: simple_thread.hh:479
gem5::SimpleThread::getWritableVecRegFlat
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex reg) override
Definition: simple_thread.hh:509
gem5::SimpleThread::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: simple_thread.cc:126
gem5::SimpleThread::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: simple_thread.hh:209
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::PCEventQueue::schedule
bool schedule(PCEvent *event) override
Definition: pc_event.cc:71
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:382
std::vector< RegVal >
gem5::SimpleThread::vecElemRegs
std::vector< RegVal > vecElemRegs
Definition: simple_thread.hh:102
gem5::SimpleThread::remove
bool remove(PCEvent *e) override
Definition: simple_thread.hh:182
gem5::SimpleThread::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:347
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::SimpleThread::clearArchRegs
void clearArchRegs() override
Definition: simple_thread.hh:249
gem5::SimpleThread::system
System * system
Definition: simple_thread.hh:132
gem5::SimpleThread::setContextId
void setContextId(ContextID id) override
Definition: simple_thread.hh:207
gem5::SimpleThread::_htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > _htmCheckpoint
Definition: simple_thread.hh:110
gem5::SimpleThread::activate
void activate() override
Set the status to Active.
Definition: simple_thread.cc:133
gem5::SimpleThread::setVecPredRegFlat
void setVecPredRegFlat(RegIndex reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:546
gem5::SimpleThread::getWritableVecPredRegFlat
TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex reg) override
Definition: simple_thread.hh:540
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:139
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
request.hh
gem5::SimpleThread::setThreadId
void setThreadId(int id) override
Definition: simple_thread.hh:205
gem5::SimpleThread::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: simple_thread.hh:552
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:402
gem5::BaseMMU
Definition: mmu.hh:53
gem5::SimpleThread::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: simple_thread.hh:215
gem5::SimpleThread::cpuId
int cpuId() const override
Definition: simple_thread.hh:202
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:464
gem5::SimpleThread::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: simple_thread.hh:486
gem5::SimpleThread::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: simple_thread.cc:174
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::SimpleThread::_pcState
std::unique_ptr< PCStateBase > _pcState
Definition: simple_thread.hh:107
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:467
gem5::SimpleThread::getSystemPtr
System * getSystemPtr() override
Definition: simple_thread.hh:217
gem5::System
Definition: system.hh:75
gem5::ThreadState::cpuId
int cpuId() const
Definition: thread_state.hh:59
gem5::SimpleThread::copyState
void copyState(ThreadContext *oldContext)
Definition: simple_thread.cc:107
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SimpleThread::isa
TheISA::ISA *const isa
Definition: simple_thread.hh:105
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:431
gem5::SimpleThread::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: simple_thread.cc:190
gem5::InstDecoder
Definition: decoder.hh:42
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:435
gem5::Event
Definition: eventq.hh:251
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::EventQueue::deschedule
void deschedule(Event *event)
Deschedule the specified event.
Definition: eventq.hh:797
gem5::SimpleThread::socketId
uint32_t socketId() const override
Definition: simple_thread.hh:203
gem5::ThreadState::storeCondFailures
unsigned storeCondFailures
Definition: thread_state.hh:138
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:447
gem5::SimpleThread::setMemAccPredicate
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Definition: simple_thread.hh:473
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Definition: simple_thread.hh:515
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Definition: pc_event.hh:74
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Definition: thread_state.hh:67
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Definition: eventq.hh:622
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Definition: mmu.cc:97
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Definition: simple_thread.hh:204
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Definition: simple_thread.hh:213
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Definition: simple_thread.cc:96
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True if the memory access should be skipped for this instruction.
Definition: simple_thread.hh:116
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Definition: simple_thread.hh:534
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Definition: vec.hh:62
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Definition: simple_thread.hh:99
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Definition: simple_thread.hh:181
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Definition: simple_thread.hh:136
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Definition: simple_thread.hh:422
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Definition: thread_state.hh:69
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Definition: simple_thread.hh:311
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Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
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Set the status to Halted.
Definition: simple_thread.cc:157
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Definition: simple_thread.hh:369
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Logical vector register elem index type.
Definition: types.hh:179
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Definition: simple_thread.cc:184
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Definition: simple_thread.hh:224
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While curTick() is useful for any object assigned to this event queue, if an object that is assigned ...
Definition: eventq.hh:857
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Definition: simple_thread.hh:278
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Definition: thread_state.hh:63
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Definition: simple_thread.hh:125
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Definition: simple_thread.hh:206
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Definition: thread_state.hh:65
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Definition: types.hh:92
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Definition: process.hh:68
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Definition: simple_thread.hh:236
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Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
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Definition: simple_thread.hh:334
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Definition: simple_thread.hh:120
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Definition: simple_thread.hh:185
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Definition: simple_thread.hh:104
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Definition: simple_thread.hh:300
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Definition: simple_thread.hh:220
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Definition: simple_thread.hh:322
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Definition: thread_state.hh:77
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Set the status to Suspended.
Definition: simple_thread.cc:144
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Definition: thread_state.hh:112
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Definition: simple_thread.hh:392
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virtual ~SimpleThread()
Definition: simple_thread.hh:151
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Definition: simple_thread.hh:172
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Globally unique thread context ID.
Definition: types.hh:246
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Definition: simple_thread.hh:103
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const TheISA::VecRegContainer & readVecRegFlat(RegIndex reg) const override
Definition: simple_thread.hh:503
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std::vector< TheISA::VecRegContainer > vecRegs
Definition: simple_thread.hh:101
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RegVal readFloatRegFlat(RegIndex idx) const override
Definition: simple_thread.hh:492
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Schedule the given event on this queue.
Definition: eventq.hh:764
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Definition: simple_thread.hh:190
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Definition: serialize.hh:66
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Definition: simple_thread.hh:426
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Definition: simple_thread.hh:195
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Definition: pra_constants.hh:278
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Definition: pcstate.hh:57
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RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: simple_thread.hh:484
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Definition: thread_state.hh:61
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Definition: isa.hh:57
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Definition: types.hh:176
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void pcState(const PCStateBase &val) override
Definition: simple_thread.hh:423
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::SimpleThread::Status
ThreadContext::Status Status
Definition: simple_thread.hh:96
gem5::SimpleThread::intRegs
std::vector< RegVal > intRegs
Definition: simple_thread.hh:100
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Definition: thread_state.hh:115
gem5::SimpleThread::getCpuPtr
BaseCPU * getCpuPtr() override
Definition: simple_thread.hh:200
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Tick readLastActivate() const
Definition: thread_state.hh:71
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Status status() const override
Definition: simple_thread.hh:222
gem5::ThreadState::readLastSuspend
Tick readLastSuspend() const
Definition: thread_state.hh:73
gem5::SimpleThread::SimpleThread
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder)
Definition: simple_thread.cc:90
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gem5::SimpleThread::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: simple_thread.hh:497
gem5::SimpleThread::comInstEventQueue
EventQueue comInstEventQueue
An instruction-based event queue.
Definition: simple_thread.hh:130
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:432
gem5::SimpleThread::readVecElemFlat
RegVal readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
Definition: simple_thread.hh:521
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:413
byteswap.hh
gem5::SimpleThread::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: simple_thread.cc:118
gem5::SimpleThread::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: simple_thread.hh:459
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Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::SimpleThread::predicate
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Did this instruction execute or is it predicated false.
Definition: simple_thread.hh:113
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Definition: thread_state.hh:75
eventq.hh

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