gem5  v22.0.0.1
exec_context.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2014, 2016-2018, 2020-2021 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2002-2005 The Regents of The University of Michigan
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
48 #ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
49 #define __CPU_MINOR_EXEC_CONTEXT_HH__
50 
51 #include "cpu/exec_context.hh"
52 #include "cpu/minor/execute.hh"
53 #include "cpu/minor/pipeline.hh"
54 #include "cpu/base.hh"
55 #include "cpu/simple_thread.hh"
56 #include "mem/request.hh"
57 #include "debug/MinorExecute.hh"
58 
59 namespace gem5
60 {
61 
63 namespace minor
64 {
65 
66 /* Forward declaration of Execute */
67 class Execute;
68 
74 {
75  public:
77 
80 
83 
86 
88  MinorCPU &cpu_,
89  SimpleThread &thread_, Execute &execute_,
90  MinorDynInstPtr inst_) :
91  cpu(cpu_),
92  thread(thread_),
93  execute(execute_),
94  inst(inst_)
95  {
96  DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", *inst->pc);
97  pcState(*inst->pc);
98  setPredicate(inst->readPredicate());
99  setMemAccPredicate(inst->readMemAccPredicate());
100  }
101 
103  {
104  inst->setPredicate(readPredicate());
105  inst->setMemAccPredicate(readMemAccPredicate());
106  }
107 
108  Fault
109  initiateMemRead(Addr addr, unsigned int size,
111  const std::vector<bool>& byte_enable) override
112  {
113  assert(byte_enable.size() == size);
114  return execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
115  size, addr, flags, nullptr, nullptr, byte_enable);
116  }
117 
118  Fault
120  {
121  panic("ExecContext::initiateMemMgmtCmd() not implemented "
122  " on MinorCPU\n");
123  return NoFault;
124  }
125 
126  Fault
127  writeMem(uint8_t *data, unsigned int size, Addr addr,
128  Request::Flags flags, uint64_t *res,
129  const std::vector<bool>& byte_enable)
130  override
131  {
132  assert(byte_enable.size() == size);
133  return execute.getLSQ().pushRequest(inst, false /* store */, data,
134  size, addr, flags, res, nullptr, byte_enable);
135  }
136 
137  Fault
139  AtomicOpFunctorPtr amo_op) override
140  {
141  // AMO requests are pushed through the store path
142  return execute.getLSQ().pushRequest(inst, false /* amo */, nullptr,
143  size, addr, flags, nullptr, std::move(amo_op),
144  std::vector<bool>(size, true));
145  }
146 
147  RegVal
148  getRegOperand(const StaticInst *si, int idx) override
149  {
150  const RegId &reg = si->srcRegIdx(idx);
151  if (reg.is(InvalidRegClass))
152  return 0;
153  return thread.getReg(reg);
154  }
155 
156  void
157  getRegOperand(const StaticInst *si, int idx, void *val) override
158  {
159  thread.getReg(si->srcRegIdx(idx), val);
160  }
161 
162  void *
163  getWritableRegOperand(const StaticInst *si, int idx) override
164  {
165  return thread.getWritableReg(si->destRegIdx(idx));
166  }
167 
168  void
169  setRegOperand(const StaticInst *si, int idx, RegVal val) override
170  {
171  const RegId &reg = si->destRegIdx(idx);
172  if (reg.is(InvalidRegClass))
173  return;
174  thread.setReg(si->destRegIdx(idx), val);
175  }
176 
177  void
178  setRegOperand(const StaticInst *si, int idx, const void *val) override
179  {
180  thread.setReg(si->destRegIdx(idx), val);
181  }
182 
183  bool
184  readPredicate() const override
185  {
186  return thread.readPredicate();
187  }
188 
189  void
190  setPredicate(bool val) override
191  {
193  }
194 
195  bool
196  readMemAccPredicate() const override
197  {
198  return thread.readMemAccPredicate();
199  }
200 
201  void
202  setMemAccPredicate(bool val) override
203  {
205  }
206 
207  // hardware transactional memory
208  uint64_t
209  getHtmTransactionUid() const override
210  {
211  panic("ExecContext::getHtmTransactionUid() not"
212  "implemented on MinorCPU\n");
213  return 0;
214  }
215 
216  uint64_t
217  newHtmTransactionUid() const override
218  {
219  panic("ExecContext::newHtmTransactionUid() not"
220  "implemented on MinorCPU\n");
221  return 0;
222  }
223 
224  bool
225  inHtmTransactionalState() const override
226  {
227  // ExecContext::inHtmTransactionalState() not
228  // implemented on MinorCPU
229  return false;
230  }
231 
232  uint64_t
233  getHtmTransactionalDepth() const override
234  {
235  panic("ExecContext::getHtmTransactionalDepth() not"
236  "implemented on MinorCPU\n");
237  return 0;
238  }
239 
240  const PCStateBase &
241  pcState() const override
242  {
243  return thread.pcState();
244  }
245 
246  void
247  pcState(const PCStateBase &val) override
248  {
249  thread.pcState(val);
250  }
251 
252  RegVal
253  readMiscRegNoEffect(int misc_reg) const
254  {
255  return thread.readMiscRegNoEffect(misc_reg);
256  }
257 
258  RegVal
259  readMiscReg(int misc_reg) override
260  {
261  return thread.readMiscReg(misc_reg);
262  }
263 
264  void
265  setMiscReg(int misc_reg, RegVal val) override
266  {
267  thread.setMiscReg(misc_reg, val);
268  }
269 
270  RegVal
271  readMiscRegOperand(const StaticInst *si, int idx) override
272  {
273  const RegId& reg = si->srcRegIdx(idx);
274  assert(reg.is(MiscRegClass));
275  return thread.readMiscReg(reg.index());
276  }
277 
278  void
279  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
280  {
281  const RegId& reg = si->destRegIdx(idx);
282  assert(reg.is(MiscRegClass));
283  return thread.setMiscReg(reg.index(), val);
284  }
285 
286  ThreadContext *tcBase() const override { return thread.getTC(); }
287 
288  /* @todo, should make stCondFailures persistent somewhere */
289  unsigned int readStCondFailures() const override { return 0; }
290  void setStCondFailures(unsigned int st_cond_failures) override {}
291 
293  /* ISA-specific (or at least currently ISA singleton) functions */
294 
295  /* X86: TLB twiddling */
296  void
297  demapPage(Addr vaddr, uint64_t asn) override
298  {
299  thread.getMMUPtr()->demapPage(vaddr, asn);
300  }
301 
302  BaseCPU *getCpuPtr() { return &cpu; }
303 
304  public:
305  // monitor/mwait funtions
306  void
307  armMonitor(Addr address) override
308  {
309  getCpuPtr()->armMonitor(inst->id.threadId, address);
310  }
311 
312  bool
313  mwait(PacketPtr pkt) override
314  {
315  return getCpuPtr()->mwait(inst->id.threadId, pkt);
316  }
317 
318  void
320  {
321  return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.mmu);
322  }
323 
324  AddressMonitor *
325  getAddrMonitor() override
326  {
327  return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId);
328  }
329 };
330 
331 } // namespace minor
332 } // namespace gem5
333 
334 #endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
gem5::minor::ExecContext::mwait
bool mwait(PacketPtr pkt) override
Definition: exec_context.hh:313
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:277
gem5::minor::ExecContext::getRegOperand
void getRegOperand(const StaticInst *si, int idx, void *val) override
Definition: exec_context.hh:157
gem5::minor::ExecContext::initiateMemMgmtCmd
Fault initiateMemMgmtCmd(Request::Flags flags) override
Initiate a memory management command with no valid address.
Definition: exec_context.hh:119
gem5::minor::ExecContext::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: exec_context.hh:225
gem5::SimpleThread::getWritableReg
void * getWritableReg(const RegId &arch_reg) override
Definition: simple_thread.hh:380
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::SimpleThread::getReg
RegVal getReg(const RegId &arch_reg) const override
Definition: simple_thread.hh:321
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::minor::ExecContext::getWritableRegOperand
void * getWritableRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:163
gem5::minor::ExecContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: exec_context.hh:253
gem5::minor::ExecContext::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Definition: exec_context.hh:259
gem5::minor::ExecContext::armMonitor
void armMonitor(Addr address) override
Definition: exec_context.hh:307
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::minor::ExecContext::readPredicate
bool readPredicate() const override
Definition: exec_context.hh:184
gem5::minor::ExecContext::setRegOperand
void setRegOperand(const StaticInst *si, int idx, const void *val) override
Definition: exec_context.hh:178
gem5::minor::ExecContext::thread
SimpleThread & thread
ThreadState object, provides all the architectural state.
Definition: exec_context.hh:79
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::minor::ExecContext::writeMem
Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
For atomic-mode contexts, perform an atomic memory write operation.
Definition: exec_context.hh:127
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:289
minor
gem5::SimpleThread::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: simple_thread.hh:207
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::minor::ExecContext::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Definition: exec_context.hh:138
gem5::minor::ExecContext::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: exec_context.hh:217
std::vector< bool >
gem5::minor::ExecContext::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: exec_context.hh:202
gem5::minor::ExecContext::ExecContext
ExecContext(MinorCPU &cpu_, SimpleThread &thread_, Execute &execute_, MinorDynInstPtr inst_)
Definition: exec_context.hh:87
gem5::SimpleThread::setReg
void setReg(const RegId &arch_reg, RegVal val) override
Definition: simple_thread.hh:399
gem5::minor::ExecContext::mwaitAtomic
void mwaitAtomic(ThreadContext *tc) override
Definition: exec_context.hh:319
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:95
request.hh
gem5::minor::ExecContext::contextId
ContextID contextId()
Definition: exec_context.hh:292
gem5::minor::ExecContext::getCpuPtr
BaseCPU * getCpuPtr()
Definition: exec_context.hh:302
execute.hh
gem5::minor::ExecContext::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Initiate a timing memory read operation.
Definition: exec_context.hh:109
gem5::RefCountingPtr< MinorDynInst >
gem5::minor::ExecContext::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:271
gem5::minor::Execute::getLSQ
LSQ & getLSQ()
To allow ExecContext to find the LSQ.
Definition: execute.hh:338
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:132
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:303
gem5::Flags< FlagsType >
gem5::minor::ExecContext::setStCondFailures
void setStCondFailures(unsigned int st_cond_failures) override
Sets the number of consecutive store conditional failures.
Definition: exec_context.hh:290
gem5::minor::ExecContext::cpu
MinorCPU & cpu
Definition: exec_context.hh:76
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::minor::ExecContext::pcState
void pcState(const PCStateBase &val) override
Definition: exec_context.hh:247
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:267
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:271
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::minor::ExecContext::pcState
const PCStateBase & pcState() const override
Definition: exec_context.hh:241
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:309
pipeline.hh
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:97
gem5::minor::ExecContext::~ExecContext
~ExecContext()
Definition: exec_context.hh:102
flags
uint8_t flags
Definition: helpers.cc:66
gem5::minor::ExecContext::inst
MinorDynInstPtr inst
Instruction for the benefit of memory operations and for PC.
Definition: exec_context.hh:85
gem5::minor::ExecContext::setRegOperand
void setRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:169
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:258
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:825
gem5::minor::ExecContext::setPredicate
void setPredicate(bool val) override
Definition: exec_context.hh:190
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::ExecContext::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: exec_context.hh:196
gem5::minor::ExecContext::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: exec_context.hh:289
gem5::SimpleThread::contextId
ContextID contextId() const override
Definition: simple_thread.hh:204
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:167
gem5::minor::ExecContext
ExecContext bears the exec_context interface for Minor.
Definition: exec_context.hh:73
gem5::minor::ExecContext::execute
Execute & execute
The execute stage so we can peek at its contents.
Definition: exec_context.hh:82
gem5::minor::ExecContext::getRegOperand
RegVal getRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:148
gem5::minor::ExecContext::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Definition: exec_context.hh:265
simple_thread.hh
gem5::minor::ExecContext::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: exec_context.hh:297
base.hh
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::minor::Execute
Execute stage.
Definition: execute.hh:68
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
exec_context.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::minor::ExecContext::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: exec_context.hh:233
gem5::minor::ExecContext::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: exec_context.hh:325
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::minor::LSQ::pushRequest
Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable=std::vector< bool >())
Single interface for readMem/writeMem/amoMem to issue requests into the LSQ.
Definition: lsq.cc:1584
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::minor::ExecContext::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:279
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:268
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::minor::ExecContext::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: exec_context.hh:209
gem5::minor::ExecContext::tcBase
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
Definition: exec_context.hh:286

Generated on Sat Jun 18 2022 08:12:20 for gem5 by doxygen 1.8.17