gem5  v21.1.0.2
exec_context.hh
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41 
48 #ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
49 #define __CPU_MINOR_EXEC_CONTEXT_HH__
50 
51 #include "cpu/exec_context.hh"
52 #include "cpu/minor/execute.hh"
53 #include "cpu/minor/pipeline.hh"
54 #include "cpu/base.hh"
55 #include "cpu/simple_thread.hh"
56 #include "mem/request.hh"
57 #include "debug/MinorExecute.hh"
58 
59 namespace gem5
60 {
61 
63 namespace minor
64 {
65 
66 /* Forward declaration of Execute */
67 class Execute;
68 
74 {
75  public:
77 
80 
83 
86 
88  MinorCPU &cpu_,
89  SimpleThread &thread_, Execute &execute_,
90  MinorDynInstPtr inst_, RegIndex zeroReg) :
91  cpu(cpu_),
92  thread(thread_),
93  execute(execute_),
94  inst(inst_)
95  {
96  DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
97  pcState(inst->pc);
98  setPredicate(inst->readPredicate());
99  setMemAccPredicate(inst->readMemAccPredicate());
100  thread.setIntReg(zeroReg, 0);
101  }
102 
104  {
105  inst->setPredicate(readPredicate());
106  inst->setMemAccPredicate(readMemAccPredicate());
107  }
108 
109  Fault
110  initiateMemRead(Addr addr, unsigned int size,
111  Request::Flags flags,
112  const std::vector<bool>& byte_enable) override
113  {
114  assert(byte_enable.size() == size);
115  return execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
116  size, addr, flags, nullptr, nullptr, byte_enable);
117  }
118 
119  Fault
121  {
122  panic("ExecContext::initiateHtmCmd() not implemented on MinorCPU\n");
123  return NoFault;
124  }
125 
126  Fault
127  writeMem(uint8_t *data, unsigned int size, Addr addr,
128  Request::Flags flags, uint64_t *res,
129  const std::vector<bool>& byte_enable)
130  override
131  {
132  assert(byte_enable.size() == size);
133  return execute.getLSQ().pushRequest(inst, false /* store */, data,
134  size, addr, flags, res, nullptr, byte_enable);
135  }
136 
137  Fault
138  initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
139  AtomicOpFunctorPtr amo_op) override
140  {
141  // AMO requests are pushed through the store path
142  return execute.getLSQ().pushRequest(inst, false /* amo */, nullptr,
143  size, addr, flags, nullptr, std::move(amo_op),
144  std::vector<bool>(size, true));
145  }
146 
147  RegVal
148  readIntRegOperand(const StaticInst *si, int idx) override
149  {
150  const RegId& reg = si->srcRegIdx(idx);
151  assert(reg.is(IntRegClass));
152  return thread.readIntReg(reg.index());
153  }
154 
155  RegVal
156  readFloatRegOperandBits(const StaticInst *si, int idx) override
157  {
158  const RegId& reg = si->srcRegIdx(idx);
159  assert(reg.is(FloatRegClass));
160  return thread.readFloatReg(reg.index());
161  }
162 
164  readVecRegOperand(const StaticInst *si, int idx) const override
165  {
166  const RegId& reg = si->srcRegIdx(idx);
167  assert(reg.is(VecRegClass));
168  return thread.readVecReg(reg);
169  }
170 
172  getWritableVecRegOperand(const StaticInst *si, int idx) override
173  {
174  const RegId& reg = si->destRegIdx(idx);
175  assert(reg.is(VecRegClass));
176  return thread.getWritableVecReg(reg);
177  }
178 
180  readVecElemOperand(const StaticInst *si, int idx) const override
181  {
182  const RegId& reg = si->srcRegIdx(idx);
183  assert(reg.is(VecElemClass));
184  return thread.readVecElem(reg);
185  }
186 
188  readVecPredRegOperand(const StaticInst *si, int idx) const override
189  {
190  const RegId& reg = si->srcRegIdx(idx);
191  assert(reg.is(VecPredRegClass));
192  return thread.readVecPredReg(reg);
193  }
194 
196  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
197  {
198  const RegId& reg = si->destRegIdx(idx);
199  assert(reg.is(VecPredRegClass));
201  }
202 
203  void
204  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
205  {
206  const RegId& reg = si->destRegIdx(idx);
207  assert(reg.is(IntRegClass));
208  thread.setIntReg(reg.index(), val);
209  }
210 
211  void
212  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
213  {
214  const RegId& reg = si->destRegIdx(idx);
215  assert(reg.is(FloatRegClass));
216  thread.setFloatReg(reg.index(), val);
217  }
218 
219  void
220  setVecRegOperand(const StaticInst *si, int idx,
221  const TheISA::VecRegContainer& val) override
222  {
223  const RegId& reg = si->destRegIdx(idx);
224  assert(reg.is(VecRegClass));
226  }
227 
228  void
230  const TheISA::VecPredRegContainer& val) override
231  {
232  const RegId& reg = si->destRegIdx(idx);
233  assert(reg.is(VecPredRegClass));
235  }
236 
237  void
238  setVecElemOperand(const StaticInst *si, int idx,
239  const TheISA::VecElem val) override
240  {
241  const RegId& reg = si->destRegIdx(idx);
242  assert(reg.is(VecElemClass));
244  }
245 
246  bool
247  readPredicate() const override
248  {
249  return thread.readPredicate();
250  }
251 
252  void
253  setPredicate(bool val) override
254  {
256  }
257 
258  bool
259  readMemAccPredicate() const override
260  {
261  return thread.readMemAccPredicate();
262  }
263 
264  void
265  setMemAccPredicate(bool val) override
266  {
268  }
269 
270  // hardware transactional memory
271  uint64_t
272  getHtmTransactionUid() const override
273  {
274  panic("ExecContext::getHtmTransactionUid() not"
275  "implemented on MinorCPU\n");
276  return 0;
277  }
278 
279  uint64_t
280  newHtmTransactionUid() const override
281  {
282  panic("ExecContext::newHtmTransactionUid() not"
283  "implemented on MinorCPU\n");
284  return 0;
285  }
286 
287  bool
288  inHtmTransactionalState() const override
289  {
290  // ExecContext::inHtmTransactionalState() not
291  // implemented on MinorCPU
292  return false;
293  }
294 
295  uint64_t
296  getHtmTransactionalDepth() const override
297  {
298  panic("ExecContext::getHtmTransactionalDepth() not"
299  "implemented on MinorCPU\n");
300  return 0;
301  }
302 
304  pcState() const override
305  {
306  return thread.pcState();
307  }
308 
309  void
310  pcState(const TheISA::PCState &val) override
311  {
312  thread.pcState(val);
313  }
314 
315  RegVal
316  readMiscRegNoEffect(int misc_reg) const
317  {
318  return thread.readMiscRegNoEffect(misc_reg);
319  }
320 
321  RegVal
322  readMiscReg(int misc_reg) override
323  {
324  return thread.readMiscReg(misc_reg);
325  }
326 
327  void
328  setMiscReg(int misc_reg, RegVal val) override
329  {
330  thread.setMiscReg(misc_reg, val);
331  }
332 
333  RegVal
334  readMiscRegOperand(const StaticInst *si, int idx) override
335  {
336  const RegId& reg = si->srcRegIdx(idx);
337  assert(reg.is(MiscRegClass));
338  return thread.readMiscReg(reg.index());
339  }
340 
341  void
342  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
343  {
344  const RegId& reg = si->destRegIdx(idx);
345  assert(reg.is(MiscRegClass));
346  return thread.setMiscReg(reg.index(), val);
347  }
348 
349  ThreadContext *tcBase() const override { return thread.getTC(); }
350 
351  /* @todo, should make stCondFailures persistent somewhere */
352  unsigned int readStCondFailures() const override { return 0; }
353  void setStCondFailures(unsigned int st_cond_failures) override {}
354 
356  /* ISA-specific (or at least currently ISA singleton) functions */
357 
358  /* X86: TLB twiddling */
359  void
360  demapPage(Addr vaddr, uint64_t asn) override
361  {
362  thread.getMMUPtr()->demapPage(vaddr, asn);
363  }
364 
365  RegVal
366  readCCRegOperand(const StaticInst *si, int idx) override
367  {
368  const RegId& reg = si->srcRegIdx(idx);
369  assert(reg.is(CCRegClass));
370  return thread.readCCReg(reg.index());
371  }
372 
373  void
374  setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
375  {
376  const RegId& reg = si->destRegIdx(idx);
377  assert(reg.is(CCRegClass));
378  thread.setCCReg(reg.index(), val);
379  }
380 
381  BaseCPU *getCpuPtr() { return &cpu; }
382 
383  public:
384  // monitor/mwait funtions
385  void
386  armMonitor(Addr address) override
387  {
388  getCpuPtr()->armMonitor(inst->id.threadId, address);
389  }
390 
391  bool
392  mwait(PacketPtr pkt) override
393  {
394  return getCpuPtr()->mwait(inst->id.threadId, pkt);
395  }
396 
397  void
399  {
400  return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.mmu);
401  }
402 
404  getAddrMonitor() override
405  {
406  return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId);
407  }
408 };
409 
410 } // namespace minor
411 } // namespace gem5
412 
413 #endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
gem5::minor::ExecContext::mwait
bool mwait(PacketPtr pkt) override
Definition: exec_context.hh:392
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:452
gem5::minor::ExecContext::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: exec_context.hh:288
gem5::SimpleThread::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:274
gem5::minor::ExecContext::readVecElemOperand
TheISA::VecElem readVecElemOperand(const StaticInst *si, int idx) const override
Vector Elem Interfaces.
Definition: exec_context.hh:180
gem5::minor::ExecContext::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: exec_context.hh:148
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::SimpleThread::readVecElem
const TheISA::VecElem & readVecElem(const RegId &reg) const override
Definition: simple_thread.hh:318
gem5::minor::ExecContext::getWritableVecRegOperand
TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Gets destination vector register operand for modification.
Definition: exec_context.hh:172
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::BaseCPU::armMonitor
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::minor::ExecContext::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
Sets a destination vector register operand to a value.
Definition: exec_context.hh:220
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::minor::ExecContext::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:366
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:367
gem5::BaseCPU::mwaitAtomic
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::SimpleThread::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: simple_thread.hh:296
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::minor::ExecContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: exec_context.hh:316
gem5::minor::ExecContext::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Definition: exec_context.hh:322
gem5::minor::ExecContext::armMonitor
void armMonitor(Addr address) override
Definition: exec_context.hh:386
gem5::minor::ExecContext::readPredicate
bool readPredicate() const override
Definition: exec_context.hh:247
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::minor::ExecContext::thread
SimpleThread & thread
ThreadState object, provides all the architectural state.
Definition: exec_context.hh:79
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::minor::ExecContext::writeMem
Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
For atomic-mode contexts, perform an atomic memory write operation.
Definition: exec_context.hh:127
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:464
minor
gem5::SimpleThread::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: simple_thread.hh:209
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::minor::ExecContext::getWritableVecPredRegOperand
TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: exec_context.hh:196
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::minor::ExecContext::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Definition: exec_context.hh:138
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:390
gem5::minor::ExecContext::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: exec_context.hh:280
std::vector< bool >
gem5::minor::ExecContext::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: exec_context.hh:265
gem5::SimpleThread::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:355
gem5::minor::ExecContext::readVecRegOperand
const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Vector Register Interfaces.
Definition: exec_context.hh:164
gem5::minor::ExecContext::mwaitAtomic
void mwaitAtomic(ThreadContext *tc) override
Definition: exec_context.hh:398
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
request.hh
gem5::minor::ExecContext::contextId
ContextID contextId()
Definition: exec_context.hh:355
gem5::minor::ExecContext::getCpuPtr
BaseCPU * getCpuPtr()
Definition: exec_context.hh:381
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, const TheISA::VecElem &val) override
Definition: simple_thread.hh:400
execute.hh
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:410
gem5::minor::ExecContext::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Initiate a timing memory read operation.
Definition: exec_context.hh:110
gem5::RefCountingPtr< MinorDynInst >
gem5::AddressMonitor
Definition: base.hh:73
gem5::minor::ExecContext::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:334
gem5::minor::Execute::getLSQ
LSQ & getLSQ()
To allow ExecContext to find the LSQ.
Definition: execute.hh:342
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:478
gem5::Flags< FlagsType >
gem5::minor::ExecContext::setStCondFailures
void setStCondFailures(unsigned int st_cond_failures) override
Sets the number of consecutive store conditional failures.
Definition: exec_context.hh:353
gem5::minor::ExecContext::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:374
gem5::minor::ExecContext::cpu
MinorCPU & cpu
Definition: exec_context.hh:76
gem5::minor::ExecContext::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets an integer register to a value.
Definition: exec_context.hh:204
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:442
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:446
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::minor::ExecContext::readVecPredRegOperand
const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: exec_context.hh:188
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:484
pipeline.hh
gem5::minor::ExecContext::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
Sets a destination predicate register operand to a value.
Definition: exec_context.hh:229
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:58
gem5::minor::ExecContext::~ExecContext
~ExecContext()
Definition: exec_context.hh:103
gem5::BaseCPU
Definition: base.hh:107
gem5::minor::ExecContext::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Sets the bits of a floating point register of single width to a binary value.
Definition: exec_context.hh:212
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::SimpleThread::pcState
TheISA::PCState pcState() const override
Definition: simple_thread.hh:430
gem5::minor::ExecContext::inst
MinorDynInstPtr inst
Instruction for the benefit of memory operations and for PC.
Definition: exec_context.hh:85
gem5::minor::ExecContext::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val) override
Sets a vector register to a value.
Definition: exec_context.hh:238
gem5::minor::ExecContext::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: exec_context.hh:120
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::BaseCPU::getCpuAddrMonitor
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:609
gem5::minor::ExecContext::setPredicate
void setPredicate(bool val) override
Definition: exec_context.hh:253
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::minor::ExecContext::ExecContext
ExecContext(MinorCPU &cpu_, SimpleThread &thread_, Execute &execute_, MinorDynInstPtr inst_, RegIndex zeroReg)
Definition: exec_context.hh:87
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::SimpleThread::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:377
gem5::minor::ExecContext::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: exec_context.hh:259
gem5::SimpleThread::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:285
gem5::minor::ExecContext::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: exec_context.hh:352
gem5::SimpleThread::contextId
ContextID contextId() const override
Definition: simple_thread.hh:206
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
gem5::minor::ExecContext
ExecContext bears the exec_context interface for Minor.
Definition: exec_context.hh:73
gem5::SimpleThread::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: simple_thread.hh:342
gem5::minor::ExecContext::execute
Execute & execute
The execute stage so we can peek at its contents.
Definition: exec_context.hh:82
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::SimpleThread::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: simple_thread.hh:307
gem5::minor::ExecContext::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Definition: exec_context.hh:328
simple_thread.hh
gem5::minor::ExecContext::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: exec_context.hh:360
gem5::SimpleThread::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: simple_thread.hh:330
base.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::minor::Execute
Execute stage.
Definition: execute.hh:68
gem5::minor::ExecContext::pcState
void pcState(const TheISA::PCState &val) override
Definition: exec_context.hh:310
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
exec_context.hh
gem5::minor::ExecContext::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: exec_context.hh:156
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::minor::ExecContext::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: exec_context.hh:296
gem5::minor::ExecContext::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: exec_context.hh:404
gem5::BaseCPU::mwait
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::minor::LSQ::pushRequest
Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable=std::vector< bool >())
Single interface for readMem/writeMem/amoMem to issue requests into the LSQ.
Definition: lsq.cc:1588
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::minor::ExecContext::pcState
TheISA::PCState pcState() const override
Definition: exec_context.hh:304
gem5::minor::ExecContext::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:342
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:443
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:421
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::minor::ExecContext::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: exec_context.hh:272
gem5::minor::ExecContext::tcBase
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
Definition: exec_context.hh:349

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