gem5 v24.0.0.0
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fetch_stage.cc
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1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
33
36
37namespace gem5
38{
39
40FetchStage::FetchStage(const ComputeUnitParams &p, ComputeUnit &cu)
41 : numVectorALUs(p.num_SIMDs), computeUnit(cu),
42 _name(cu.name() + ".FetchStage"), stats(&cu)
43{
44 for (int j = 0; j < numVectorALUs; ++j) {
45 FetchUnit newFetchUnit(p, cu);
46 _fetchUnit.push_back(newFetchUnit);
47 }
48}
49
51{
52 _fetchUnit.clear();
53}
54
55void
57{
58 for (int j = 0; j < numVectorALUs; ++j) {
59 _fetchUnit[j].bindWaveList(&computeUnit.wfList[j]);
60 _fetchUnit[j].init();
61 }
62}
63
64void
66{
67 for (int j = 0; j < numVectorALUs; ++j) {
68 _fetchUnit[j].exec();
69 }
70}
71
72void
74{
77
78 Wavefront *wavefront = sender_state->wavefront;
79
80 const unsigned num_instructions = pkt->req->getSize() /
81 sizeof(TheGpuISA::RawMachInst);
82
83 stats.instFetchInstReturned.sample(num_instructions);
84 uint32_t simdId = wavefront->simdId;
85 _fetchUnit[simdId].processFetchReturn(pkt);
86}
87
88void
90{
91 _fetchUnit[wavefront->simdId].fetch(pkt, wavefront);
92}
93
95 : statistics::Group(parent, "FetchStage"),
96 ADD_STAT(instFetchInstReturned, "For each instruction fetch request "
97 "received record how many instructions you got from it")
98{
100}
101
102} // namespace gem5
std::vector< std::vector< Wavefront * > > wfList
void fetch(PacketPtr pkt, Wavefront *wave)
FetchStage(const ComputeUnitParams &p, ComputeUnit &cu)
std::vector< FetchUnit > _fetchUnit
gem5::FetchStage::FetchStageStats stats
ComputeUnit & computeUnit
void processFetchReturn(PacketPtr pkt)
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
SenderState * senderState
This packet's sender state.
Definition packet.hh:545
RequestPtr req
A pointer to the original request.
Definition packet.hh:377
const int simdId
Definition wavefront.hh:101
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
Statistics container.
Definition group.hh:93
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition group.hh:75
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
T safe_cast(U &&ref_or_ptr)
Definition cast.hh:74
statistics::Distribution instFetchInstReturned
FetchStageStats(statistics::Group *parent)
const std::string & name()
Definition trace.cc:48

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