gem5  v21.1.0.2
hybrid_gen.cc
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37 
39 
40 #include <algorithm>
41 
42 #include "base/random.hh"
43 #include "base/trace.hh"
44 #include "debug/TrafficGen.hh"
45 #include "enums/AddrMap.hh"
46 
47 namespace gem5
48 {
49 
51  RequestorID requestor_id, Tick _duration,
52  Addr start_addr_dram, Addr end_addr_dram,
53  Addr blocksize_dram,
54  Addr start_addr_nvm, Addr end_addr_nvm,
55  Addr blocksize_nvm,
56  Addr cacheline_size,
57  Tick min_period, Tick max_period,
58  uint8_t read_percent, Addr data_limit,
59  unsigned int num_seq_pkts_dram, unsigned int page_size_dram,
60  unsigned int nbr_of_banks_dram,
61  unsigned int nbr_of_banks_util_dram,
62  unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm,
63  unsigned int nbr_of_banks_nvm,
64  unsigned int nbr_of_banks_util_nvm,
65  enums::AddrMap addr_mapping,
66  unsigned int nbr_of_ranks_dram,
67  unsigned int nbr_of_ranks_nvm,
68  uint8_t nvm_percent)
69  : BaseGen(obj, requestor_id, _duration),
70  startAddrDram(start_addr_dram),
71  endAddrDram(end_addr_dram),
72  blocksizeDram(blocksize_dram),
73  startAddrNvm(start_addr_nvm),
74  endAddrNvm(end_addr_nvm),
75  blocksizeNvm(blocksize_nvm),
76  cacheLineSize(cacheline_size),
77  minPeriod(min_period), maxPeriod(max_period),
78  readPercent(read_percent), dataLimit(data_limit),
79  numSeqPktsDram(num_seq_pkts_dram),
80  numSeqPktsNvm(num_seq_pkts_nvm),
81  countNumSeqPkts(0), addr(0),
82  pageSizeDram(page_size_dram),
83  pageBitsDram(floorLog2(pageSizeDram / blocksizeDram)),
84  bankBitsDram(floorLog2(nbr_of_banks_dram)),
85  blockBitsDram(floorLog2(blocksizeDram)),
86  nbrOfBanksDram(nbr_of_banks_dram),
87  nbrOfBanksUtilDram(nbr_of_banks_util_dram),
88  bufferSizeNvm(buffer_size_nvm),
89  pageBitsNvm(floorLog2(bufferSizeNvm / blocksizeNvm)),
90  bankBitsNvm(floorLog2(nbr_of_banks_nvm)),
91  blockBitsNvm(floorLog2(blocksizeNvm)),
92  nbrOfBanksNvm(nbr_of_banks_nvm),
93  nbrOfBanksUtilNvm(nbr_of_banks_util_nvm),
94  addrMapping(addr_mapping),
95  nbrOfRanksDram(nbr_of_ranks_dram),
96  rankBitsDram(floorLog2(nbrOfRanksDram)),
97  nbrOfRanksNvm(nbr_of_ranks_nvm),
98  rankBitsNvm(floorLog2(nbrOfRanksNvm)),
99  nvmPercent(nvm_percent),
100  isRead(true),
101  isNvm(false),
102  dataManipulated(0)
103 {
105  fatal("TrafficGen %s Dram block size (%d) is larger than "
106  "cache line size (%d)\n", name(),
108 
110  fatal("TrafficGen %s Nvm block size (%d) is larger than "
111  "cache line size (%d)\n", name(),
113 
114  if (readPercent > 100)
115  fatal("%s cannot have more than 100% reads", name());
116 
117  if (minPeriod > maxPeriod)
118  fatal("%s cannot have min_period > max_period", name());
119 
121  fatal("Attempting to use more Dram banks (%d) than "
122  "what is available (%d)\n",
124 
126  fatal("Attempting to use more Nvm banks (%d) than "
127  "what is available (%d)\n",
129 }
130 
131 void
133 {
134  // reset the counter to zero
135  dataManipulated = 0;
136 }
137 
138 PacketPtr
140 {
141  // if this is the first of the packets in series to be generated,
142  // start counting again
143  if (countNumSeqPkts == 0) {
144  isNvm = nvmPercent != 0 &&
145  (nvmPercent == 100 || random_mt.random(0, 100) < nvmPercent);
146 
147  // choose if we generate a read or a write here
148  isRead = readPercent != 0 &&
149  (readPercent == 100 || random_mt.random(0, 100) < readPercent);
150 
151  assert((readPercent == 0 && !isRead) ||
152  (readPercent == 100 && isRead) ||
153  readPercent != 100);
154 
155  if (isNvm) {
156  // Select the appropriate parameters for this interface
169  } else {
170  // Select the appropriate parameters for this interface
183  }
184 
186 
187  // pick a random bank
188  unsigned int new_bank =
189  random_mt.random<unsigned int>(0, nbrOfBanksUtil - 1);
190 
191  // pick a random rank
192  unsigned int new_rank =
193  random_mt.random<unsigned int>(0, nbrOfRanks - 1);
194 
195  // Generate the start address of the command series
196  // routine will update addr variable with bank, rank, and col
197  // bits updated for random traffic mode
198  genStartAddr(new_bank, new_rank);
199 
200 
201  } else {
202  // increment the column by one
203  if (addrMapping == enums::RoRaBaCoCh ||
204  addrMapping == enums::RoRaBaChCo)
205  // Simply increment addr by blocksize to increment
206  // the column by one
207  addr += blocksize;
208 
209  else if (addrMapping == enums::RoCoRaBaCh) {
210  // Explicity increment the column bits
211  unsigned int new_col = ((addr / blocksize /
213  (pageSize / blocksize)) + 1;
215  blockBits + bankBits + rankBits, new_col);
216  }
217  }
218 
219  DPRINTF(TrafficGen, "HybridGen::getNextPacket: %c to addr %x, "
220  "size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
222 
223  // create a new request packet
226 
227  // add the amount of data manipulated to the total
229 
230  // subtract the number of packets remained to be generated
231  --countNumSeqPkts;
232 
233  // return the generated packet
234  return pkt;
235 }
236 
237 void
238 HybridGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
239 {
240  // start by picking a random address in the range
242 
243  // round down to start address of a block, i.e. a DRAM burst
244  addr -= addr % blocksize;
245 
246  // insert the bank bits at the right spot, and align the
247  // address to achieve the required hit length, this involves
248  // finding the appropriate start address such that all
249  // sequential packets target successive columns in the same
250  // page
251 
252  // for example, if we have a stride size of 192B, which means
253  // for LPDDR3 where burstsize = 32B we have numSeqPkts = 6,
254  // the address generated previously can be such that these
255  // 192B cross the page boundary, hence it needs to be aligned
256  // so that they all belong to the same page for page hit
257  unsigned int burst_per_page = pageSize / blocksize;
258 
259  // pick a random column, but ensure that there is room for
260  // numSeqPkts sequential columns in the same page
261  unsigned int new_col =
262  random_mt.random<unsigned int>(0, burst_per_page - numSeqPkts);
263 
264  if (addrMapping == enums::RoRaBaCoCh ||
265  addrMapping == enums::RoRaBaChCo) {
266  // Block bits, then page bits, then bank bits, then rank bits
268  blockBits + pageBits, new_bank);
269  replaceBits(addr, blockBits + pageBits - 1, blockBits, new_col);
270  if (rankBits != 0) {
272  blockBits + pageBits + bankBits, new_rank);
273  }
274  } else if (addrMapping == enums::RoCoRaBaCh) {
275  // Block bits, then bank bits, then rank bits, then page bits
276  replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
278  blockBits + bankBits + rankBits, new_col);
279  if (rankBits != 0) {
281  blockBits + bankBits, new_rank);
282  }
283  }
284 }
285 
286 Tick
287 HybridGen::nextPacketTick(bool elastic, Tick delay) const
288 {
289  // Check to see if we have reached the data limit. If dataLimit is
290  // zero we do not have a data limit and therefore we will keep
291  // generating requests for the entire residency in this state.
293  {
294  DPRINTF(TrafficGen, "Data limit for RandomGen reached.\n");
295  // No more requests. Return MaxTick.
296  return MaxTick;
297  } else {
298  // return the time when the next request should take place
300 
301  // compensate for the delay experienced to not be elastic, by
302  // default the value we generate is from the time we are
303  // asked, so the elasticity happens automatically
304  if (!elastic) {
305  if (wait < delay)
306  wait = 0;
307  else
308  wait -= delay;
309  }
310 
311  return curTick() + wait;
312  }
313 }
314 
315 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::HybridGen::countNumSeqPkts
unsigned int countNumSeqPkts
Track number of sequential packets generated for a request
Definition: hybrid_gen.hh:168
gem5::HybridGen::rankBits
unsigned int rankBits
Number of rank bits in DRAM address.
Definition: hybrid_gen.hh:274
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::HybridGen::cacheLineSize
const Addr cacheLineSize
Cache line size in the simulated system.
Definition: hybrid_gen.hh:151
gem5::HybridGen::addrMapping
enums::AddrMap addrMapping
Address mapping to be used.
Definition: hybrid_gen.hh:210
gem5::HybridGen::blocksizeNvm
const Addr blocksizeNvm
Blocksize and address increment for DRAM.
Definition: hybrid_gen.hh:148
gem5::HybridGen::pageBitsNvm
const unsigned int pageBitsNvm
Number of buffer bits in NVM address.
Definition: hybrid_gen.hh:195
gem5::HybridGen::nvmPercent
const uint8_t nvmPercent
Percent of generated transactions that should go to NVM.
Definition: hybrid_gen.hh:225
gem5::BaseGen::name
std::string name() const
Get the name, useful for DPRINTFs.
Definition: base_gen.hh:107
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
random.hh
gem5::HybridGen::numSeqPkts
unsigned int numSeqPkts
Number of sequential DRAM packets to be generated per cpu request.
Definition: hybrid_gen.hh:241
gem5::MaxTick
const Tick MaxTick
Definition: types.hh:60
gem5::HybridGen::blocksize
Addr blocksize
Blocksize and address increment.
Definition: hybrid_gen.hh:250
gem5::HybridGen::isRead
bool isRead
Remember type of requests to be generated in series.
Definition: hybrid_gen.hh:228
gem5::HybridGen::pageSizeDram
const unsigned int pageSizeDram
Page size of DRAM.
Definition: hybrid_gen.hh:174
gem5::HybridGen::bankBitsNvm
const unsigned int bankBitsNvm
Number of bank bits in NVM address.
Definition: hybrid_gen.hh:198
gem5::HybridGen::maxPeriod
const Tick maxPeriod
Definition: hybrid_gen.hh:155
gem5::HybridGen::HybridGen
HybridGen(SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr_dram, Addr end_addr_dram, Addr blocksize_dram, Addr start_addr_nvm, Addr end_addr_nvm, Addr blocksize_nvm, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts_dram, unsigned int page_size_dram, unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram, unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm, unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm, enums::AddrMap addr_mapping, unsigned int nbr_of_ranks_dram, unsigned int nbr_of_ranks_nvm, uint8_t nvm_percent)
Create a hybrid DRAM + NVM address sequence generator.
Definition: hybrid_gen.cc:50
gem5::HybridGen::startAddrNvm
const Addr startAddrNvm
Start of DRAM address range.
Definition: hybrid_gen.hh:142
gem5::HybridGen::pageSize
unsigned int pageSize
Page size of DRAM.
Definition: hybrid_gen.hh:253
gem5::HybridGen::endAddr
Addr endAddr
End of address range.
Definition: hybrid_gen.hh:247
gem5::HybridGen::startAddrDram
const Addr startAddrDram
Start of DRAM address range.
Definition: hybrid_gen.hh:133
gem5::HybridGen::nbrOfBanksUtilDram
const unsigned int nbrOfBanksUtilDram
Number of banks to be utilized for a given configuration.
Definition: hybrid_gen.hh:189
gem5::BaseGen::getPacket
PacketPtr getPacket(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
Generate a new request and associated packet.
Definition: base_gen.cc:55
gem5::HybridGen::bankBits
unsigned int bankBits
Number of bank bits in DRAM address.
Definition: hybrid_gen.hh:259
gem5::HybridGen::rankBitsNvm
const unsigned int rankBitsNvm
Number of rank bits in DRAM address.
Definition: hybrid_gen.hh:222
gem5::HybridGen::dataManipulated
Addr dataManipulated
Counter to determine the amount of data manipulated.
Definition: hybrid_gen.hh:238
gem5::HybridGen::pageBitsDram
const unsigned int pageBitsDram
Number of page bits in DRAM address.
Definition: hybrid_gen.hh:177
gem5::HybridGen::dataLimit
const Addr dataLimit
Maximum amount of data to manipulate.
Definition: hybrid_gen.hh:161
gem5::HybridGen::nbrOfBanksNvm
const unsigned int nbrOfBanksNvm
Number of banks in NVM.
Definition: hybrid_gen.hh:204
hybrid_gen.hh
gem5::Random::random
std::enable_if_t< std::is_integral< T >::value, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:90
gem5::HybridGen::blockBitsDram
const unsigned int blockBitsDram
Number of block bits in DRAM address.
Definition: hybrid_gen.hh:183
gem5::HybridGen::nbrOfRanksDram
const unsigned int nbrOfRanksDram
Number of ranks to be utilized for a given configuration.
Definition: hybrid_gen.hh:213
gem5::HybridGen::blockBitsNvm
const unsigned int blockBitsNvm
Number of block bits in NVM address.
Definition: hybrid_gen.hh:201
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::HybridGen::bankBitsDram
const unsigned int bankBitsDram
Number of bank bits in DRAM address.
Definition: hybrid_gen.hh:180
gem5::HybridGen::nbrOfBanksDram
const unsigned int nbrOfBanksDram
Number of banks in DRAM.
Definition: hybrid_gen.hh:186
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::HybridGen::nextPacketTick
Tick nextPacketTick(bool elastic, Tick delay) const
Determine the tick when the next packet is available.
Definition: hybrid_gen.cc:287
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::HybridGen::blocksizeDram
const Addr blocksizeDram
Blocksize and address increment for DRAM.
Definition: hybrid_gen.hh:139
gem5::HybridGen::minPeriod
const Tick minPeriod
Request generation period.
Definition: hybrid_gen.hh:154
gem5::HybridGen::nbrOfBanksUtilNvm
const unsigned int nbrOfBanksUtilNvm
Number of banks to be utilized for a given configuration.
Definition: hybrid_gen.hh:207
gem5::BaseGen
Base class for all generators, with the shared functionality and virtual functions for entering,...
Definition: base_gen.hh:64
gem5::HybridGen::genStartAddr
void genStartAddr(unsigned int new_bank, unsigned int new_rank)
Insert bank, rank, and column bits into packed address to create address for 1st command in a series.
Definition: hybrid_gen.cc:238
gem5::HybridGen::getNextPacket
PacketPtr getNextPacket()
Get the next generated packet.
Definition: hybrid_gen.cc:139
gem5::HybridGen::nbrOfBanks
unsigned int nbrOfBanks
Number of banks in DRAM.
Definition: hybrid_gen.hh:265
gem5::HybridGen::numSeqPktsDram
const unsigned int numSeqPktsDram
Number of sequential packets to be generated per cpu request.
Definition: hybrid_gen.hh:164
sc_core::wait
void wait()
Definition: sc_module.cc:653
gem5::HybridGen::addr
Addr addr
Address of request.
Definition: hybrid_gen.hh:171
gem5::HybridGen::enter
void enter()
Enter this generator state.
Definition: hybrid_gen.cc:132
gem5::HybridGen::nbrOfBanksUtil
unsigned int nbrOfBanksUtil
Number of banks to be utilized for a given configuration.
Definition: hybrid_gen.hh:268
gem5::HybridGen::blockBits
unsigned int blockBits
Number of block bits in DRAM address.
Definition: hybrid_gen.hh:262
gem5::TrafficGen
The traffic generator is a module that generates stimuli for the memory system, based on a collection...
Definition: traffic_gen.hh:70
gem5::HybridGen::startAddr
Addr startAddr
Start of address range.
Definition: hybrid_gen.hh:244
gem5::floorLog2
static constexpr std::enable_if_t< std::is_integral< T >::value, int > floorLog2(T x)
Definition: intmath.hh:59
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::HybridGen::numSeqPktsNvm
const unsigned int numSeqPktsNvm
Definition: hybrid_gen.hh:165
gem5::HybridGen::readPercent
const uint8_t readPercent
Percent of generated transactions that should be reads.
Definition: hybrid_gen.hh:158
gem5::HybridGen::nbrOfRanks
unsigned int nbrOfRanks
Number of ranks to be utilized for a given configuration.
Definition: hybrid_gen.hh:271
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
trace.hh
gem5::HybridGen::pageBits
unsigned int pageBits
Number of page bits in DRAM address.
Definition: hybrid_gen.hh:256
gem5::HybridGen::nbrOfRanksNvm
const unsigned int nbrOfRanksNvm
Number of ranks to be utilized for a given configuration.
Definition: hybrid_gen.hh:219
gem5::HybridGen::isNvm
bool isNvm
Remember the interface to be generated in series.
Definition: hybrid_gen.hh:231
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::random_mt
Random random_mt
Definition: random.cc:99
gem5::HybridGen::rankBitsDram
const unsigned int rankBitsDram
Number of rank bits in DRAM address.
Definition: hybrid_gen.hh:216
gem5::HybridGen::endAddrDram
const Addr endAddrDram
End of DRAM address range.
Definition: hybrid_gen.hh:136
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::HybridGen::endAddrNvm
const Addr endAddrNvm
End of DRAM address range.
Definition: hybrid_gen.hh:145
gem5::HybridGen::bufferSizeNvm
const unsigned int bufferSizeNvm
Buffer size of NVM.
Definition: hybrid_gen.hh:192

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