gem5  v21.1.0.2
lsq_unit.hh
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41 
42 #ifndef __CPU_O3_LSQ_UNIT_HH__
43 #define __CPU_O3_LSQ_UNIT_HH__
44 
45 #include <algorithm>
46 #include <cstring>
47 #include <map>
48 #include <memory>
49 #include <queue>
50 
52 #include "arch/generic/vec_reg.hh"
53 #include "arch/locked_mem.hh"
54 #include "base/circular_queue.hh"
55 #include "config/the_isa.hh"
56 #include "cpu/base.hh"
57 #include "cpu/inst_seq.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/o3/cpu.hh"
60 #include "cpu/o3/dyn_inst_ptr.hh"
61 #include "cpu/o3/lsq.hh"
62 #include "cpu/timebuf.hh"
63 #include "debug/HtmCpu.hh"
64 #include "debug/LSQUnit.hh"
65 #include "mem/packet.hh"
66 #include "mem/port.hh"
67 
68 namespace gem5
69 {
70 
71 struct O3CPUParams;
72 
73 namespace o3
74 {
75 
76 class IEW;
77 
90 class LSQUnit
91 {
92  public:
93  static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
94 
97  private:
98  class LSQEntry
99  {
100  private:
104  LSQRequest* req = nullptr;
106  uint32_t _size = 0;
108  bool _valid = false;
109 
110  public:
112  {
113  if (req != nullptr) {
114  req->freeLSQEntry();
115  req = nullptr;
116  }
117  }
118 
119  void
121  {
122  inst = nullptr;
123  if (req != nullptr) {
124  req->freeLSQEntry();
125  }
126  req = nullptr;
127  _valid = false;
128  _size = 0;
129  }
130 
131  void
132  set(const DynInstPtr& new_inst)
133  {
134  assert(!_valid);
135  inst = new_inst;
136  _valid = true;
137  _size = 0;
138  }
139 
140  LSQRequest* request() { return req; }
141  void setRequest(LSQRequest* r) { req = r; }
142  bool hasRequest() { return req != nullptr; }
145  bool valid() const { return _valid; }
146  uint32_t& size() { return _size; }
147  const uint32_t& size() const { return _size; }
148  const DynInstPtr& instruction() const { return inst; }
150  };
151 
152  class SQEntry : public LSQEntry
153  {
154  private:
158  bool _canWB = false;
160  bool _committed = false;
162  bool _completed = false;
167  bool _isAllZeros = false;
168 
169  public:
170  static constexpr size_t DataSize = sizeof(_data);
173  {
174  std::memset(_data, 0, DataSize);
175  }
176 
177  void set(const DynInstPtr& inst) { LSQEntry::set(inst); }
178 
179  void
181  {
182  LSQEntry::clear();
183  _canWB = _completed = _committed = _isAllZeros = false;
184  }
185 
188  bool& canWB() { return _canWB; }
189  const bool& canWB() const { return _canWB; }
190  bool& completed() { return _completed; }
191  const bool& completed() const { return _completed; }
192  bool& committed() { return _committed; }
193  const bool& committed() const { return _committed; }
194  bool& isAllZeros() { return _isAllZeros; }
195  const bool& isAllZeros() const { return _isAllZeros; }
196  char* data() { return _data; }
197  const char* data() const { return _data; }
199  };
200  using LQEntry = LSQEntry;
201 
203  enum class AddrRangeCoverage
204  {
205  PartialAddrRangeCoverage, /* Two ranges partly overlap */
206  FullAddrRangeCoverage, /* One range fully covers another */
207  NoAddrRangeCoverage /* Two ranges are disjoint */
208  };
209 
210  public:
213 
214  public:
216  LSQUnit(uint32_t lqEntries, uint32_t sqEntries);
217 
222  LSQUnit(const LSQUnit &l): stats(nullptr)
223  {
224  panic("LSQUnit is not copy-able");
225  }
226 
228  void init(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params,
229  LSQ *lsq_ptr, unsigned id);
230 
232  std::string name() const;
233 
235  void setDcachePort(RequestPort *dcache_port);
236 
238  void drainSanityCheck() const;
239 
241  void takeOverFrom();
242 
244  void insert(const DynInstPtr &inst);
246  void insertLoad(const DynInstPtr &load_inst);
248  void insertStore(const DynInstPtr &store_inst);
249 
256  Fault checkViolations(typename LoadQueue::iterator& loadIt,
257  const DynInstPtr& inst);
258 
263  void checkSnoop(PacketPtr pkt);
264 
266  Fault executeLoad(const DynInstPtr &inst);
267 
268  Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
270  Fault executeStore(const DynInstPtr &inst);
271 
273  void commitLoad();
275  void commitLoads(InstSeqNum &youngest_inst);
276 
278  void commitStores(InstSeqNum &youngest_inst);
279 
281  void writebackStores();
282 
285  void completeDataAccess(PacketPtr pkt);
286 
288  void squash(const InstSeqNum &squashed_num);
289 
293  bool violation() { return memDepViolator; }
294 
297 
299  unsigned numFreeLoadEntries();
300 
302  unsigned numFreeStoreEntries();
303 
305  int numLoads() { return loads; }
306 
308  int numStores() { return stores; }
309 
310  // hardware transactional memory
311  int numHtmStarts() const { return htmStarts; }
312  int numHtmStops() const { return htmStops; }
314  uint64_t getLatestHtmUid() const;
315  void
316  setLastRetiredHtmUid(uint64_t htm_uid)
317  {
318  assert(htm_uid >= lastRetiredHtmUid);
319  lastRetiredHtmUid = htm_uid;
320  }
321 
323  bool isFull() { return lqFull() || sqFull(); }
324 
326  bool isEmpty() const { return lqEmpty() && sqEmpty(); }
327 
329  bool lqFull() { return loadQueue.full(); }
330 
332  bool sqFull() { return storeQueue.full(); }
333 
335  bool lqEmpty() const { return loads == 0; }
336 
338  bool sqEmpty() const { return stores == 0; }
339 
341  unsigned getCount() { return loads + stores; }
342 
344  bool hasStoresToWB() { return storesToWB; }
345 
347  int numStoresToWB() { return storesToWB; }
348 
350  bool
352  {
353  return storeWBIt.dereferenceable() &&
354  storeWBIt->valid() &&
355  storeWBIt->canWB() &&
356  !storeWBIt->completed() &&
358  }
359 
361  void recvRetry();
362 
363  unsigned int cacheLineSize();
364  private:
366  void resetState();
367 
369  void writeback(const DynInstPtr &inst, PacketPtr pkt);
370 
372  void writebackBlockedStore();
373 
375  void completeStore(typename StoreQueue::iterator store_idx);
376 
378  void storePostSend();
379 
380  public:
385  bool trySendPacket(bool isLoad, PacketPtr data_pkt);
386 
387 
389  void dumpInsts() const;
390 
392  void schedule(Event& ev, Tick when);
393 
394  BaseMMU *getMMUPtr();
395 
396  private:
399 
402 
405 
408 
411  {
412  using LSQSenderState::alive;
413  public:
414  LQSenderState(typename LoadQueue::iterator idx_)
415  : LSQSenderState(idx_->request(), true), idx(idx_) { }
416 
418  typename LoadQueue::iterator idx;
419  //virtual LSQRequest* request() { return idx->request(); }
420  virtual void
422  {
423  //if (alive())
424  // idx->request()->senderState(nullptr);
425  }
426  };
427 
430  {
431  using LSQSenderState::alive;
432  public:
433  SQSenderState(typename StoreQueue::iterator idx_)
434  : LSQSenderState(idx_->request(), false), idx(idx_) { }
436  typename StoreQueue::iterator idx;
437  //virtual LSQRequest* request() { return idx->request(); }
438  virtual void
440  {
441  //if (alive())
442  // idx->request()->senderState(nullptr);
443  }
444  };
445 
447  class WritebackEvent : public Event
448  {
449  public:
451  WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt,
452  LSQUnit *lsq_ptr);
453 
455  void process();
456 
458  const char *description() const;
459 
460  private:
463 
466 
469  };
470 
471  public:
478  bool recvTimingResp(PacketPtr pkt);
479 
480  private:
483  public:
486 
489 
490  private:
494  unsigned depCheckShift;
495 
498 
500  int loads;
502  int stores;
505 
506  // hardware transactional memory
507  // nesting depth
509  int htmStops;
510  // sanity checks and debugging
512 
516  typename StoreQueue::iterator storeWBIt;
517 
520 
523 
525  bool stalled;
532 
535 
538 
541 
544 
546  bool needsTSO;
547 
548  protected:
549  // Will also need how many read/write ports the Dcache has. Or keep track
550  // of that in stage that is one level up, and only call executeLoad/Store
551  // the appropriate number of times.
553  {
555 
558 
561 
565 
568 
571 
574 
577 
581  } stats;
582 
583  public:
585  Fault read(LSQRequest *req, int load_idx);
586 
588  Fault write(LSQRequest *req, uint8_t *data, int store_idx);
589 
591  int getLoadHead() { return loadQueue.head(); }
592 
595 
597  int getStoreHead() { return storeQueue.head(); }
600 
602  bool isStalled() { return stalled; }
603  public:
608 };
609 
610 } // namespace o3
611 } // namespace gem5
612 
613 #endif // __CPU_O3_LSQ_UNIT_HH__
gem5::o3::LSQUnit::sqEmpty
bool sqEmpty() const
Returns if the SQ is empty.
Definition: lsq_unit.hh:338
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::o3::LSQUnit::SQEntry::isAllZeros
bool & isAllZeros()
Definition: lsq_unit.hh:194
gem5::o3::LSQUnit::storePostSend
void storePostSend()
Handles completing the send of a store to memory.
Definition: lsq_unit.cc:1062
gem5::o3::LSQUnit::LSQUnitStats::squashedLoads
statistics::Scalar squashedLoads
Total number of squashed loads.
Definition: lsq_unit.hh:560
gem5::o3::LSQUnit::WritebackEvent::process
void process()
Processes the writeback event.
Definition: lsq_unit.cc:76
gem5::o3::LSQUnit::LQSenderState::complete
virtual void complete()
Definition: lsq_unit.hh:421
gem5::o3::LSQUnit::lastRetiredHtmUid
uint64_t lastRetiredHtmUid
Definition: lsq_unit.hh:511
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:231
gem5::o3::LSQUnit::SQEntry::SQEntry
SQEntry()
Constructs an empty store queue entry.
Definition: lsq_unit.hh:172
gem5::o3::LSQUnit::violation
bool violation()
Returns if there is a memory ordering violation.
Definition: lsq_unit.hh:293
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::LSQUnit::stallingStoreIsn
InstSeqNum stallingStoreIsn
The store that causes the stall due to partial store to load forwarding.
Definition: lsq_unit.hh:529
gem5::o3::LSQUnit::insertStore
void insertStore(const DynInstPtr &store_inst)
Inserts a store instruction.
Definition: lsq_unit.cc:392
gem5::o3::LSQUnit::storeInFlight
bool storeInFlight
Whether or not a store is in flight.
Definition: lsq_unit.hh:540
gem5::o3::LSQUnit::LSQEntry::request
LSQRequest * request()
Definition: lsq_unit.hh:140
gem5::o3::LSQUnit::WritebackEvent::description
const char * description() const
Returns the description of this event.
Definition: lsq_unit.cc:88
gem5::o3::LSQUnit::isStalled
bool isStalled()
Returns whether or not the LSQ unit is stalled.
Definition: lsq_unit.hh:602
gem5::o3::LSQUnit::checkLoads
bool checkLoads
Should loads be checked for dependency issues.
Definition: lsq_unit.hh:497
gem5::o3::LSQUnit::LSQEntry::inst
DynInstPtr inst
The instruction.
Definition: lsq_unit.hh:102
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2081
gem5::o3::LSQUnit::LSQUnitStats::memOrderViolation
statistics::Scalar memOrderViolation
Tota number of memory ordering violations.
Definition: lsq_unit.hh:567
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::o3::LSQUnit::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Handles writing back and completing the load or store that has returned from memory.
Definition: lsq_unit.cc:94
gem5::o3::LSQUnit::LSQEntry::setRequest
void setRequest(LSQRequest *r)
Definition: lsq_unit.hh:141
gem5::o3::LSQUnit::SQEntry::canWB
bool & canWB()
Member accessors.
Definition: lsq_unit.hh:188
gem5::o3::LSQUnit::SQEntry::committed
const bool & committed() const
Definition: lsq_unit.hh:193
gem5::o3::LSQUnit::iewStage
IEW * iewStage
Pointer to the IEW stage.
Definition: lsq_unit.hh:401
gem5::o3::LSQUnit::memDepViolator
DynInstPtr memDepViolator
The oldest load that caused a memory ordering violation.
Definition: lsq_unit.hh:543
gem5::o3::LSQUnit::resetHtmStartsStops
void resetHtmStartsStops()
Definition: lsq_unit.hh:313
gem5::o3::LSQUnit::stallingLoadIdx
int stallingLoadIdx
The index of the above store.
Definition: lsq_unit.hh:531
gem5::o3::LSQUnit::isFull
bool isFull()
Returns if either the LQ or SQ is full.
Definition: lsq_unit.hh:323
gem5::o3::LSQUnit::LSQUnit
LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
Constructs an LSQ unit.
Definition: lsq_unit.cc:203
gem5::o3::LSQUnit::read
Fault read(LSQRequest *req, int load_idx)
Executes the load at the given index.
Definition: lsq_unit.cc:1305
gem5::o3::LSQUnit::SQEntry::data
char * data()
Definition: lsq_unit.hh:196
gem5::o3::LSQUnit::WritebackEvent::lsqPtr
LSQUnit * lsqPtr
The pointer to the LSQ unit that issued the store.
Definition: lsq_unit.hh:468
gem5::o3::LSQUnit::numHtmStarts
int numHtmStarts() const
Definition: lsq_unit.hh:311
gem5::o3::LSQUnit::numFreeStoreEntries
unsigned numFreeStoreEntries()
Returns the number of free SQ entries.
Definition: lsq_unit.cc:433
gem5::o3::LSQUnit::init
void init(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params, LSQ *lsq_ptr, unsigned id)
Initializes the LSQ unit with the specified number of entries.
Definition: lsq_unit.cc:214
gem5::o3::LSQUnit::LSQUnitStats::ignoredResponses
statistics::Scalar ignoredResponses
Total number of responses from the memory system that are ignored due to the instruction already bein...
Definition: lsq_unit.hh:564
gem5::o3::LSQUnit::schedule
void schedule(Event &ev, Tick when)
Schedule event for the cpu.
Definition: lsq_unit.cc:1294
gem5::o3::LSQUnit::sqFull
bool sqFull()
Returns if the SQ is full.
Definition: lsq_unit.hh:332
gem5::o3::LSQUnit::SQEntry::_isAllZeros
bool _isAllZeros
Does this request write all zeros and thus doesn't have any data attached to it.
Definition: lsq_unit.hh:167
gem5::o3::LSQUnit::htmStops
int htmStops
Definition: lsq_unit.hh:509
gem5::o3::LSQUnit::getLoadHead
int getLoadHead()
Returns the index of the head load instruction.
Definition: lsq_unit.hh:591
gem5::o3::LSQUnit::MaxDataBytes
static constexpr auto MaxDataBytes
Definition: lsq_unit.hh:93
gem5::o3::LSQ
Definition: lsq.hh:75
gem5::o3::LSQUnit::storesToWB
int storesToWB
The number of store instructions in the SQ waiting to writeback.
Definition: lsq_unit.hh:504
gem5::o3::LSQUnit::cacheBlockMask
Addr cacheBlockMask
Address Mask for a cache block (e.g.
Definition: lsq_unit.hh:519
gem5::o3::LSQUnit::numStoresToWB
int numStoresToWB()
Returns the number of stores to writeback.
Definition: lsq_unit.hh:347
gem5::o3::LSQUnit::setDcachePort
void setDcachePort(RequestPort *dcache_port)
Sets the pointer to the dcache port.
Definition: lsq_unit.cc:292
gem5::o3::LSQUnit::LQSenderState::LQSenderState
LQSenderState(typename LoadQueue::iterator idx_)
Definition: lsq_unit.hh:414
gem5::CircularQueue::full
bool full() const
Is the queue full? A queue is full if the head is the 0^{th} element and the tail is the (size-1)^{th...
Definition: circular_queue.hh:558
gem5::o3::LSQUnit::LSQEntry::hasRequest
bool hasRequest()
Definition: lsq_unit.hh:142
gem5::o3::LSQUnit::getCount
unsigned getCount()
Returns the number of instructions in the LSQ.
Definition: lsq_unit.hh:341
gem5::o3::LSQUnit::LSQUnitStats::loadToUse
statistics::Distribution loadToUse
Distribution of cycle latency between the first time a load is issued and its completion.
Definition: lsq_unit.hh:580
gem5::o3::LSQUnit::SQEntry::_committed
bool _committed
Whether or not the store is committed.
Definition: lsq_unit.hh:160
gem5::o3::LSQUnit::LSQEntry::valid
bool valid() const
Member accessors.
Definition: lsq_unit.hh:145
gem5::o3::LSQUnit::depCheckShift
unsigned depCheckShift
The number of places to shift addresses in the LSQ before checking for dependency violations.
Definition: lsq_unit.hh:494
gem5::o3::LSQUnit::LSQEntry::~LSQEntry
~LSQEntry()
Definition: lsq_unit.hh:111
gem5::o3::LSQUnit::AddrRangeCoverage::PartialAddrRangeCoverage
@ PartialAddrRangeCoverage
gem5::o3::LSQUnit::numFreeLoadEntries
unsigned numFreeLoadEntries()
Returns the number of free LQ entries.
Definition: lsq_unit.cc:423
gem5::o3::LSQUnit::getStoreHead
int getStoreHead()
Returns the index of the head store instruction.
Definition: lsq_unit.hh:597
gem5::o3::LSQUnit::LSQEntry::size
const uint32_t & size() const
Definition: lsq_unit.hh:147
gem5::o3::LSQUnit::setLastRetiredHtmUid
void setLastRetiredHtmUid(uint64_t htm_uid)
Definition: lsq_unit.hh:316
gem5::RefCountingPtr< DynInst >
gem5::BaseMMU
Definition: mmu.hh:50
gem5::o3::LSQUnit::SQEntry::_completed
bool _completed
Whether or not the store is completed.
Definition: lsq_unit.hh:162
packet.hh
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::o3::LSQUnit::getLatestHtmUid
uint64_t getLatestHtmUid() const
Definition: lsq_unit.cc:1055
gem5::o3::LSQUnit::completeStore
void completeStore(typename StoreQueue::iterator store_idx)
Completes the store at the specified index.
Definition: lsq_unit.cc:1155
gem5::o3::LSQUnit::needsTSO
bool needsTSO
Flag for memory model.
Definition: lsq_unit.hh:546
gem5::o3::LSQUnit::LSQEntry::_size
uint32_t _size
The size of the operation.
Definition: lsq_unit.hh:106
timebuf.hh
gem5::o3::LSQUnit::LQueue
CircularQueue< LQEntry > LQueue
Definition: lsq_unit.hh:606
gem5::o3::LSQUnit::LSQUnitStats::forwLoads
statistics::Scalar forwLoads
Total number of loads forwaded from LSQ stores.
Definition: lsq_unit.hh:557
gem5::o3::LSQUnit::LSQUnitStats::blockedByCache
statistics::Scalar blockedByCache
Number of times the LSQ is blocked due to the cache.
Definition: lsq_unit.hh:576
comm.hh
gem5::o3::LSQUnit::SQEntry::isAllZeros
const bool & isAllZeros() const
Definition: lsq_unit.hh:195
gem5::o3::LSQUnit::WritebackEvent
Writeback event, specifically for when stores forward data to loads.
Definition: lsq_unit.hh:447
gem5::o3::LSQUnit::SQEntry::completed
bool & completed()
Definition: lsq_unit.hh:190
gem5::o3::LSQUnit::LSQEntry::set
void set(const DynInstPtr &new_inst)
Definition: lsq_unit.hh:132
gem5::o3::LSQUnit
Class that implements the actual LQ and SQ for each specific thread.
Definition: lsq_unit.hh:90
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::LSQUnit::stats
gem5::o3::LSQUnit::LSQUnitStats stats
gem5::o3::LSQUnit::commitLoad
void commitLoad()
Commits the head load.
Definition: lsq_unit.cc:721
gem5::o3::LSQUnit::LSQEntry
Definition: lsq_unit.hh:98
gem5::o3::LSQUnit::LSQUnitStats::rescheduledLoads
statistics::Scalar rescheduledLoads
Number of loads that were rescheduled.
Definition: lsq_unit.hh:573
gem5::o3::LSQUnit::LSQEntry::size
uint32_t & size()
Definition: lsq_unit.hh:146
circular_queue.hh
gem5::o3::LSQUnit::trySendPacket
bool trySendPacket(bool isLoad, PacketPtr data_pkt)
Attempts to send a packet to the cache.
Definition: lsq_unit.cc:1219
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::Event
Definition: eventq.hh:251
gem5::o3::LSQUnit::LQSenderState
Particularisation of the LSQSenderState to the LQ.
Definition: lsq_unit.hh:410
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::LSQUnit::loads
int loads
The number of load instructions in the LQ.
Definition: lsq_unit.hh:500
gem5::o3::LSQUnit::numStores
int numStores()
Returns the number of stores in the SQ.
Definition: lsq_unit.hh:308
gem5::o3::LSQUnit::isStoreBlocked
bool isStoreBlocked
Whehter or not a store is blocked due to the memory system.
Definition: lsq_unit.hh:537
gem5::o3::LSQUnit::SQEntry::set
void set(const DynInstPtr &inst)
Definition: lsq_unit.hh:177
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::o3::LSQUnit::WritebackEvent::WritebackEvent
WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr)
Constructs a writeback event.
Definition: lsq_unit.cc:66
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::LSQUnit::SQEntry::_data
char _data[MaxDataBytes]
The store data.
Definition: lsq_unit.hh:156
gem5::o3::LSQUnit::htmStarts
int htmStarts
Definition: lsq_unit.hh:508
gem5::o3::LSQUnit::cpu
CPU * cpu
Pointer to the CPU.
Definition: lsq_unit.hh:398
gem5::o3::LSQUnit::storeWBIt
StoreQueue::iterator storeWBIt
The index of the first instruction that may be ready to be written back, and has not yet been written...
Definition: lsq_unit.hh:516
gem5::o3::LSQUnit::lsqID
ThreadID lsqID
The LSQUnit thread id.
Definition: lsq_unit.hh:482
gem5::o3::LSQUnit::SQEntry::_canWB
bool _canWB
Whether or not the store can writeback.
Definition: lsq_unit.hh:158
gem5::o3::LSQUnit::write
Fault write(LSQRequest *req, uint8_t *data, int store_idx)
Executes the store at the given index.
Definition: lsq_unit.cc:1628
gem5::o3::LSQUnit::WritebackEvent::pkt
PacketPtr pkt
The packet that would have been sent to memory.
Definition: lsq_unit.hh:465
gem5::MaxVecRegLenInBytes
constexpr unsigned MaxVecRegLenInBytes
Definition: vec_reg.hh:111
gem5::o3::LSQUnit::SQEntry::committed
bool & committed()
Definition: lsq_unit.hh:192
port.hh
gem5::o3::LSQUnit::commitLoads
void commitLoads(InstSeqNum &youngest_inst)
Commits loads older than a specific sequence number.
Definition: lsq_unit.cc:746
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::o3::LSQUnit::completeDataAccess
void completeDataAccess(PacketPtr pkt)
Completes the data access that has been returned from the memory system.
Definition: lsq_unit.cc:111
gem5::o3::LSQ::LSQSenderState::alive
bool alive()
Definition: lsq.hh:116
gem5::o3::LSQUnit::SQSenderState::idx
StoreQueue::iterator idx
The SQ index of the instruction.
Definition: lsq_unit.hh:436
gem5::o3::LSQUnit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: lsq_unit.cc:308
gem5::o3::LSQUnit::SQSenderState::SQSenderState
SQSenderState(typename StoreQueue::iterator idx_)
Definition: lsq_unit.hh:433
gem5::o3::LSQUnit::retryPkt
PacketPtr retryPkt
The packet that needs to be retried.
Definition: lsq_unit.hh:534
gem5::o3::LSQUnit::checkViolations
Fault checkViolations(typename LoadQueue::iterator &loadIt, const DynInstPtr &inst)
Check for ordering violations in the LSQ.
Definition: lsq_unit.cc:524
gem5::o3::LSQUnit::LQIterator
CircularQueue< LQEntry >::iterator LQIterator
Definition: lsq_unit.hh:604
gem5::o3::LSQUnit::stores
int stores
The number of store instructions in the SQ.
Definition: lsq_unit.hh:502
gem5::o3::LSQUnit::writeback
void writeback(const DynInstPtr &inst, PacketPtr pkt)
Writes back the instruction, sending it to IEW.
Definition: lsq_unit.cc:1093
gem5::o3::LSQUnit::numLoads
int numLoads()
Returns the number of loads in the LQ.
Definition: lsq_unit.hh:305
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::LSQUnit::AddrRangeCoverage::FullAddrRangeCoverage
@ FullAddrRangeCoverage
gem5::o3::LSQUnit::squash
void squash(const InstSeqNum &squashed_num)
Squashes all instructions younger than a specific sequence number.
Definition: lsq_unit.cc:938
dyn_inst_ptr.hh
gem5::o3::LSQUnit::LSQUnit
LSQUnit(const LSQUnit &l)
We cannot copy LSQUnit because it has stats for which copy contructor is deleted explicitly.
Definition: lsq_unit.hh:222
gem5::o3::LSQUnit::LSQUnitStats::squashedStores
statistics::Scalar squashedStores
Total number of squashed stores.
Definition: lsq_unit.hh:570
gem5::o3::LSQUnit::willWB
bool willWB()
Returns if the LSQ unit will writeback on this cycle.
Definition: lsq_unit.hh:351
gem5::o3::LSQUnit::SQIterator
CircularQueue< SQEntry >::iterator SQIterator
Definition: lsq_unit.hh:605
gem5::o3::LSQUnit::SQEntry::clear
void clear()
Definition: lsq_unit.hh:180
gem5::o3::LSQUnit::LSQEntry::instruction
const DynInstPtr & instruction() const
Definition: lsq_unit.hh:148
vec_reg.hh
gem5::o3::LSQUnit::executeStore
Fault executeStore(const DynInstPtr &inst)
Executes a store instruction.
Definition: lsq_unit.cc:670
gem5::o3::LSQUnit::writebackBlockedStore
void writebackBlockedStore()
Try to finish a previously blocked write back attempt.
Definition: lsq_unit.cc:783
gem5::o3::LSQUnit::WritebackEvent::inst
DynInstPtr inst
Instruction whose results are being written back.
Definition: lsq_unit.hh:462
gem5::o3::LSQUnit::insert
void insert(const DynInstPtr &inst)
Inserts an instruction.
Definition: lsq_unit.cc:314
gem5::o3::LSQUnit::dcachePort
RequestPort * dcachePort
Pointer to the dcache port.
Definition: lsq_unit.hh:407
gem5::o3::LSQ::LSQSenderState
Derived class to hold any sender state the LSQ needs.
Definition: lsq.hh:80
gem5::o3::LSQUnit::hasStoresToWB
bool hasStoresToWB()
Returns if there are any stores to writeback.
Definition: lsq_unit.hh:344
gem5::o3::LSQUnit::stalled
bool stalled
Whether or not the LSQ is stalled.
Definition: lsq_unit.hh:525
gem5::o3::LSQUnit::LSQEntry::req
LSQRequest * req
The request.
Definition: lsq_unit.hh:104
gem5::o3::LSQUnit::LSQEntry::clear
void clear()
Definition: lsq_unit.hh:120
base.hh
gem5::CircularQueue::head
size_t head() const
Definition: circular_queue.hh:451
gem5::o3::LSQUnit::SQEntry::DataSize
static constexpr size_t DataSize
Definition: lsq_unit.hh:170
gem5::o3::LSQUnit::getMMUPtr
BaseMMU * getMMUPtr()
Definition: lsq_unit.cc:1296
gem5::o3::LSQUnit::lsq
LSQ * lsq
Pointer to the LSQ.
Definition: lsq_unit.hh:404
gem5::o3::LSQUnit::numHtmStops
int numHtmStops() const
Definition: lsq_unit.hh:312
gem5::o3::LSQUnit::executeLoad
Fault executeLoad(const DynInstPtr &inst)
Executes a load instruction.
Definition: lsq_unit.cc:604
gem5::o3::LSQUnit::recvRetry
void recvRetry()
Handles doing the retry.
Definition: lsq_unit.cc:1262
gem5::o3::LSQUnit::LSQUnitStats
Definition: lsq_unit.hh:552
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::LSQUnit::SQSenderState::complete
virtual void complete()
Definition: lsq_unit.hh:439
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::o3::LSQUnit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: lsq_unit.cc:298
gem5::o3::LSQUnit::commitStores
void commitStores(InstSeqNum &youngest_inst)
Commits stores older than a specific sequence number.
Definition: lsq_unit.cc:757
gem5::o3::LSQUnit::LSQEntry::_valid
bool _valid
Valid entry.
Definition: lsq_unit.hh:108
gem5::o3::LSQUnit::SQEntry::completed
const bool & completed() const
Definition: lsq_unit.hh:191
gem5::o3::LSQUnit::resetState
void resetState()
Reset the LSQ state.
Definition: lsq_unit.cc:237
gem5::o3::LSQUnit::SQEntry
Definition: lsq_unit.hh:152
gem5::o3::LSQUnit::SQSenderState
Particularisation of the LSQSenderState to the SQ.
Definition: lsq_unit.hh:429
gem5::o3::LSQUnit::SQEntry::canWB
const bool & canWB() const
Definition: lsq_unit.hh:189
gem5::o3::LSQUnit::SQueue
CircularQueue< SQEntry > SQueue
Definition: lsq_unit.hh:607
gem5::o3::LSQUnit::LQSenderState::idx
LoadQueue::iterator idx
The LQ index of the instruction.
Definition: lsq_unit.hh:418
debugfaults.hh
cpu.hh
gem5::o3::LSQUnit::getMemDepViolator
DynInstPtr getMemDepViolator()
Returns the memory ordering violator.
Definition: lsq_unit.cc:413
gem5::o3::LSQUnit::isEmpty
bool isEmpty() const
Returns if both the LQ and SQ are empty.
Definition: lsq_unit.hh:326
gem5::o3::LSQUnit::getStoreHeadSeqNum
InstSeqNum getStoreHeadSeqNum()
Returns the sequence number of the head store instruction.
Definition: lsq_unit.cc:1666
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::LSQUnit::loadQueue
LoadQueue loadQueue
The load queue.
Definition: lsq_unit.hh:488
gem5::o3::LSQUnit::name
std::string name() const
Returns the name of the LSQ unit.
Definition: lsq_unit.cc:256
lsq.hh
gem5::o3::LSQUnit::AddrRangeCoverage::NoAddrRangeCoverage
@ NoAddrRangeCoverage
gem5::o3::LSQUnit::AddrRangeCoverage
AddrRangeCoverage
Coverage of one address range with another.
Definition: lsq_unit.hh:203
gem5::o3::LSQUnit::dumpInsts
void dumpInsts() const
Debugging function to dump instructions in the LSQ.
Definition: lsq_unit.cc:1271
gem5::o3::LSQUnit::lqFull
bool lqFull()
Returns if the LQ is full.
Definition: lsq_unit.hh:329
gem5::o3::LSQUnit::SQEntry::data
const char * data() const
Definition: lsq_unit.hh:197
gem5::CircularQueue< LQEntry >
gem5::o3::LSQUnit::insertLoad
void insertLoad(const DynInstPtr &load_inst)
Inserts a load instruction.
Definition: lsq_unit.cc:330
gem5::o3::LSQUnit::cacheLineSize
unsigned int cacheLineSize()
Definition: lsq_unit.cc:1299
gem5::o3::LSQUnit::fromIssue
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: lsq_unit.hh:522
gem5::o3::LSQUnit::storeQueue
CircularQueue< SQEntry > storeQueue
The store queue.
Definition: lsq_unit.hh:485
gem5::o3::LSQ::LSQSenderState::request
LSQRequest * request()
Definition: lsq.hh:117
gem5::o3::LSQUnit::getLoadHeadSeqNum
InstSeqNum getLoadHeadSeqNum()
Returns the sequence number of the head load instruction.
Definition: lsq_unit.cc:1657
gem5::o3::LSQUnit::writebackStores
void writebackStores()
Writes back stores.
Definition: lsq_unit.cc:793
gem5::o3::LSQUnit::executeLoad
Fault executeLoad(int lq_idx)
Definition: lsq_unit.hh:268
gem5::o3::LSQUnit::lqEmpty
bool lqEmpty() const
Returns if the LQ is empty.
Definition: lsq_unit.hh:335
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::TimeBuffer::wire
Definition: timebuf.hh:59
gem5::o3::LSQUnit::checkSnoop
void checkSnoop(PacketPtr pkt)
Check if an incoming invalidate hits in the lsq on a load that might have issued out of order wrt ano...
Definition: lsq_unit.cc:444
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::LSQUnit::LSQUnitStats::LSQUnitStats
LSQUnitStats(statistics::Group *parent)
Definition: lsq_unit.cc:265
gem5::o3::LSQ::LSQRequest::freeLSQEntry
void freeLSQEntry()
The LSQ entry is cleared.
Definition: lsq.hh:569

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