gem5  v22.0.0.2
lsq_unit.hh
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41 
42 #ifndef __CPU_O3_LSQ_UNIT_HH__
43 #define __CPU_O3_LSQ_UNIT_HH__
44 
45 #include <algorithm>
46 #include <cstring>
47 #include <map>
48 #include <memory>
49 #include <queue>
50 
52 #include "arch/generic/vec_reg.hh"
53 #include "base/circular_queue.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/base.hh"
56 #include "cpu/inst_seq.hh"
57 #include "cpu/o3/comm.hh"
58 #include "cpu/o3/cpu.hh"
59 #include "cpu/o3/dyn_inst_ptr.hh"
60 #include "cpu/o3/lsq.hh"
61 #include "cpu/timebuf.hh"
62 #include "debug/HtmCpu.hh"
63 #include "debug/LSQUnit.hh"
64 #include "mem/packet.hh"
65 #include "mem/port.hh"
66 
67 namespace gem5
68 {
69 
70 struct BaseO3CPUParams;
71 
72 namespace o3
73 {
74 
75 class IEW;
76 
89 class LSQUnit
90 {
91  public:
92  static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
93 
95  private:
96  class LSQEntry
97  {
98  private:
102  LSQRequest* _request = nullptr;
104  uint32_t _size = 0;
106  bool _valid = false;
107 
108  public:
110  {
111  if (_request != nullptr) {
113  _request = nullptr;
114  }
115  }
116 
117  void
119  {
120  _inst = nullptr;
121  if (_request != nullptr) {
123  }
124  _request = nullptr;
125  _valid = false;
126  _size = 0;
127  }
128 
129  void
130  set(const DynInstPtr& new_inst)
131  {
132  assert(!_valid);
133  _inst = new_inst;
134  _valid = true;
135  _size = 0;
136  }
137 
138  LSQRequest* request() { return _request; }
140  bool hasRequest() { return _request != nullptr; }
143  bool valid() const { return _valid; }
144  uint32_t& size() { return _size; }
145  const uint32_t& size() const { return _size; }
146  const DynInstPtr& instruction() const { return _inst; }
148  };
149 
150  class SQEntry : public LSQEntry
151  {
152  private:
156  bool _canWB = false;
158  bool _committed = false;
160  bool _completed = false;
165  bool _isAllZeros = false;
166 
167  public:
168  static constexpr size_t DataSize = sizeof(_data);
171  {
172  std::memset(_data, 0, DataSize);
173  }
174 
175  void set(const DynInstPtr& inst) { LSQEntry::set(inst); }
176 
177  void
179  {
180  LSQEntry::clear();
181  _canWB = _completed = _committed = _isAllZeros = false;
182  }
183 
186  bool& canWB() { return _canWB; }
187  const bool& canWB() const { return _canWB; }
188  bool& completed() { return _completed; }
189  const bool& completed() const { return _completed; }
190  bool& committed() { return _committed; }
191  const bool& committed() const { return _committed; }
192  bool& isAllZeros() { return _isAllZeros; }
193  const bool& isAllZeros() const { return _isAllZeros; }
194  char* data() { return _data; }
195  const char* data() const { return _data; }
197  };
198  using LQEntry = LSQEntry;
199 
201  enum class AddrRangeCoverage
202  {
203  PartialAddrRangeCoverage, /* Two ranges partly overlap */
204  FullAddrRangeCoverage, /* One range fully covers another */
205  NoAddrRangeCoverage /* Two ranges are disjoint */
206  };
207 
208  public:
211 
212  public:
214  LSQUnit(uint32_t lqEntries, uint32_t sqEntries);
215 
220  LSQUnit(const LSQUnit &l): stats(nullptr)
221  {
222  panic("LSQUnit is not copy-able");
223  }
224 
226  void init(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params,
227  LSQ *lsq_ptr, unsigned id);
228 
230  std::string name() const;
231 
233  void setDcachePort(RequestPort *dcache_port);
234 
236  void drainSanityCheck() const;
237 
239  void takeOverFrom();
240 
242  void insert(const DynInstPtr &inst);
244  void insertLoad(const DynInstPtr &load_inst);
246  void insertStore(const DynInstPtr &store_inst);
247 
254  Fault checkViolations(typename LoadQueue::iterator& loadIt,
255  const DynInstPtr& inst);
256 
261  void checkSnoop(PacketPtr pkt);
262 
264  Fault executeLoad(const DynInstPtr &inst);
265 
266  Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
268  Fault executeStore(const DynInstPtr &inst);
269 
271  void commitLoad();
273  void commitLoads(InstSeqNum &youngest_inst);
274 
276  void commitStores(InstSeqNum &youngest_inst);
277 
279  void writebackStores();
280 
283  void completeDataAccess(PacketPtr pkt);
284 
286  void squash(const InstSeqNum &squashed_num);
287 
291  bool violation() { return memDepViolator; }
292 
295 
297  unsigned numFreeLoadEntries();
298 
300  unsigned numFreeStoreEntries();
301 
303  int numLoads() { return loadQueue.size(); }
304 
306  int numStores() { return storeQueue.size(); }
307 
308  // hardware transactional memory
309  int numHtmStarts() const { return htmStarts; }
310  int numHtmStops() const { return htmStops; }
312  uint64_t getLatestHtmUid() const;
313  void
314  setLastRetiredHtmUid(uint64_t htm_uid)
315  {
316  assert(htm_uid >= lastRetiredHtmUid);
317  lastRetiredHtmUid = htm_uid;
318  }
319 
320  // Stale translation checks
322  bool checkStaleTranslations() const;
323 
325  bool isFull() { return lqFull() || sqFull(); }
326 
328  bool isEmpty() const { return lqEmpty() && sqEmpty(); }
329 
331  bool lqFull() { return loadQueue.full(); }
332 
334  bool sqFull() { return storeQueue.full(); }
335 
337  bool lqEmpty() const { return loadQueue.size() == 0; }
338 
340  bool sqEmpty() const { return storeQueue.size() == 0; }
341 
343  unsigned getCount() { return loadQueue.size() + storeQueue.size(); }
344 
346  bool hasStoresToWB() { return storesToWB; }
347 
349  int numStoresToWB() { return storesToWB; }
350 
352  bool
354  {
355  return storeWBIt.dereferenceable() &&
356  storeWBIt->valid() &&
357  storeWBIt->canWB() &&
358  !storeWBIt->completed() &&
360  }
361 
363  void recvRetry();
364 
365  unsigned int cacheLineSize();
366  private:
368  void resetState();
369 
371  void writeback(const DynInstPtr &inst, PacketPtr pkt);
372 
374  void writebackBlockedStore();
375 
377  void completeStore(typename StoreQueue::iterator store_idx);
378 
380  void storePostSend();
381 
382  public:
387  bool trySendPacket(bool isLoad, PacketPtr data_pkt);
388 
389 
391  void dumpInsts() const;
392 
394  void schedule(Event& ev, Tick when);
395 
396  BaseMMU *getMMUPtr();
397 
398  private:
401 
404 
407 
410 
412  class WritebackEvent : public Event
413  {
414  public:
416  WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt,
417  LSQUnit *lsq_ptr);
418 
420  void process();
421 
423  const char *description() const;
424 
425  private:
428 
431 
434  };
435 
436  public:
443  bool recvTimingResp(PacketPtr pkt);
444 
445  private:
448  public:
451 
454 
455  private:
459  unsigned depCheckShift;
460 
463 
466 
467  // hardware transactional memory
468  // nesting depth
470  int htmStops;
471  // sanity checks and debugging
473 
477  typename StoreQueue::iterator storeWBIt;
478 
481 
484 
486  bool stalled;
493 
496 
499 
502 
505 
507  bool needsTSO;
508 
509  protected:
510  // Will also need how many read/write ports the Dcache has. Or keep track
511  // of that in stage that is one level up, and only call executeLoad/Store
512  // the appropriate number of times.
514  {
516 
519 
522 
526 
529 
532 
535 
538 
542  } stats;
543 
544  public:
546  Fault read(LSQRequest *request, ssize_t load_idx);
547 
549  Fault write(LSQRequest *requst, uint8_t *data, ssize_t store_idx);
550 
552  int getLoadHead() { return loadQueue.head(); }
553 
556 
558  int getStoreHead() { return storeQueue.head(); }
561 
563  bool isStalled() { return stalled; }
564  public:
567 };
568 
569 } // namespace o3
570 } // namespace gem5
571 
572 #endif // __CPU_O3_LSQ_UNIT_HH__
gem5::o3::LSQUnit::sqEmpty
bool sqEmpty() const
Returns if the SQ is empty.
Definition: lsq_unit.hh:340
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::o3::LSQUnit::SQEntry::isAllZeros
bool & isAllZeros()
Definition: lsq_unit.hh:192
gem5::o3::LSQUnit::storePostSend
void storePostSend()
Handles completing the send of a store to memory.
Definition: lsq_unit.cc:1044
gem5::o3::LSQUnit::LSQUnitStats::squashedLoads
statistics::Scalar squashedLoads
Total number of squashed loads.
Definition: lsq_unit.hh:521
gem5::o3::LSQUnit::WritebackEvent::process
void process()
Processes the writeback event.
Definition: lsq_unit.cc:75
gem5::o3::LSQUnit::lastRetiredHtmUid
uint64_t lastRetiredHtmUid
Definition: lsq_unit.hh:472
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:189
gem5::o3::LSQUnit::init
void init(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params, LSQ *lsq_ptr, unsigned id)
Initializes the LSQ unit with the specified number of entries.
Definition: lsq_unit.cc:204
gem5::o3::LSQUnit::SQEntry::SQEntry
SQEntry()
Constructs an empty store queue entry.
Definition: lsq_unit.hh:170
gem5::o3::LSQUnit::violation
bool violation()
Returns if there is a memory ordering violation.
Definition: lsq_unit.hh:291
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::o3::LSQUnit::stallingStoreIsn
InstSeqNum stallingStoreIsn
The store that causes the stall due to partial store to load forwarding.
Definition: lsq_unit.hh:490
gem5::o3::LSQUnit::insertStore
void insertStore(const DynInstPtr &store_inst)
Inserts a store instruction.
Definition: lsq_unit.cc:380
gem5::o3::LSQUnit::storeInFlight
bool storeInFlight
Whether or not a store is in flight.
Definition: lsq_unit.hh:501
gem5::o3::LSQUnit::LSQEntry::request
LSQRequest * request()
Definition: lsq_unit.hh:138
gem5::o3::LSQUnit::WritebackEvent::description
const char * description() const
Returns the description of this event.
Definition: lsq_unit.cc:87
gem5::o3::LSQUnit::isStalled
bool isStalled()
Returns whether or not the LSQ unit is stalled.
Definition: lsq_unit.hh:563
gem5::o3::LSQUnit::checkLoads
bool checkLoads
Should loads be checked for dependency issues.
Definition: lsq_unit.hh:462
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2084
gem5::o3::LSQUnit::LSQUnitStats::memOrderViolation
statistics::Scalar memOrderViolation
Tota number of memory ordering violations.
Definition: lsq_unit.hh:528
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::o3::LSQUnit::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Handles writing back and completing the load or store that has returned from memory.
Definition: lsq_unit.cc:93
gem5::o3::LSQUnit::LSQEntry::setRequest
void setRequest(LSQRequest *r)
Definition: lsq_unit.hh:139
gem5::o3::LSQUnit::SQEntry::canWB
bool & canWB()
Member accessors.
Definition: lsq_unit.hh:186
gem5::o3::LSQUnit::SQEntry::committed
const bool & committed() const
Definition: lsq_unit.hh:191
gem5::o3::LSQUnit::iewStage
IEW * iewStage
Pointer to the IEW stage.
Definition: lsq_unit.hh:403
gem5::o3::LSQUnit::memDepViolator
DynInstPtr memDepViolator
The oldest load that caused a memory ordering violation.
Definition: lsq_unit.hh:504
gem5::o3::LSQUnit::resetHtmStartsStops
void resetHtmStartsStops()
Definition: lsq_unit.hh:311
gem5::o3::LSQUnit::isFull
bool isFull()
Returns if either the LQ or SQ is full.
Definition: lsq_unit.hh:325
gem5::o3::LSQUnit::LSQUnit
LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
Constructs an LSQ unit.
Definition: lsq_unit.cc:193
gem5::o3::LSQUnit::SQEntry::data
char * data()
Definition: lsq_unit.hh:194
gem5::o3::LSQUnit::WritebackEvent::lsqPtr
LSQUnit * lsqPtr
The pointer to the LSQ unit that issued the store.
Definition: lsq_unit.hh:433
gem5::o3::LSQUnit::numHtmStarts
int numHtmStarts() const
Definition: lsq_unit.hh:309
gem5::o3::LSQUnit::numFreeStoreEntries
unsigned numFreeStoreEntries()
Returns the number of free SQ entries.
Definition: lsq_unit.cc:419
gem5::o3::LSQUnit::LSQUnitStats::ignoredResponses
statistics::Scalar ignoredResponses
Total number of responses from the memory system that are ignored due to the instruction already bein...
Definition: lsq_unit.hh:525
gem5::o3::LSQUnit::write
Fault write(LSQRequest *requst, uint8_t *data, ssize_t store_idx)
Executes the store at the given index.
Definition: lsq_unit.cc:1603
gem5::o3::LSQUnit::startStaleTranslationFlush
void startStaleTranslationFlush()
Definition: lsq_unit.cc:1242
gem5::o3::LSQUnit::schedule
void schedule(Event &ev, Tick when)
Schedule event for the cpu.
Definition: lsq_unit.cc:1307
gem5::o3::LSQUnit::sqFull
bool sqFull()
Returns if the SQ is full.
Definition: lsq_unit.hh:334
gem5::o3::LSQUnit::SQEntry::_isAllZeros
bool _isAllZeros
Does this request write all zeros and thus doesn't have any data attached to it.
Definition: lsq_unit.hh:165
gem5::o3::LSQUnit::htmStops
int htmStops
Definition: lsq_unit.hh:470
gem5::o3::LSQUnit::getLoadHead
int getLoadHead()
Returns the index of the head load instruction.
Definition: lsq_unit.hh:552
gem5::o3::LSQUnit::MaxDataBytes
static constexpr auto MaxDataBytes
Definition: lsq_unit.hh:92
gem5::o3::LSQ
Definition: lsq.hh:75
gem5::o3::LSQUnit::storesToWB
int storesToWB
The number of store instructions in the SQ waiting to writeback.
Definition: lsq_unit.hh:465
gem5::o3::LSQUnit::stallingLoadIdx
ssize_t stallingLoadIdx
The index of the above store.
Definition: lsq_unit.hh:492
gem5::o3::LSQUnit::cacheBlockMask
Addr cacheBlockMask
Address Mask for a cache block (e.g.
Definition: lsq_unit.hh:480
gem5::o3::LSQUnit::numStoresToWB
int numStoresToWB()
Returns the number of stores to writeback.
Definition: lsq_unit.hh:349
gem5::o3::LSQUnit::setDcachePort
void setDcachePort(RequestPort *dcache_port)
Sets the pointer to the dcache port.
Definition: lsq_unit.cc:282
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::CircularQueue::full
bool full() const
Is the queue full? A queue is full if the head is the 0^{th} element and the tail is the (size-1)^{th...
Definition: circular_queue.hh:558
gem5::o3::LSQUnit::LSQEntry::hasRequest
bool hasRequest()
Definition: lsq_unit.hh:140
gem5::o3::LSQUnit::getCount
unsigned getCount()
Returns the number of instructions in the LSQ.
Definition: lsq_unit.hh:343
gem5::o3::LSQUnit::LSQUnitStats::loadToUse
statistics::Distribution loadToUse
Distribution of cycle latency between the first time a load is issued and its completion.
Definition: lsq_unit.hh:541
gem5::o3::LSQUnit::SQEntry::_committed
bool _committed
Whether or not the store is committed.
Definition: lsq_unit.hh:158
gem5::o3::LSQUnit::LSQEntry::valid
bool valid() const
Member accessors.
Definition: lsq_unit.hh:143
gem5::o3::LSQUnit::depCheckShift
unsigned depCheckShift
The number of places to shift addresses in the LSQ before checking for dependency violations.
Definition: lsq_unit.hh:459
gem5::o3::LSQUnit::LSQEntry::~LSQEntry
~LSQEntry()
Definition: lsq_unit.hh:109
gem5::o3::LSQUnit::AddrRangeCoverage::PartialAddrRangeCoverage
@ PartialAddrRangeCoverage
gem5::o3::LSQUnit::numFreeLoadEntries
unsigned numFreeLoadEntries()
Returns the number of free LQ entries.
Definition: lsq_unit.cc:411
gem5::o3::LSQUnit::getStoreHead
int getStoreHead()
Returns the index of the head store instruction.
Definition: lsq_unit.hh:558
gem5::o3::LSQUnit::LSQEntry::size
const uint32_t & size() const
Definition: lsq_unit.hh:145
gem5::o3::LSQUnit::setLastRetiredHtmUid
void setLastRetiredHtmUid(uint64_t htm_uid)
Definition: lsq_unit.hh:314
gem5::RefCountingPtr< DynInst >
gem5::BaseMMU
Definition: mmu.hh:53
gem5::o3::LSQUnit::SQEntry::_completed
bool _completed
Whether or not the store is completed.
Definition: lsq_unit.hh:160
packet.hh
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::o3::LSQUnit::getLatestHtmUid
uint64_t getLatestHtmUid() const
Definition: lsq_unit.cc:1037
gem5::o3::LSQUnit::completeStore
void completeStore(typename StoreQueue::iterator store_idx)
Completes the store at the specified index.
Definition: lsq_unit.cc:1137
gem5::o3::LSQUnit::needsTSO
bool needsTSO
Flag for memory model.
Definition: lsq_unit.hh:507
gem5::o3::LSQUnit::LSQEntry::_size
uint32_t _size
The size of the operation.
Definition: lsq_unit.hh:104
timebuf.hh
gem5::o3::LSQUnit::LSQUnitStats::forwLoads
statistics::Scalar forwLoads
Total number of loads forwaded from LSQ stores.
Definition: lsq_unit.hh:518
gem5::o3::LSQUnit::LSQUnitStats::blockedByCache
statistics::Scalar blockedByCache
Number of times the LSQ is blocked due to the cache.
Definition: lsq_unit.hh:537
comm.hh
gem5::o3::LSQUnit::SQEntry::isAllZeros
const bool & isAllZeros() const
Definition: lsq_unit.hh:193
gem5::o3::LSQUnit::WritebackEvent
Writeback event, specifically for when stores forward data to loads.
Definition: lsq_unit.hh:412
gem5::o3::LSQUnit::SQEntry::completed
bool & completed()
Definition: lsq_unit.hh:188
gem5::o3::LSQUnit::LSQEntry::set
void set(const DynInstPtr &new_inst)
Definition: lsq_unit.hh:130
gem5::o3::LSQUnit
Class that implements the actual LQ and SQ for each specific thread.
Definition: lsq_unit.hh:89
gem5::CircularQueue::size
size_t size() const
Definition: circular_queue.hh:466
gem5::o3::LSQUnit::storeQueue
StoreQueue storeQueue
The store queue.
Definition: lsq_unit.hh:450
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::LSQUnit::stats
gem5::o3::LSQUnit::LSQUnitStats stats
gem5::o3::LSQUnit::commitLoad
void commitLoad()
Commits the head load.
Definition: lsq_unit.cc:720
gem5::o3::LSQUnit::LSQEntry
Definition: lsq_unit.hh:96
gem5::o3::LSQUnit::LSQUnitStats::rescheduledLoads
statistics::Scalar rescheduledLoads
Number of loads that were rescheduled.
Definition: lsq_unit.hh:534
gem5::o3::LSQUnit::LSQEntry::size
uint32_t & size()
Definition: lsq_unit.hh:144
circular_queue.hh
gem5::o3::LSQUnit::trySendPacket
bool trySendPacket(bool isLoad, PacketPtr data_pkt)
Attempts to send a packet to the cache.
Definition: lsq_unit.cc:1200
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::o3::LSQUnit::numStores
int numStores()
Returns the number of stores in the SQ.
Definition: lsq_unit.hh:306
gem5::o3::LSQUnit::isStoreBlocked
bool isStoreBlocked
Whehter or not a store is blocked due to the memory system.
Definition: lsq_unit.hh:498
gem5::o3::LSQUnit::SQEntry::set
void set(const DynInstPtr &inst)
Definition: lsq_unit.hh:175
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::o3::LSQUnit::WritebackEvent::WritebackEvent
WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr)
Constructs a writeback event.
Definition: lsq_unit.cc:65
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::LSQUnit::SQEntry::_data
char _data[MaxDataBytes]
The store data.
Definition: lsq_unit.hh:154
gem5::o3::LSQUnit::htmStarts
int htmStarts
Definition: lsq_unit.hh:469
gem5::o3::LSQUnit::cpu
CPU * cpu
Pointer to the CPU.
Definition: lsq_unit.hh:400
gem5::o3::LSQUnit::storeWBIt
StoreQueue::iterator storeWBIt
The index of the first instruction that may be ready to be written back, and has not yet been written...
Definition: lsq_unit.hh:477
gem5::o3::LSQUnit::lsqID
ThreadID lsqID
The LSQUnit thread id.
Definition: lsq_unit.hh:447
gem5::o3::LSQUnit::SQEntry::_canWB
bool _canWB
Whether or not the store can writeback.
Definition: lsq_unit.hh:156
gem5::o3::LSQUnit::WritebackEvent::pkt
PacketPtr pkt
The packet that would have been sent to memory.
Definition: lsq_unit.hh:430
gem5::MaxVecRegLenInBytes
constexpr unsigned MaxVecRegLenInBytes
Definition: vec_reg.hh:113
gem5::o3::LSQUnit::SQEntry::committed
bool & committed()
Definition: lsq_unit.hh:190
port.hh
gem5::o3::LSQUnit::commitLoads
void commitLoads(InstSeqNum &youngest_inst)
Commits loads older than a specific sequence number.
Definition: lsq_unit.cc:743
gem5::o3::LSQUnit::completeDataAccess
void completeDataAccess(PacketPtr pkt)
Completes the data access that has been returned from the memory system.
Definition: lsq_unit.cc:106
gem5::o3::LSQUnit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: lsq_unit.cc:298
gem5::o3::LSQUnit::retryPkt
PacketPtr retryPkt
The packet that needs to be retried.
Definition: lsq_unit.hh:495
gem5::o3::LSQUnit::checkViolations
Fault checkViolations(typename LoadQueue::iterator &loadIt, const DynInstPtr &inst)
Check for ordering violations in the LSQ.
Definition: lsq_unit.cc:511
gem5::o3::LSQUnit::LQIterator
CircularQueue< LQEntry >::iterator LQIterator
Definition: lsq_unit.hh:565
gem5::o3::LSQUnit::writeback
void writeback(const DynInstPtr &inst, PacketPtr pkt)
Writes back the instruction, sending it to IEW.
Definition: lsq_unit.cc:1075
gem5::o3::LSQUnit::numLoads
int numLoads()
Returns the number of loads in the LQ.
Definition: lsq_unit.hh:303
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::LSQUnit::AddrRangeCoverage::FullAddrRangeCoverage
@ FullAddrRangeCoverage
gem5::o3::LSQUnit::squash
void squash(const InstSeqNum &squashed_num)
Squashes all instructions younger than a specific sequence number.
Definition: lsq_unit.cc:922
dyn_inst_ptr.hh
gem5::o3::LSQUnit::LSQUnit
LSQUnit(const LSQUnit &l)
We cannot copy LSQUnit because it has stats for which copy contructor is deleted explicitly.
Definition: lsq_unit.hh:220
gem5::o3::LSQUnit::LSQUnitStats::squashedStores
statistics::Scalar squashedStores
Total number of squashed stores.
Definition: lsq_unit.hh:531
gem5::o3::LSQUnit::willWB
bool willWB()
Returns if the LSQ unit will writeback on this cycle.
Definition: lsq_unit.hh:353
gem5::o3::LSQUnit::SQIterator
CircularQueue< SQEntry >::iterator SQIterator
Definition: lsq_unit.hh:566
gem5::o3::LSQUnit::SQEntry::clear
void clear()
Definition: lsq_unit.hh:178
gem5::o3::LSQUnit::LSQEntry::instruction
const DynInstPtr & instruction() const
Definition: lsq_unit.hh:146
vec_reg.hh
gem5::o3::LSQUnit::executeStore
Fault executeStore(const DynInstPtr &inst)
Executes a store instruction.
Definition: lsq_unit.cc:658
gem5::o3::LSQUnit::writebackBlockedStore
void writebackBlockedStore()
Try to finish a previously blocked write back attempt.
Definition: lsq_unit.cc:780
gem5::o3::LSQUnit::LSQEntry::_inst
DynInstPtr _inst
The instruction.
Definition: lsq_unit.hh:100
gem5::o3::LSQUnit::WritebackEvent::inst
DynInstPtr inst
Instruction whose results are being written back.
Definition: lsq_unit.hh:427
gem5::o3::LSQUnit::insert
void insert(const DynInstPtr &inst)
Inserts an instruction.
Definition: lsq_unit.cc:304
gem5::o3::LSQUnit::dcachePort
RequestPort * dcachePort
Pointer to the dcache port.
Definition: lsq_unit.hh:409
gem5::o3::LSQUnit::hasStoresToWB
bool hasStoresToWB()
Returns if there are any stores to writeback.
Definition: lsq_unit.hh:346
gem5::o3::LSQUnit::stalled
bool stalled
Whether or not the LSQ is stalled.
Definition: lsq_unit.hh:486
gem5::o3::LSQUnit::checkStaleTranslations
bool checkStaleTranslations() const
Definition: lsq_unit.cc:1257
gem5::o3::LSQUnit::LSQEntry::clear
void clear()
Definition: lsq_unit.hh:118
base.hh
gem5::o3::LSQUnit::read
Fault read(LSQRequest *request, ssize_t load_idx)
Executes the load at the given index.
Definition: lsq_unit.cc:1318
gem5::CircularQueue::head
size_t head() const
Definition: circular_queue.hh:451
gem5::o3::LSQUnit::SQEntry::DataSize
static constexpr size_t DataSize
Definition: lsq_unit.hh:168
gem5::o3::LSQUnit::getMMUPtr
BaseMMU * getMMUPtr()
Definition: lsq_unit.cc:1309
gem5::o3::LSQUnit::lsq
LSQ * lsq
Pointer to the LSQ.
Definition: lsq_unit.hh:406
gem5::o3::LSQUnit::numHtmStops
int numHtmStops() const
Definition: lsq_unit.hh:310
gem5::o3::LSQUnit::executeLoad
Fault executeLoad(const DynInstPtr &inst)
Executes a load instruction.
Definition: lsq_unit.cc:591
gem5::o3::LSQUnit::recvRetry
void recvRetry()
Handles doing the retry.
Definition: lsq_unit.cc:1275
gem5::o3::LSQUnit::LSQUnitStats
Definition: lsq_unit.hh:513
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::VegaISA::l
Bitfield< 55 > l
Definition: pagetable.hh:54
gem5::o3::LSQUnit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: lsq_unit.cc:288
gem5::o3::LSQUnit::commitStores
void commitStores(InstSeqNum &youngest_inst)
Commits stores older than a specific sequence number.
Definition: lsq_unit.cc:754
gem5::o3::LSQUnit::LSQEntry::_valid
bool _valid
Valid entry.
Definition: lsq_unit.hh:106
gem5::o3::LSQUnit::SQEntry::completed
const bool & completed() const
Definition: lsq_unit.hh:189
gem5::o3::LSQUnit::resetState
void resetState()
Reset the LSQ state.
Definition: lsq_unit.cc:227
gem5::o3::LSQUnit::SQEntry
Definition: lsq_unit.hh:150
gem5::o3::LSQUnit::LSQEntry::_request
LSQRequest * _request
The request.
Definition: lsq_unit.hh:102
gem5::o3::LSQUnit::SQEntry::canWB
const bool & canWB() const
Definition: lsq_unit.hh:187
debugfaults.hh
cpu.hh
gem5::o3::LSQUnit::getMemDepViolator
DynInstPtr getMemDepViolator()
Returns the memory ordering violator.
Definition: lsq_unit.cc:401
gem5::o3::LSQUnit::isEmpty
bool isEmpty() const
Returns if both the LQ and SQ are empty.
Definition: lsq_unit.hh:328
gem5::o3::LSQUnit::getStoreHeadSeqNum
InstSeqNum getStoreHeadSeqNum()
Returns the sequence number of the head store instruction.
Definition: lsq_unit.cc:1641
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::LSQUnit::loadQueue
LoadQueue loadQueue
The load queue.
Definition: lsq_unit.hh:453
gem5::o3::LSQUnit::name
std::string name() const
Returns the name of the LSQ unit.
Definition: lsq_unit.cc:246
lsq.hh
gem5::o3::LSQUnit::AddrRangeCoverage::NoAddrRangeCoverage
@ NoAddrRangeCoverage
gem5::o3::LSQUnit::AddrRangeCoverage
AddrRangeCoverage
Coverage of one address range with another.
Definition: lsq_unit.hh:201
gem5::o3::LSQUnit::dumpInsts
void dumpInsts() const
Debugging function to dump instructions in the LSQ.
Definition: lsq_unit.cc:1284
gem5::o3::LSQUnit::lqFull
bool lqFull()
Returns if the LQ is full.
Definition: lsq_unit.hh:331
gem5::o3::LSQUnit::SQEntry::data
const char * data() const
Definition: lsq_unit.hh:195
gem5::CircularQueue< LQEntry >
gem5::o3::LSQUnit::insertLoad
void insertLoad(const DynInstPtr &load_inst)
Inserts a load instruction.
Definition: lsq_unit.cc:320
gem5::o3::LSQUnit::cacheLineSize
unsigned int cacheLineSize()
Definition: lsq_unit.cc:1312
gem5::o3::LSQUnit::fromIssue
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: lsq_unit.hh:483
gem5::o3::LSQUnit::getLoadHeadSeqNum
InstSeqNum getLoadHeadSeqNum()
Returns the sequence number of the head load instruction.
Definition: lsq_unit.cc:1632
gem5::o3::LSQUnit::writebackStores
void writebackStores()
Writes back stores.
Definition: lsq_unit.cc:790
gem5::o3::LSQUnit::executeLoad
Fault executeLoad(int lq_idx)
Definition: lsq_unit.hh:266
gem5::o3::LSQUnit::lqEmpty
bool lqEmpty() const
Returns if the LQ is empty.
Definition: lsq_unit.hh:337
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::TimeBuffer::wire
Definition: timebuf.hh:59
gem5::o3::LSQUnit::checkSnoop
void checkSnoop(PacketPtr pkt)
Check if an incoming invalidate hits in the lsq on a load that might have issued out of order wrt ano...
Definition: lsq_unit.cc:428
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::LSQUnit::LSQUnitStats::LSQUnitStats
LSQUnitStats(statistics::Group *parent)
Definition: lsq_unit.cc:255
gem5::o3::LSQ::LSQRequest::freeLSQEntry
void freeLSQEntry()
The LSQ entry is cleared.
Definition: lsq.hh:509

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