gem5  v21.1.0.2
nativetrace.cc
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28 
29 #include "arch/x86/nativetrace.hh"
30 
31 #include "arch/x86/regs/float.hh"
32 #include "arch/x86/regs/int.hh"
33 #include "cpu/thread_context.hh"
34 #include "debug/ExecRegDelta.hh"
35 #include "params/X86NativeTrace.hh"
36 #include "sim/byteswap.hh"
37 
38 namespace gem5
39 {
40 
41 namespace Trace {
42 
43 void
45 {
46  parent->read(this, sizeof(*this));
47  rax = letoh(rax);
48  rcx = letoh(rcx);
49  rdx = letoh(rdx);
50  rbx = letoh(rbx);
51  rsp = letoh(rsp);
52  rbp = letoh(rbp);
53  rsi = letoh(rsi);
54  rdi = letoh(rdi);
55  r8 = letoh(r8);
56  r9 = letoh(r9);
57  r10 = letoh(r10);
58  r11 = letoh(r11);
59  r12 = letoh(r12);
60  r13 = letoh(r13);
61  r14 = letoh(r14);
62  r15 = letoh(r15);
63  rip = letoh(rip);
64  //This should be expanded if x87 registers are considered
65  for (int i = 0; i < 8; i++)
66  mmx[i] = letoh(mmx[i]);
67  for (int i = 0; i < 32; i++)
68  xmm[i] = letoh(xmm[i]);
69 }
70 
71 void
73 {
74  rax = tc->readIntReg(X86ISA::INTREG_RAX);
75  rcx = tc->readIntReg(X86ISA::INTREG_RCX);
76  rdx = tc->readIntReg(X86ISA::INTREG_RDX);
77  rbx = tc->readIntReg(X86ISA::INTREG_RBX);
78  rsp = tc->readIntReg(X86ISA::INTREG_RSP);
79  rbp = tc->readIntReg(X86ISA::INTREG_RBP);
80  rsi = tc->readIntReg(X86ISA::INTREG_RSI);
81  rdi = tc->readIntReg(X86ISA::INTREG_RDI);
82  r8 = tc->readIntReg(X86ISA::INTREG_R8);
83  r9 = tc->readIntReg(X86ISA::INTREG_R9);
84  r10 = tc->readIntReg(X86ISA::INTREG_R10);
85  r11 = tc->readIntReg(X86ISA::INTREG_R11);
86  r12 = tc->readIntReg(X86ISA::INTREG_R12);
87  r13 = tc->readIntReg(X86ISA::INTREG_R13);
88  r14 = tc->readIntReg(X86ISA::INTREG_R14);
89  r15 = tc->readIntReg(X86ISA::INTREG_R15);
90  rip = tc->pcState().npc();
91  //This should be expanded if x87 registers are considered
92  for (int i = 0; i < 8; i++)
93  mmx[i] = tc->readFloatReg(X86ISA::FLOATREG_MMX(i));
94  for (int i = 0; i < 32; i++)
96 }
97 
98 
100 {
101  checkRcx = true;
102  checkR11 = true;
103 }
104 
105 bool
106 X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
107 {
108  if (!checkRcx)
109  checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
110  if (checkRcx)
111  return checkReg(name, mVal, nVal);
112  return true;
113 }
114 
115 bool
116 X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
117 {
118  if (!checkR11)
119  checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
120  if (checkR11)
121  return checkReg(name, mVal, nVal);
122  return true;
123 }
124 
125 bool
126 X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
127 {
128  if (mXmmBuf[num * 2] != nXmmBuf[num * 2] ||
129  mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
130  DPRINTF(ExecRegDelta,
131  "Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
132  num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
133  mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
134  return false;
135  }
136  return true;
137 }
138 
139 void
141 {
142  nState.update(this);
143  mState.update(record->getThread());
144 
145  if (record->getStaticInst()->isSyscall())
146  {
147  checkRcx = false;
148  checkR11 = false;
149  oldRcxVal = mState.rcx;
151  oldR11Val = mState.r11;
153  }
154 
155  checkReg("rax", mState.rax, nState.rax);
156  checkRcxReg("rcx", mState.rcx, nState.rcx);
157  checkReg("rdx", mState.rdx, nState.rdx);
158  checkReg("rbx", mState.rbx, nState.rbx);
159  checkReg("rsp", mState.rsp, nState.rsp);
160  checkReg("rbp", mState.rbp, nState.rbp);
161  checkReg("rsi", mState.rsi, nState.rsi);
162  checkReg("rdi", mState.rdi, nState.rdi);
163  checkReg("r8", mState.r8, nState.r8);
164  checkReg("r9", mState.r9, nState.r9);
165  checkReg("r10", mState.r10, nState.r10);
166  checkR11Reg("r11", mState.r11, nState.r11);
167  checkReg("r12", mState.r12, nState.r12);
168  checkReg("r13", mState.r13, nState.r13);
169  checkReg("r14", mState.r14, nState.r14);
170  checkReg("r15", mState.r15, nState.r15);
171  checkReg("rip", mState.rip, nState.rip);
182  checkXMM(10, mState.xmm, nState.xmm);
183  checkXMM(11, mState.xmm, nState.xmm);
184  checkXMM(12, mState.xmm, nState.xmm);
185  checkXMM(13, mState.xmm, nState.xmm);
186  checkXMM(14, mState.xmm, nState.xmm);
187  checkXMM(15, mState.xmm, nState.xmm);
188 }
189 
190 } // namespace Trace
191 } // namespace gem5
nativetrace.hh
gem5::Trace::X86NativeTrace::ThreadState::rbp
uint64_t rbp
Definition: nativetrace.hh:57
gem5::Trace::ExeTracer::Params
ExeTracerParams Params
Definition: exetrace.hh:65
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::X86ISA::FLOATREG_MMX
static FloatRegIndex FLOATREG_MMX(int index)
Definition: float.hh:120
gem5::Trace::X86NativeTrace::ThreadState::mmx
uint64_t mmx[8]
Definition: nativetrace.hh:70
gem5::Trace::X86NativeTrace::ThreadState::rax
uint64_t rax
Definition: nativetrace.hh:52
gem5::Trace::X86NativeTrace::ThreadState::rsp
uint64_t rsp
Definition: nativetrace.hh:56
gem5::Trace::X86NativeTrace::oldRealRcxVal
uint64_t oldRealRcxVal
Definition: nativetrace.hh:48
gem5::Trace::NativeTrace::read
void read(void *ptr, size_t size)
Definition: nativetrace.hh:104
gem5::Trace::NativeTrace
Definition: nativetrace.hh:69
gem5::Trace::X86NativeTrace::ThreadState::rdi
uint64_t rdi
Definition: nativetrace.hh:59
gem5::Trace::InstRecord::getStaticInst
StaticInstPtr getStaticInst() const
Definition: insttracer.hh:237
gem5::Trace::X86NativeTrace::X86NativeTrace
X86NativeTrace(const Params &p)
Definition: nativetrace.cc:99
gem5::Trace::X86NativeTrace::oldRcxVal
uint64_t oldRcxVal
Definition: nativetrace.hh:47
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Trace::X86NativeTrace::oldR11Val
uint64_t oldR11Val
Definition: nativetrace.hh:47
gem5::Trace::X86NativeTrace::nState
ThreadState nState
Definition: nativetrace.hh:77
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::Trace::X86NativeTrace::ThreadState::r9
uint64_t r9
Definition: nativetrace.hh:61
gem5::Trace::X86NativeTrace::checkRcx
bool checkRcx
Definition: nativetrace.hh:45
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
int.hh
gem5::Trace::X86NativeTrace::ThreadState::rcx
uint64_t rcx
Definition: nativetrace.hh:53
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Trace::X86NativeTrace::ThreadState::update
void update(NativeTrace *parent)
Definition: nativetrace.cc:44
gem5::Trace::InstRecord::getThread
ThreadContext * getThread() const
Definition: insttracer.hh:236
gem5::Trace::X86NativeTrace::checkR11Reg
bool checkR11Reg(const char *regName, uint64_t &, uint64_t &)
Definition: nativetrace.cc:116
gem5::Trace::X86NativeTrace::ThreadState::r10
uint64_t r10
Definition: nativetrace.hh:62
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::Trace::X86NativeTrace::ThreadState::r8
uint64_t r8
Definition: nativetrace.hh:60
gem5::Trace::X86NativeTrace::ThreadState::r11
uint64_t r11
Definition: nativetrace.hh:63
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
name
const std::string & name()
Definition: trace.cc:49
gem5::Trace::X86NativeTrace::ThreadState::r12
uint64_t r12
Definition: nativetrace.hh:64
gem5::Trace::X86NativeTrace::ThreadState::rdx
uint64_t rdx
Definition: nativetrace.hh:54
gem5::Trace::X86NativeTrace::ThreadState::rbx
uint64_t rbx
Definition: nativetrace.hh:55
gem5::Trace::X86NativeTrace::ThreadState::r14
uint64_t r14
Definition: nativetrace.hh:66
gem5::Trace::X86NativeTrace::ThreadState::rsi
uint64_t rsi
Definition: nativetrace.hh:58
gem5::Trace::NativeTrace::checkReg
bool checkReg(const char *regName, T &val, T &realVal)
Definition: nativetrace.hh:92
gem5::Trace::X86NativeTrace::oldRealR11Val
uint64_t oldRealR11Val
Definition: nativetrace.hh:48
gem5::Trace::X86NativeTrace::ThreadState::xmm
uint64_t xmm[32]
Definition: nativetrace.hh:71
gem5::Trace::X86NativeTrace::checkR11
bool checkR11
Definition: nativetrace.hh:46
gem5::Trace::X86NativeTrace::checkRcxReg
bool checkRcxReg(const char *regName, uint64_t &, uint64_t &)
Definition: nativetrace.cc:106
gem5::Trace::X86NativeTrace::ThreadState::r15
uint64_t r15
Definition: nativetrace.hh:67
gem5::StaticInst::isSyscall
bool isSyscall() const
Definition: static_inst.hh:206
gem5::Trace::X86NativeTrace::check
void check(NativeTraceRecord *record)
Definition: nativetrace.cc:140
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Trace::X86NativeTrace::ThreadState::rip
uint64_t rip
Definition: nativetrace.hh:68
gem5::X86ISA::FLOATREG_XMM_BASE
@ FLOATREG_XMM_BASE
Definition: float.hh:72
gem5::Trace::X86NativeTrace::checkXMM
bool checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
Definition: nativetrace.cc:126
gem5::Trace::X86NativeTrace::mState
ThreadState mState
Definition: nativetrace.hh:78
thread_context.hh
float.hh
gem5::Trace::NativeTraceRecord
Definition: nativetrace.hh:51
byteswap.hh
gem5::Trace::X86NativeTrace::ThreadState::r13
uint64_t r13
Definition: nativetrace.hh:65

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