gem5  v21.2.1.1
nativetrace.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2007-2009 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "arch/x86/nativetrace.hh"
30 
31 #include "arch/x86/pcstate.hh"
32 #include "arch/x86/regs/float.hh"
33 #include "arch/x86/regs/int.hh"
34 #include "cpu/thread_context.hh"
35 #include "debug/ExecRegDelta.hh"
36 #include "params/X86NativeTrace.hh"
37 #include "sim/byteswap.hh"
38 
39 namespace gem5
40 {
41 
42 namespace Trace {
43 
44 void
46 {
47  parent->read(this, sizeof(*this));
48  rax = letoh(rax);
49  rcx = letoh(rcx);
50  rdx = letoh(rdx);
51  rbx = letoh(rbx);
52  rsp = letoh(rsp);
53  rbp = letoh(rbp);
54  rsi = letoh(rsi);
55  rdi = letoh(rdi);
56  r8 = letoh(r8);
57  r9 = letoh(r9);
58  r10 = letoh(r10);
59  r11 = letoh(r11);
60  r12 = letoh(r12);
61  r13 = letoh(r13);
62  r14 = letoh(r14);
63  r15 = letoh(r15);
64  rip = letoh(rip);
65  //This should be expanded if x87 registers are considered
66  for (int i = 0; i < 8; i++)
67  mmx[i] = letoh(mmx[i]);
68  for (int i = 0; i < 32; i++)
69  xmm[i] = letoh(xmm[i]);
70 }
71 
72 void
74 {
75  rax = tc->readIntReg(X86ISA::INTREG_RAX);
76  rcx = tc->readIntReg(X86ISA::INTREG_RCX);
77  rdx = tc->readIntReg(X86ISA::INTREG_RDX);
78  rbx = tc->readIntReg(X86ISA::INTREG_RBX);
79  rsp = tc->readIntReg(X86ISA::INTREG_RSP);
80  rbp = tc->readIntReg(X86ISA::INTREG_RBP);
81  rsi = tc->readIntReg(X86ISA::INTREG_RSI);
82  rdi = tc->readIntReg(X86ISA::INTREG_RDI);
83  r8 = tc->readIntReg(X86ISA::INTREG_R8);
84  r9 = tc->readIntReg(X86ISA::INTREG_R9);
85  r10 = tc->readIntReg(X86ISA::INTREG_R10);
86  r11 = tc->readIntReg(X86ISA::INTREG_R11);
87  r12 = tc->readIntReg(X86ISA::INTREG_R12);
88  r13 = tc->readIntReg(X86ISA::INTREG_R13);
89  r14 = tc->readIntReg(X86ISA::INTREG_R14);
90  r15 = tc->readIntReg(X86ISA::INTREG_R15);
91  rip = tc->pcState().as<X86ISA::PCState>().npc();
92  //This should be expanded if x87 registers are considered
93  for (int i = 0; i < 8; i++)
94  mmx[i] = tc->readFloatReg(X86ISA::FLOATREG_MMX(i));
95  for (int i = 0; i < 32; i++)
97 }
98 
99 
101 {
102  checkRcx = true;
103  checkR11 = true;
104 }
105 
106 bool
107 X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
108 {
109  if (!checkRcx)
110  checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
111  if (checkRcx)
112  return checkReg(name, mVal, nVal);
113  return true;
114 }
115 
116 bool
117 X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
118 {
119  if (!checkR11)
120  checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
121  if (checkR11)
122  return checkReg(name, mVal, nVal);
123  return true;
124 }
125 
126 bool
127 X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
128 {
129  if (mXmmBuf[num * 2] != nXmmBuf[num * 2] ||
130  mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
131  DPRINTF(ExecRegDelta,
132  "Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
133  num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
134  mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
135  return false;
136  }
137  return true;
138 }
139 
140 void
142 {
143  nState.update(this);
144  mState.update(record->getThread());
145 
146  if (record->getStaticInst()->isSyscall())
147  {
148  checkRcx = false;
149  checkR11 = false;
150  oldRcxVal = mState.rcx;
152  oldR11Val = mState.r11;
154  }
155 
156  checkReg("rax", mState.rax, nState.rax);
157  checkRcxReg("rcx", mState.rcx, nState.rcx);
158  checkReg("rdx", mState.rdx, nState.rdx);
159  checkReg("rbx", mState.rbx, nState.rbx);
160  checkReg("rsp", mState.rsp, nState.rsp);
161  checkReg("rbp", mState.rbp, nState.rbp);
162  checkReg("rsi", mState.rsi, nState.rsi);
163  checkReg("rdi", mState.rdi, nState.rdi);
164  checkReg("r8", mState.r8, nState.r8);
165  checkReg("r9", mState.r9, nState.r9);
166  checkReg("r10", mState.r10, nState.r10);
167  checkR11Reg("r11", mState.r11, nState.r11);
168  checkReg("r12", mState.r12, nState.r12);
169  checkReg("r13", mState.r13, nState.r13);
170  checkReg("r14", mState.r14, nState.r14);
171  checkReg("r15", mState.r15, nState.r15);
172  checkReg("rip", mState.rip, nState.rip);
183  checkXMM(10, mState.xmm, nState.xmm);
184  checkXMM(11, mState.xmm, nState.xmm);
185  checkXMM(12, mState.xmm, nState.xmm);
186  checkXMM(13, mState.xmm, nState.xmm);
187  checkXMM(14, mState.xmm, nState.xmm);
188  checkXMM(15, mState.xmm, nState.xmm);
189 }
190 
191 } // namespace Trace
192 } // namespace gem5
pcstate.hh
nativetrace.hh
gem5::Trace::X86NativeTrace::ThreadState::rbp
uint64_t rbp
Definition: nativetrace.hh:57
gem5::Trace::ExeTracer::Params
ExeTracerParams Params
Definition: exetrace.hh:65
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::X86ISA::FLOATREG_MMX
static FloatRegIndex FLOATREG_MMX(int index)
Definition: float.hh:120
gem5::Trace::X86NativeTrace::ThreadState::mmx
uint64_t mmx[8]
Definition: nativetrace.hh:70
gem5::Trace::X86NativeTrace::ThreadState::rax
uint64_t rax
Definition: nativetrace.hh:52
gem5::Trace::X86NativeTrace::ThreadState::rsp
uint64_t rsp
Definition: nativetrace.hh:56
gem5::Trace::X86NativeTrace::oldRealRcxVal
uint64_t oldRealRcxVal
Definition: nativetrace.hh:48
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::Trace::NativeTrace::read
void read(void *ptr, size_t size)
Definition: nativetrace.hh:104
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::Trace::NativeTrace
Definition: nativetrace.hh:69
gem5::Trace::X86NativeTrace::ThreadState::rdi
uint64_t rdi
Definition: nativetrace.hh:59
gem5::Trace::InstRecord::getStaticInst
StaticInstPtr getStaticInst() const
Definition: insttracer.hh:239
gem5::Trace::X86NativeTrace::X86NativeTrace
X86NativeTrace(const Params &p)
Definition: nativetrace.cc:100
gem5::Trace::X86NativeTrace::oldRcxVal
uint64_t oldRcxVal
Definition: nativetrace.hh:47
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Trace::X86NativeTrace::oldR11Val
uint64_t oldR11Val
Definition: nativetrace.hh:47
gem5::Trace::X86NativeTrace::nState
ThreadState nState
Definition: nativetrace.hh:77
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::Trace::X86NativeTrace::ThreadState::r9
uint64_t r9
Definition: nativetrace.hh:61
gem5::Trace::X86NativeTrace::checkRcx
bool checkRcx
Definition: nativetrace.hh:45
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
int.hh
gem5::Trace::X86NativeTrace::ThreadState::rcx
uint64_t rcx
Definition: nativetrace.hh:53
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Trace::X86NativeTrace::ThreadState::update
void update(NativeTrace *parent)
Definition: nativetrace.cc:45
gem5::Trace::InstRecord::getThread
ThreadContext * getThread() const
Definition: insttracer.hh:238
gem5::Trace::X86NativeTrace::checkR11Reg
bool checkR11Reg(const char *regName, uint64_t &, uint64_t &)
Definition: nativetrace.cc:117
gem5::Trace::X86NativeTrace::ThreadState::r10
uint64_t r10
Definition: nativetrace.hh:62
gem5::Trace::X86NativeTrace::ThreadState::r8
uint64_t r8
Definition: nativetrace.hh:60
gem5::Trace::X86NativeTrace::ThreadState::r11
uint64_t r11
Definition: nativetrace.hh:63
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
name
const std::string & name()
Definition: trace.cc:49
gem5::Trace::X86NativeTrace::ThreadState::r12
uint64_t r12
Definition: nativetrace.hh:64
gem5::Trace::X86NativeTrace::ThreadState::rdx
uint64_t rdx
Definition: nativetrace.hh:54
gem5::Trace::X86NativeTrace::ThreadState::rbx
uint64_t rbx
Definition: nativetrace.hh:55
gem5::Trace::X86NativeTrace::ThreadState::r14
uint64_t r14
Definition: nativetrace.hh:66
gem5::Trace::X86NativeTrace::ThreadState::rsi
uint64_t rsi
Definition: nativetrace.hh:58
gem5::Trace::NativeTrace::checkReg
bool checkReg(const char *regName, T &val, T &realVal)
Definition: nativetrace.hh:92
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::Trace::X86NativeTrace::oldRealR11Val
uint64_t oldRealR11Val
Definition: nativetrace.hh:48
gem5::Trace::X86NativeTrace::ThreadState::xmm
uint64_t xmm[32]
Definition: nativetrace.hh:71
gem5::Trace::X86NativeTrace::checkR11
bool checkR11
Definition: nativetrace.hh:46
gem5::Trace::X86NativeTrace::checkRcxReg
bool checkRcxReg(const char *regName, uint64_t &, uint64_t &)
Definition: nativetrace.cc:107
gem5::Trace::X86NativeTrace::ThreadState::r15
uint64_t r15
Definition: nativetrace.hh:67
gem5::StaticInst::isSyscall
bool isSyscall() const
Definition: static_inst.hh:205
gem5::Trace::X86NativeTrace::check
void check(NativeTraceRecord *record)
Definition: nativetrace.cc:141
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::Trace::X86NativeTrace::ThreadState::rip
uint64_t rip
Definition: nativetrace.hh:68
gem5::X86ISA::FLOATREG_XMM_BASE
@ FLOATREG_XMM_BASE
Definition: float.hh:72
gem5::Trace::X86NativeTrace::checkXMM
bool checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
Definition: nativetrace.cc:127
gem5::Trace::X86NativeTrace::mState
ThreadState mState
Definition: nativetrace.hh:78
thread_context.hh
float.hh
gem5::Trace::NativeTraceRecord
Definition: nativetrace.hh:51
byteswap.hh
gem5::Trace::X86NativeTrace::ThreadState::r13
uint64_t r13
Definition: nativetrace.hh:65

Generated on Wed May 4 2022 12:13:48 for gem5 by doxygen 1.8.17