gem5 v24.0.0.0
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stage2_lookup.hh
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1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
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23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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36 */
37
38#ifndef __ARCH_ARM_STAGE2_LOOKUP_HH__
39#define __ARCH_ARM_STAGE2_LOOKUP_HH__
40
41#include <list>
42
43#include "arch/arm/system.hh"
45#include "arch/arm/tlb.hh"
46#include "arch/generic/mmu.hh"
47#include "mem/request.hh"
48
49namespace gem5
50{
51
52class ThreadContext;
53
54namespace ArmISA {
55class Translation;
56class TLB;
57
58
60{
61 private:
67 bool timing;
75 bool secure;
76
77 public:
78 Stage2LookUp(MMU *_mmu, TlbEntry s1_te, const RequestPtr &_req,
79 MMU::Translation *_transState, BaseMMU::Mode _mode, bool _timing,
80 bool _functional, bool _secure, MMU::ArmTranslationType _tranType) :
81 mmu(_mmu), stage1Te(s1_te), s1Req(_req),
82 transState(_transState), mode(_mode), timing(_timing),
83 functional(_functional), tranType(_tranType), stage2Te(nullptr),
84 fault(NoFault), complete(false), selfDelete(false), secure(_secure)
85 {
86 req = std::make_shared<Request>();
87 req->setVirt(s1_te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
88 s1Req->getFlags(), s1Req->requestorId(), 0);
89 }
90
91 Fault getTe(ThreadContext *tc, TlbEntry *destTe);
92
94
95 void setSelfDelete() { selfDelete = true; }
96
97 bool isComplete() const { return complete; }
98
99 void markDelayed() {}
100
101 void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
103};
104
105} // namespace ArmISA
106} // namespace gem5
107
108#endif //__ARCH_ARM_STAGE2_LOOKUP_HH__
BaseMMU::Translation * transState
void mergeTe(BaseMMU::Mode mode)
void markDelayed()
Signal that the translation has been delayed due to a hw page table walk.
Stage2LookUp(MMU *_mmu, TlbEntry s1_te, const RequestPtr &_req, MMU::Translation *_transState, BaseMMU::Mode _mode, bool _timing, bool _functional, bool _secure, MMU::ArmTranslationType _tranType)
MMU::ArmTranslationType tranType
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Fault getTe(ThreadContext *tc, TlbEntry *destTe)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
constexpr decltype(nullptr) NoFault
Definition types.hh:253
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Addr pAddr(Addr va) const
Definition pagetable.hh:351

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