gem5  v21.1.0.2
stage2_lookup.cc
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37 
39 
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/system.hh"
42 #include "arch/arm/table_walker.hh"
43 #include "arch/arm/tlb.hh"
44 #include "cpu/base.hh"
45 #include "cpu/thread_context.hh"
46 #include "debug/Checkpoint.hh"
47 #include "debug/TLB.hh"
48 #include "debug/TLBVerbose.hh"
49 #include "sim/system.hh"
50 
51 namespace gem5
52 {
53 
54 using namespace ArmISA;
55 
56 Fault
58 
59 {
60  fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
62  // Call finish if we're done already
63  if ((fault != NoFault) || (stage2Te != NULL)) {
64  // Since we directly requested the table entry (which we need later on
65  // to merge the attributes) then we've skipped some stage2 permissions
66  // checking. So call translate on stage 2 to do the checking. As the
67  // entry is now in the TLB this should always hit the cache.
68  if (fault == NoFault) {
69  if (ELIs64(tc, EL2))
71  else
73  }
74 
75  mergeTe(req, mode);
76  *destTe = stage1Te;
77  }
78  return fault;
79 }
80 
81 void
83 {
84  // Check again that we haven't got a fault
85  if (fault == NoFault) {
86  assert(stage2Te != NULL);
87 
88  // Now we have the table entries for both stages of translation
89  // merge them and insert the result into the stage 1 TLB. See
90  // CombineS1S2Desc() in pseudocode
92  stage1Te.xn |= stage2Te->xn;
93 
94  if (stage1Te.size > stage2Te->size) {
95  // Size mismatch also implies vpn mismatch (this is shifted by
96  // sizebits!).
97  stage1Te.vpn = s1Req->getVaddr() >> stage2Te->N;
100  stage1Te.N = stage2Te->N;
101  } else if (stage1Te.size < stage2Te->size) {
102  // Guest 4K could well be section-backed by host hugepage! In this
103  // case a 4K entry is added but pfn needs to be adjusted. New PFN =
104  // offset into section PFN given by stage2 IPA treated as a stage1
105  // page size.
106  const Addr pa = (stage2Te->pfn << stage2Te->N);
107  const Addr ipa = (stage1Te.pfn << stage1Te.N);
108  stage1Te.pfn = (pa | (ipa & mask(stage2Te->N))) >> stage1Te.N;
109  // Size remains smaller of the two.
110  } else {
111  // Matching sizes
113  }
114 
121  } else {
123  }
124 
126 
127  if (stage2Te->innerAttrs == 0 ||
128  stage1Te.innerAttrs == 0) {
129  // either encoding Non-cacheable
130  stage1Te.innerAttrs = 0;
131  } else if (stage2Te->innerAttrs == 2 ||
132  stage1Te.innerAttrs == 2) {
133  // either encoding Write-Through cacheable
134  stage1Te.innerAttrs = 2;
135  } else {
136  // both encodings Write-Back
137  stage1Te.innerAttrs = 3;
138  }
139 
140  if (stage2Te->outerAttrs == 0 ||
141  stage1Te.outerAttrs == 0) {
142  // either encoding Non-cacheable
143  stage1Te.outerAttrs = 0;
144  } else if (stage2Te->outerAttrs == 2 ||
145  stage1Te.outerAttrs == 2) {
146  // either encoding Write-Through cacheable
147  stage1Te.outerAttrs = 2;
148  } else {
149  // both encodings Write-Back
150  stage1Te.outerAttrs = 3;
151  }
152 
155  if (stage1Te.innerAttrs == 0 &&
156  stage1Te.outerAttrs == 0) {
157  // something Non-cacheable at each level is outer shareable
158  stage1Te.shareable = true;
159  stage1Te.outerShareable = true;
160  }
161  } else {
162  stage1Te.shareable = true;
163  stage1Te.outerShareable = true;
164  }
166  }
167 
168  // if there's a fault annotate it,
169  if (fault != NoFault) {
170  // If the second stage of translation generated a fault add the
171  // details of the original stage 1 virtual address
172  reinterpret_cast<ArmFault *>(fault.get())->annotate(ArmFault::OVA,
173  s1Req->getVaddr());
174  }
175  complete = true;
176 }
177 
178 void
179 Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req,
181 {
182  fault = _fault;
183  // if we haven't got the table entry get it now
184  if ((fault == NoFault) && (stage2Te == NULL)) {
185  fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
187  }
188 
189  // Now we have the stage 2 table entry we need to merge it with the stage
190  // 1 entry we were given at the start
191  mergeTe(req, mode);
192 
193  if (fault != NoFault) {
194  // Returning with a fault requires the original request
195  transState->finish(fault, s1Req, tc, mode);
196  } else if (timing) {
197  // Now notify the original stage 1 translation that we finally have
198  // a result
200  }
201  // if we have been asked to delete ourselfs do it now
202  if (selfDelete) {
203  delete this;
204  }
205 }
206 
207 } // namespace gem5
gem5::ArmISA::Stage2LookUp::selfDelete
bool selfDelete
Definition: stage2_lookup.hh:75
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::Stage2LookUp::stage2Tlb
TLB * stage2Tlb
Definition: stage2_lookup.hh:63
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:282
system.hh
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::TlbEntry::outerAttrs
uint8_t outerAttrs
Definition: pagetable.hh:119
gem5::ArmISA::TlbEntry::pfn
Addr pfn
Definition: pagetable.hh:105
gem5::ArmISA::Stage2LookUp::stage1Te
TlbEntry stage1Te
Definition: stage2_lookup.hh:64
gem5::ArmISA::Stage2LookUp::mergeTe
void mergeTe(const RequestPtr &req, BaseMMU::Mode mode)
Definition: stage2_lookup.cc:82
gem5::ArmISA::Stage2LookUp::stage1Tlb
TLB * stage1Tlb
Definition: stage2_lookup.hh:62
gem5::ArmISA::Stage2LookUp::stage2Te
TlbEntry * stage2Te
Definition: stage2_lookup.hh:71
gem5::ArmISA::TLB::checkPermissions
Fault checkPermissions(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode)
Definition: tlb.cc:581
gem5::ArmISA::Stage2LookUp::complete
bool complete
Definition: stage2_lookup.hh:74
tlb.hh
gem5::ArmISA::TlbEntry::MemoryType::Normal
@ Normal
system.hh
table_walker.hh
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:86
gem5::ArmISA::TlbEntry::size
Addr size
Definition: pagetable.hh:106
gem5::ArmISA::pa
Bitfield< 39, 12 > pa
Definition: misc_types.hh:656
gem5::ArmISA::TlbEntry::MemoryType::Device
@ Device
gem5::ArmISA::Stage2LookUp::req
RequestPtr req
Definition: stage2_lookup.hh:72
gem5::ArmISA::TlbEntry::shareable
bool shareable
Definition: pagetable.hh:144
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::Stage2LookUp::secure
bool secure
Definition: stage2_lookup.hh:76
gem5::ArmISA::TlbEntry::mtype
MemoryType mtype
Definition: pagetable.hh:124
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
stage2_lookup.hh
gem5::ArmISA::TlbEntry::N
uint8_t N
Definition: pagetable.hh:117
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
faults.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TlbEntry::vpn
Addr vpn
Definition: pagetable.hh:107
gem5::ArmISA::TLB::checkPermissions64
Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode, ThreadContext *tc)
Definition: tlb.cc:759
gem5::ArmISA::TlbEntry::outerShareable
bool outerShareable
Definition: pagetable.hh:145
gem5::ArmISA::Stage2LookUp::transState
BaseMMU::Translation * transState
Definition: stage2_lookup.hh:66
gem5::ArmISA::Stage2LookUp::tranType
TLB::ArmTranslationType tranType
Definition: stage2_lookup.hh:70
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::Stage2LookUp::getTe
Fault getTe(ThreadContext *tc, TlbEntry *destTe)
Definition: stage2_lookup.cc:57
gem5::ArmISA::TlbEntry::MemoryType::StronglyOrdered
@ StronglyOrdered
gem5::ArmISA::Stage2LookUp::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: stage2_lookup.cc:179
base.hh
gem5::ArmISA::TlbEntry::xn
bool xn
Definition: pagetable.hh:148
gem5::ArmISA::Stage2LookUp::fault
Fault fault
Definition: stage2_lookup.hh:73
gem5::ArmISA::Stage2LookUp::timing
bool timing
Definition: stage2_lookup.hh:68
gem5::ArmISA::Stage2LookUp::s1Req
RequestPtr s1Req
Definition: stage2_lookup.hh:65
gem5::ArmISA::TlbEntry::updateAttributes
void updateAttributes()
Definition: pagetable.hh:249
gem5::ArmISA::Stage2LookUp::functional
bool functional
Definition: stage2_lookup.hh:69
gem5::ArmISA::TlbEntry::nonCacheable
bool nonCacheable
Definition: pagetable.hh:141
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseMMU::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
gem5::ArmISA::TLB::translateComplete
Fault translateComplete(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType, bool callFromS2)
Definition: tlb.cc:1316
gem5::ArmISA::Stage2LookUp::mode
BaseMMU::Mode mode
Definition: stage2_lookup.hh:67
thread_context.hh
gem5::ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:135
gem5::ArmISA::TlbEntry::innerAttrs
uint8_t innerAttrs
Definition: pagetable.hh:118
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ArmISA::TLB::getTE
Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType)
Definition: tlb.cc:1586

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