gem5  v21.2.1.1
macromem.hh
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40 
41 #ifndef __ARCH_ARM_MACROMEM_HH__
42 #define __ARCH_ARM_MACROMEM_HH__
43 
45 #include "arch/arm/pcstate.hh"
46 #include "arch/arm/tlb.hh"
47 #include "cpu/thread_context.hh"
48 
49 namespace gem5
50 {
51 
52 namespace ArmISA
53 {
54 
55 static inline unsigned int
57 {
58  uint32_t ones = 0;
59  for (int i = 0; i < 32; i++ )
60  {
61  if ( val & (1<<i) )
62  ones++;
63  }
64  return ones;
65 }
66 
70 class MicroOp : public PredOp
71 {
72  protected:
73  MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
74  : PredOp(mnem, machInst, __opClass)
75  {
76  }
77 
78  public:
79  void
80  advancePC(PCStateBase &pcState) const override
81  {
82  auto &apc = pcState.as<PCState>();
83  if (flags[IsLastMicroop]) {
84  apc.uEnd();
85  } else if (flags[IsMicroop]) {
86  apc.uAdvance();
87  } else {
88  apc.advance();
89  }
90  }
91 
92  void
93  advancePC(ThreadContext *tc) const override
94  {
95  PCState pc = tc->pcState().as<PCState>();
96  if (flags[IsLastMicroop]) {
97  pc.uEnd();
98  } else if (flags[IsMicroop]) {
99  pc.uAdvance();
100  } else {
101  pc.advance();
102  }
103  tc->pcState(pc);
104  }
105 };
106 
107 class MicroOpX : public ArmStaticInst
108 {
109  protected:
110  MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
111  : ArmStaticInst(mnem, machInst, __opClass)
112  {}
113 
114  public:
115  void
116  advancePC(PCStateBase &pcState) const override
117  {
118  auto &apc = pcState.as<PCState>();
119  if (flags[IsLastMicroop]) {
120  apc.uEnd();
121  } else if (flags[IsMicroop]) {
122  apc.uAdvance();
123  } else {
124  apc.advance();
125  }
126  }
127 
128  void
129  advancePC(ThreadContext *tc) const override
130  {
131  PCState pc = tc->pcState().as<PCState>();
132  if (flags[IsLastMicroop]) {
133  pc.uEnd();
134  } else if (flags[IsMicroop]) {
135  pc.uAdvance();
136  } else {
137  pc.advance();
138  }
139  tc->pcState(pc);
140  }
141 };
142 
146 class MicroNeonMemOp : public MicroOp
147 {
148  protected:
150  uint32_t imm;
151  unsigned memAccessFlags;
152 
153  MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
154  RegIndex _dest, RegIndex _ura, uint32_t _imm)
155  : MicroOp(mnem, machInst, __opClass),
156  dest(_dest), ura(_ura), imm(_imm), memAccessFlags()
157  {
158  }
159 };
160 
164 class MicroNeonMixOp : public MicroOp
165 {
166  protected:
168  uint32_t step;
169 
170  MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
171  RegIndex _dest, RegIndex _op1, uint32_t _step)
172  : MicroOp(mnem, machInst, __opClass),
173  dest(_dest), op1(_op1), step(_step)
174  {
175  }
176 };
177 
179 {
180  protected:
181  unsigned lane;
182 
184  OpClass __opClass, RegIndex _dest, RegIndex _op1,
185  uint32_t _step, unsigned _lane)
186  : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
187  lane(_lane)
188  {
189  }
190 };
191 
195 class MicroNeonMixOp64 : public MicroOp
196 {
197  protected:
200 
201  MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
202  RegIndex _dest, RegIndex _op1, uint8_t _eSize,
203  uint8_t _dataSize, uint8_t _numStructElems,
204  uint8_t _numRegs, uint8_t _step)
205  : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
206  eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
207  numRegs(_numRegs), step(_step)
208  {
209  }
210 };
211 
213 {
214  protected:
217  bool replicate;
218 
220  OpClass __opClass, RegIndex _dest, RegIndex _op1,
221  uint8_t _eSize, uint8_t _dataSize,
222  uint8_t _numStructElems, uint8_t _lane, uint8_t _step,
223  bool _replicate = false)
224  : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
225  eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
226  lane(_lane), step(_step), replicate(_replicate)
227  {
228  }
229 };
230 
234 class VldMultOp64 : public PredMacroOp
235 {
236  protected:
238  bool wb;
239 
240  VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
241  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
242  uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
243  bool wb);
244 };
245 
246 class VstMultOp64 : public PredMacroOp
247 {
248  protected:
250  bool wb;
251 
252  VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
253  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
254  uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
255  bool wb);
256 };
257 
259 {
260  protected:
262  bool wb, replicate;
263 
264  VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
265  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
266  uint8_t dataSize, uint8_t numStructElems, uint8_t index,
267  bool wb, bool replicate = false);
268 };
269 
271 {
272  protected:
274  bool wb, replicate;
275 
276  VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
277  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
278  uint8_t dataSize, uint8_t numStructElems, uint8_t index,
279  bool wb, bool replicate = false);
280 };
281 
287 class MicroSetPCCPSR : public MicroOp
288 {
289  protected:
290  IntRegIndex ura, urb, urc;
291 
292  MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
293  IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
294  : MicroOp(mnem, machInst, __opClass),
295  ura(_ura), urb(_urb), urc(_urc)
296  {
297  }
298 
299  std::string generateDisassembly(
300  Addr pc, const loader::SymbolTable *symtab) const override;
301 };
302 
306 class MicroIntMov : public MicroOp
307 {
308  protected:
310 
311  MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
312  RegIndex _ura, RegIndex _urb)
313  : MicroOp(mnem, machInst, __opClass),
314  ura(_ura), urb(_urb)
315  {
316  }
317 
318  std::string generateDisassembly(
319  Addr pc, const loader::SymbolTable *symtab) const override;
320 };
321 
325 class MicroIntImmOp : public MicroOp
326 {
327  protected:
329  int32_t imm;
330 
331  MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
332  RegIndex _ura, RegIndex _urb, int32_t _imm)
333  : MicroOp(mnem, machInst, __opClass),
334  ura(_ura), urb(_urb), imm(_imm)
335  {
336  }
337 
338  std::string generateDisassembly(
339  Addr pc, const loader::SymbolTable *symtab) const override;
340 };
341 
342 class MicroIntImmXOp : public MicroOpX
343 {
344  protected:
346  int64_t imm;
347 
348  MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
349  RegIndex _ura, RegIndex _urb, int64_t _imm)
350  : MicroOpX(mnem, machInst, __opClass),
351  ura(_ura), urb(_urb), imm(_imm)
352  {
353  }
354 
355  std::string generateDisassembly(
356  Addr pc, const loader::SymbolTable *symtab) const override;
357 };
358 
362 class MicroIntOp : public MicroOp
363 {
364  protected:
366 
367  MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
368  RegIndex _ura, RegIndex _urb, RegIndex _urc)
369  : MicroOp(mnem, machInst, __opClass),
370  ura(_ura), urb(_urb), urc(_urc)
371  {
372  }
373 
374  std::string generateDisassembly(
375  Addr pc, const loader::SymbolTable *symtab) const override;
376 };
377 
378 class MicroIntRegXOp : public MicroOp
379 {
380  protected:
383  uint32_t shiftAmt;
384 
385  MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
386  RegIndex _ura, RegIndex _urb, RegIndex _urc,
387  ArmExtendType _type, uint32_t _shiftAmt)
388  : MicroOp(mnem, machInst, __opClass),
389  ura(_ura), urb(_urb), urc(_urc),
390  type(_type), shiftAmt(_shiftAmt)
391  {
392  }
393 
394  std::string generateDisassembly(
395  Addr pc, const loader::SymbolTable *symtab) const override;
396 };
397 
401 class MicroIntRegOp : public MicroOp
402 {
403  protected:
405  int32_t shiftAmt;
406  ArmShiftType shiftType;
407 
408  MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
409  RegIndex _ura, RegIndex _urb, RegIndex _urc,
410  int32_t _shiftAmt, ArmShiftType _shiftType)
411  : MicroOp(mnem, machInst, __opClass),
412  ura(_ura), urb(_urb), urc(_urc),
413  shiftAmt(_shiftAmt), shiftType(_shiftType)
414  {
415  }
416 };
417 
421 class MicroMemOp : public MicroIntImmOp
422 {
423  protected:
424  bool up;
425  unsigned memAccessFlags;
426 
427  MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
428  RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
429  : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
430  up(_up), memAccessFlags(MMU::AlignWord)
431  {
432  }
433 
434  std::string generateDisassembly(
435  Addr pc, const loader::SymbolTable *symtab) const override;
436 };
437 
438 class MicroMemPairOp : public MicroOp
439 {
440  protected:
442  bool up;
443  int32_t imm;
444  unsigned memAccessFlags;
445 
446  MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
447  RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
448  bool _up, uint8_t _imm)
449  : MicroOp(mnem, machInst, __opClass),
450  dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
451  memAccessFlags(MMU::AlignWord)
452  {
453  }
454 
455  std::string generateDisassembly(
456  Addr pc, const loader::SymbolTable *symtab) const override;
457 };
458 
462 class MacroMemOp : public PredMacroOp
463 {
464  protected:
465  MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
466  IntRegIndex rn, bool index, bool up, bool user,
467  bool writeback, bool load, uint32_t reglist);
468 };
469 
473 class PairMemOp : public PredMacroOp
474 {
475  public:
476  enum AddrMode
477  {
481  };
482 
483  protected:
484  PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
485  uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
486  bool exclusive, bool acrel, int64_t imm, AddrMode mode,
487  IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
488 };
489 
491 {
492  protected:
493  BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
494  bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
495 };
496 
498 {
499  protected:
500  BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
501  bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
502 };
503 
505 {
506  protected:
507  BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
508  bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
509 };
510 
512 {
513  protected:
514  BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
515  bool load, IntRegIndex dest, IntRegIndex base,
516  IntRegIndex offset, ArmExtendType type, int64_t imm);
517 };
518 
520 {
521  protected:
522  BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
523  IntRegIndex dest, int64_t imm);
524 };
525 
529 class VldMultOp : public PredMacroOp
530 {
531  protected:
532  VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
533  unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
534  unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
535 };
536 
537 class VldSingleOp : public PredMacroOp
538 {
539  protected:
540  VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
541  bool all, unsigned elems, RegIndex rn, RegIndex vd,
542  unsigned regs, unsigned inc, uint32_t size,
543  uint32_t align, RegIndex rm, unsigned lane);
544 };
545 
549 class VstMultOp : public PredMacroOp
550 {
551  protected:
552  VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
553  unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
554  unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
555 };
556 
557 class VstSingleOp : public PredMacroOp
558 {
559  protected:
560  VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
561  bool all, unsigned elems, RegIndex rn, RegIndex vd,
562  unsigned regs, unsigned inc, uint32_t size,
563  uint32_t align, RegIndex rm, unsigned lane);
564 };
565 
570 {
571  protected:
572  MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
573  IntRegIndex rn, RegIndex vd, bool single, bool up,
574  bool writeback, bool load, uint32_t offset);
575 };
576 
577 } // namespace ArmISA
578 } // namespace gem5
579 
580 #endif //__ARCH_ARM_INSTS_MACROMEM_HH__
gem5::ArmISA::VldMultOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:237
gem5::ArmISA::MicroMemPairOp::MicroMemPairOp
MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, bool _up, uint8_t _imm)
Definition: macromem.hh:446
gem5::ArmISA::VldSingleOp64::VldSingleOp64
VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate=false)
Definition: macromem.cc:1291
gem5::ArmISA::MicroIntOp::ura
RegIndex ura
Definition: macromem.hh:365
gem5::ArmISA::number_of_ones
static unsigned int number_of_ones(int32_t val)
Definition: macromem.hh:56
gem5::ArmISA::MicroNeonMixLaneOp64::op1
RegIndex op1
Definition: macromem.hh:215
gem5::ArmISA::BigFpMemLitOp::BigFpMemLitOp
BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex dest, int64_t imm)
Definition: macromem.cc:447
gem5::ArmISA::MicroNeonMixOp
Microops for Neon load/store (de)interleaving.
Definition: macromem.hh:164
gem5::ArmISA::VldSingleOp64
Definition: macromem.hh:258
gem5::ArmISA::MicroIntImmOp::ura
RegIndex ura
Definition: macromem.hh:328
gem5::ArmISA::VstMultOp64::eSize
uint8_t eSize
Definition: macromem.hh:249
gem5::ArmISA::VldSingleOp64::replicate
bool replicate
Definition: macromem.hh:262
gem5::ArmISA::MicroIntMov
Microops of the form IntRegA = IntRegB.
Definition: macromem.hh:306
gem5::ArmISA::VstSingleOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:273
gem5::ArmISA::BigFpMemPostOp
Definition: macromem.hh:497
gem5::ArmISA::MicroNeonMixOp::op1
RegIndex op1
Definition: macromem.hh:167
gem5::ArmISA::MicroIntImmOp
Microops of the form IntRegA = IntRegB op Imm.
Definition: macromem.hh:325
gem5::ArmISA::MicroNeonMixOp64::eSize
uint8_t eSize
Definition: macromem.hh:199
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp
BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
Definition: macromem.cc:369
gem5::ArmISA::MicroIntRegXOp::urb
RegIndex urb
Definition: macromem.hh:381
gem5::ArmISA::MicroIntRegOp::ura
RegIndex ura
Definition: macromem.hh:404
gem5::ArmISA::MicroNeonMixLaneOp64::step
uint8_t step
Definition: macromem.hh:216
gem5::ArmISA::MicroNeonMixOp::step
uint32_t step
Definition: macromem.hh:168
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::MicroNeonMixOp64::numRegs
uint8_t numRegs
Definition: macromem.hh:199
gem5::ArmISA::up
Bitfield< 23 > up
Definition: types.hh:124
gem5::ArmISA::writeback
Bitfield< 21 > writeback
Definition: types.hh:126
gem5::ArmISA::VstMultOp
Base class for microcoded integer memory instructions.
Definition: macromem.hh:549
gem5::ArmISA::MicroNeonMemOp::imm
uint32_t imm
Definition: macromem.hh:150
gem5::ArmISA::MicroNeonMixOp64::op1
RegIndex op1
Definition: macromem.hh:198
gem5::ArmISA::MicroIntRegOp::urc
RegIndex urc
Definition: macromem.hh:404
gem5::ArmISA::MicroSetPCCPSR::ura
IntRegIndex ura
Definition: macromem.hh:290
gem5::ArmISA::MicroOp
Base class for Memory microops.
Definition: macromem.hh:70
gem5::ArmISA::MicroNeonMixLaneOp::lane
unsigned lane
Definition: macromem.hh:181
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::MacroMemOp
Base class for microcoded integer memory instructions.
Definition: macromem.hh:462
gem5::ArmISA::MicroOpX
Definition: macromem.hh:107
gem5::ArmISA::MicroMemOp
Memory microops which use IntReg + Imm addressing.
Definition: macromem.hh:421
gem5::ArmISA::MicroIntImmOp::MicroIntImmOp
MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, int32_t _imm)
Definition: macromem.hh:331
gem5::ArmISA::PairMemOp::AddrMd_PreIndex
@ AddrMd_PreIndex
Definition: macromem.hh:479
gem5::ArmISA::VldMultOp64::numRegs
uint8_t numRegs
Definition: macromem.hh:237
gem5::ArmISA::MicroIntRegOp::shiftType
ArmShiftType shiftType
Definition: macromem.hh:406
gem5::ArmISA::MicroNeonMixLaneOp::MicroNeonMixLaneOp
MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint32_t _step, unsigned _lane)
Definition: macromem.hh:183
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::MicroIntImmOp::urb
RegIndex urb
Definition: macromem.hh:328
gem5::ArmISA::MicroIntRegXOp::urc
RegIndex urc
Definition: macromem.hh:381
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:215
gem5::ArmISA::PairMemOp::AddrMode
AddrMode
Definition: macromem.hh:476
gem5::ArmISA::MicroOpX::MicroOpX
MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
Definition: macromem.hh:110
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::VldMultOp64::wb
bool wb
Definition: macromem.hh:238
gem5::ArmISA::MicroNeonMixOp64::MicroNeonMixOp64
MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, uint8_t _numRegs, uint8_t _step)
Definition: macromem.hh:201
gem5::ArmISA::MicroMemPairOp::up
bool up
Definition: macromem.hh:442
gem5::ArmISA::MicroSetPCCPSR::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1545
tlb.hh
gem5::ArmISA::VstSingleOp
Definition: macromem.hh:557
gem5::ArmISA::MicroNeonMixLaneOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:216
gem5::ArmISA::MicroMemPairOp::urb
RegIndex urb
Definition: macromem.hh:441
gem5::ArmISA::VstMultOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:249
gem5::ArmISA::MicroOp::advancePC
void advancePC(ThreadContext *tc) const override
Definition: macromem.hh:93
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::MicroMemPairOp::dest
RegIndex dest
Definition: macromem.hh:441
gem5::ArmISA::MicroNeonMixOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:199
gem5::ArmISA::MicroMemPairOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1612
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::fp
Bitfield< 19, 16 > fp
Definition: misc_types.hh:177
gem5::ArmISA::VstMultOp::VstMultOp
VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned width, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm)
Definition: macromem.cc:823
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::MicroIntRegXOp::shiftAmt
uint32_t shiftAmt
Definition: macromem.hh:383
gem5::ArmISA::VstMultOp64
Definition: macromem.hh:246
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:151
gem5::ArmISA::MicroIntRegXOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1555
gem5::ArmISA::MicroNeonMixOp64
Microops for AArch64 NEON load/store (de)interleaving.
Definition: macromem.hh:195
gem5::ArmISA::VldSingleOp64::wb
bool wb
Definition: macromem.hh:262
gem5::ArmISA::MicroNeonMemOp::MicroNeonMemOp
MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _ura, uint32_t _imm)
Definition: macromem.hh:153
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
sc_dt::inc
void inc(scfx_mant &mant)
Definition: scfx_mant.hh:341
gem5::ArmISA::BigFpMemLitOp
Definition: macromem.hh:519
gem5::ArmISA::MicroIntRegOp
Microops of the form IntRegA = IntRegB op shifted IntRegC.
Definition: macromem.hh:401
gem5::ArmISA::MicroIntImmXOp::ura
RegIndex ura
Definition: macromem.hh:345
gem5::ArmISA::VstSingleOp::VstSingleOp
VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
Definition: macromem.cc:918
gem5::ArmISA::MicroIntRegXOp::MicroIntRegXOp
MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc, ArmExtendType _type, uint32_t _shiftAmt)
Definition: macromem.hh:385
gem5::ArmISA::VstSingleOp64::VstSingleOp64
VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate=false)
Definition: macromem.cc:1365
gem5::ArmISA::VstSingleOp64::wb
bool wb
Definition: macromem.hh:274
gem5::ArmISA::MicroIntRegOp::MicroIntRegOp
MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc, int32_t _shiftAmt, ArmShiftType _shiftType)
Definition: macromem.hh:408
gem5::ArmISA::MicroMemPairOp::imm
int32_t imm
Definition: macromem.hh:443
gem5::ArmISA::MicroOpX::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: macromem.hh:116
gem5::ArmISA::MicroIntImmXOp::MicroIntImmXOp
MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, int64_t _imm)
Definition: macromem.hh:348
gem5::ArmISA::MicroIntImmXOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1531
gem5::ArmISA::MicroIntRegXOp::ura
RegIndex ura
Definition: macromem.hh:381
gem5::ArmISA::MacroMemOp::MacroMemOp
MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, bool index, bool up, bool user, bool writeback, bool load, uint32_t reglist)
Definition: macromem.cc:57
gem5::ArmISA::MicroIntRegXOp
Definition: macromem.hh:378
gem5::ArmISA::MicroNeonMemOp::ura
RegIndex ura
Definition: macromem.hh:149
gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp
BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
Definition: macromem.cc:348
gem5::ArmISA::BigFpMemPreOp
Definition: macromem.hh:504
gem5::ArmISA::MicroNeonMixLaneOp64::lane
uint8_t lane
Definition: macromem.hh:216
gem5::ArmISA::MicroNeonMixOp::dest
RegIndex dest
Definition: macromem.hh:167
gem5::ArmISA::MicroIntOp
Microops of the form IntRegA = IntRegB op IntRegC.
Definition: macromem.hh:362
gem5::ArmISA::MicroNeonMixLaneOp64::MicroNeonMixLaneOp64
MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, uint8_t _lane, uint8_t _step, bool _replicate=false)
Definition: macromem.hh:219
gem5::ArmISA::BigFpMemImmOp
Definition: macromem.hh:490
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MicroIntMov::urb
RegIndex urb
Definition: macromem.hh:309
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:72
gem5::ArmISA::MicroIntRegOp::urb
RegIndex urb
Definition: macromem.hh:404
gem5::ArmISA::MicroMemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1594
gem5::ArmISA::VstSingleOp64::eSize
uint8_t eSize
Definition: macromem.hh:273
gem5::ArmISA::MicroSetPCCPSR
Microops of the form PC = IntRegA CPSR = IntRegB.
Definition: macromem.hh:287
gem5::ArmISA::MicroIntImmXOp::imm
int64_t imm
Definition: macromem.hh:346
gem5::ArmISA::MicroOp::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: macromem.hh:80
gem5::ArmISA::MicroMemPairOp
Definition: macromem.hh:438
gem5::ArmISA::VstSingleOp64::index
uint8_t index
Definition: macromem.hh:273
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::MicroNeonMemOp::dest
RegIndex dest
Definition: macromem.hh:149
gem5::ArmISA::rm
Bitfield< 3, 0 > rm
Definition: types.hh:118
gem5::ArmISA::MacroVFPMemOp
Base class for microcoded floating point memory instructions.
Definition: macromem.hh:569
gem5::ArmISA::MicroNeonMixLaneOp64::replicate
bool replicate
Definition: macromem.hh:217
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ArmISA::VldMultOp64::VldMultOp64
VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb)
Definition: macromem.cc:1121
gem5::ArmISA::VstMultOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:249
gem5::ArmISA::MicroNeonMixOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:199
gem5::ArmISA::MicroMemPairOp::memAccessFlags
unsigned memAccessFlags
Definition: macromem.hh:444
gem5::ArmISA::VldSingleOp64::eSize
uint8_t eSize
Definition: macromem.hh:261
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:102
gem5::ArmISA::VldSingleOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:261
gem5::ArmISA::MicroOp::MicroOp
MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
Definition: macromem.hh:73
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::ArmISA::MicroNeonMixOp64::dest
RegIndex dest
Definition: macromem.hh:198
gem5::ArmISA::MicroNeonMemOp::memAccessFlags
unsigned memAccessFlags
Definition: macromem.hh:151
gem5::ArmISA::MicroIntOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1580
gem5::ArmISA::BigFpMemRegOp
Definition: macromem.hh:511
gem5::ArmISA::VldMultOp64::eSize
uint8_t eSize
Definition: macromem.hh:237
gem5::ArmISA::MicroIntRegXOp::type
ArmExtendType type
Definition: macromem.hh:382
gem5::ArmISA::VstSingleOp64
Definition: macromem.hh:270
gem5::ArmISA::MicroNeonMemOp
Microops for Neon loads/stores.
Definition: macromem.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::VstSingleOp64::replicate
bool replicate
Definition: macromem.hh:274
gem5::ArmISA::MicroNeonMixLaneOp64::dest
RegIndex dest
Definition: macromem.hh:215
pred_inst.hh
gem5::ArmISA::MicroNeonMixLaneOp64
Definition: macromem.hh:212
gem5::ArmISA::MicroSetPCCPSR::MicroSetPCCPSR
MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
Definition: macromem.hh:292
gem5::ArmISA::MicroNeonMixLaneOp
Definition: macromem.hh:178
gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp
BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, IntRegIndex offset, ArmExtendType type, int64_t imm)
Definition: macromem.cc:421
pcstate.hh
gem5::ArmISA::MicroMemOp::up
bool up
Definition: macromem.hh:424
gem5::ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:342
gem5::ArmISA::MicroIntOp::urb
RegIndex urb
Definition: macromem.hh:365
gem5::ArmISA::MicroNeonMixLaneOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:216
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp
MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, RegIndex vd, bool single, bool up, bool writeback, bool load, uint32_t offset)
Definition: macromem.cc:1438
gem5::ArmISA::VstMultOp64::wb
bool wb
Definition: macromem.hh:250
gem5::ArmISA::VldMultOp64
Base classes for microcoded AArch64 NEON memory instructions.
Definition: macromem.hh:234
gem5::ArmISA::MicroNeonMixLaneOp64::eSize
uint8_t eSize
Definition: macromem.hh:216
gem5::ArmISA::MicroIntOp::urc
RegIndex urc
Definition: macromem.hh:365
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MicroIntRegOp::shiftAmt
int32_t shiftAmt
Definition: macromem.hh:405
gem5::ArmISA::PairMemOp::PairMemOp
PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, bool exclusive, bool acrel, int64_t imm, AddrMode mode, IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2)
Definition: macromem.cc:243
gem5::ArmISA::MicroNeonMixOp64::step
uint8_t step
Definition: macromem.hh:199
gem5::ArmISA::MicroNeonMixOp::MicroNeonMixOp
MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint32_t _step)
Definition: macromem.hh:170
gem5::ArmISA::MicroMemOp::MicroMemOp
MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
Definition: macromem.hh:427
gem5::ArmISA::MicroIntOp::MicroIntOp
MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc)
Definition: macromem.hh:367
gem5::ArmISA::VldMultOp::VldMultOp
VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm)
Definition: macromem.cc:460
gem5::ArmISA::PairMemOp::AddrMd_PostIndex
@ AddrMd_PostIndex
Definition: macromem.hh:480
gem5::ArmISA::VldMultOp
Base classes for microcoded integer memory instructions.
Definition: macromem.hh:529
gem5::ArmISA::VldSingleOp::VldSingleOp
VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
Definition: macromem.cc:555
gem5::ArmISA::VstMultOp64::VstMultOp64
VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb)
Definition: macromem.cc:1206
gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp
BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
Definition: macromem.cc:395
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MicroIntMov::MicroIntMov
MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb)
Definition: macromem.hh:311
gem5::ArmISA::VstSingleOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:273
gem5::ArmISA::MicroMemOp::memAccessFlags
unsigned memAccessFlags
Definition: macromem.hh:425
gem5::ArmISA::MicroIntImmXOp::urb
RegIndex urb
Definition: macromem.hh:345
gem5::ArmISA::MicroIntImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1517
gem5::ArmISA::MicroOpX::advancePC
void advancePC(ThreadContext *tc) const override
Definition: macromem.hh:129
gem5::ArmISA::MicroSetPCCPSR::urb
IntRegIndex urb
Definition: macromem.hh:290
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:216
gem5::ArmISA::VldSingleOp64::index
uint8_t index
Definition: macromem.hh:261
gem5::ArmISA::MicroIntMov::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1568
gem5::ArmISA::MicroMemPairOp::dest2
RegIndex dest2
Definition: macromem.hh:441
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::PairMemOp::AddrMd_Offset
@ AddrMd_Offset
Definition: macromem.hh:478
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::VldSingleOp
Definition: macromem.hh:537
gem5::ArmISA::VldMultOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:237
gem5::ArmISA::PairMemOp
Base class for pair load/store instructions.
Definition: macromem.hh:473
gem5::ArmISA::MMU
Definition: mmu.hh:59
gem5::ArmISA::MicroIntImmOp::imm
int32_t imm
Definition: macromem.hh:329
gem5::ArmISA::MicroSetPCCPSR::urc
IntRegIndex urc
Definition: macromem.hh:290
gem5::ArmISA::MicroIntImmXOp
Definition: macromem.hh:342
gem5::ArmISA::rn
Bitfield< 19, 16 > rn
Definition: types.hh:113
thread_context.hh
gem5::ArmISA::VstMultOp64::numRegs
uint8_t numRegs
Definition: macromem.hh:249
gem5::ArmISA::MicroIntMov::ura
RegIndex ura
Definition: macromem.hh:309
gem5::GenericISA::SimplePCState::advance
void advance() override
Definition: pcstate.hh:376
gem5::ArmISA::VldSingleOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:261
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

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