gem5  v21.1.0.2
macromem.hh
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40 
41 #ifndef __ARCH_ARM_MACROMEM_HH__
42 #define __ARCH_ARM_MACROMEM_HH__
43 
45 #include "arch/arm/tlb.hh"
46 
47 namespace gem5
48 {
49 
50 namespace ArmISA
51 {
52 
53 static inline unsigned int
55 {
56  uint32_t ones = 0;
57  for (int i = 0; i < 32; i++ )
58  {
59  if ( val & (1<<i) )
60  ones++;
61  }
62  return ones;
63 }
64 
68 class MicroOp : public PredOp
69 {
70  protected:
71  MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
72  : PredOp(mnem, machInst, __opClass)
73  {
74  }
75 
76  public:
77  void
78  advancePC(PCState &pcState) const override
79  {
80  if (flags[IsLastMicroop]) {
81  pcState.uEnd();
82  } else if (flags[IsMicroop]) {
83  pcState.uAdvance();
84  } else {
85  pcState.advance();
86  }
87  }
88 };
89 
90 class MicroOpX : public ArmStaticInst
91 {
92  protected:
93  MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
94  : ArmStaticInst(mnem, machInst, __opClass)
95  {}
96 
97  public:
98  void
99  advancePC(PCState &pcState) const override
100  {
101  if (flags[IsLastMicroop]) {
102  pcState.uEnd();
103  } else if (flags[IsMicroop]) {
104  pcState.uAdvance();
105  } else {
106  pcState.advance();
107  }
108  }
109 };
110 
114 class MicroNeonMemOp : public MicroOp
115 {
116  protected:
118  uint32_t imm;
119  unsigned memAccessFlags;
120 
121  MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
122  RegIndex _dest, RegIndex _ura, uint32_t _imm)
123  : MicroOp(mnem, machInst, __opClass),
124  dest(_dest), ura(_ura), imm(_imm), memAccessFlags()
125  {
126  }
127 };
128 
132 class MicroNeonMixOp : public MicroOp
133 {
134  protected:
136  uint32_t step;
137 
138  MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
139  RegIndex _dest, RegIndex _op1, uint32_t _step)
140  : MicroOp(mnem, machInst, __opClass),
141  dest(_dest), op1(_op1), step(_step)
142  {
143  }
144 };
145 
147 {
148  protected:
149  unsigned lane;
150 
152  OpClass __opClass, RegIndex _dest, RegIndex _op1,
153  uint32_t _step, unsigned _lane)
154  : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
155  lane(_lane)
156  {
157  }
158 };
159 
163 class MicroNeonMixOp64 : public MicroOp
164 {
165  protected:
168 
169  MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
170  RegIndex _dest, RegIndex _op1, uint8_t _eSize,
171  uint8_t _dataSize, uint8_t _numStructElems,
172  uint8_t _numRegs, uint8_t _step)
173  : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
174  eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
175  numRegs(_numRegs), step(_step)
176  {
177  }
178 };
179 
181 {
182  protected:
185  bool replicate;
186 
188  OpClass __opClass, RegIndex _dest, RegIndex _op1,
189  uint8_t _eSize, uint8_t _dataSize,
190  uint8_t _numStructElems, uint8_t _lane, uint8_t _step,
191  bool _replicate = false)
192  : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
193  eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
194  lane(_lane), step(_step), replicate(_replicate)
195  {
196  }
197 };
198 
202 class VldMultOp64 : public PredMacroOp
203 {
204  protected:
206  bool wb;
207 
208  VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
209  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
210  uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
211  bool wb);
212 };
213 
214 class VstMultOp64 : public PredMacroOp
215 {
216  protected:
218  bool wb;
219 
220  VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
221  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
222  uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
223  bool wb);
224 };
225 
227 {
228  protected:
230  bool wb, replicate;
231 
232  VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
233  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
234  uint8_t dataSize, uint8_t numStructElems, uint8_t index,
235  bool wb, bool replicate = false);
236 };
237 
239 {
240  protected:
242  bool wb, replicate;
243 
244  VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
245  RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
246  uint8_t dataSize, uint8_t numStructElems, uint8_t index,
247  bool wb, bool replicate = false);
248 };
249 
255 class MicroSetPCCPSR : public MicroOp
256 {
257  protected:
258  IntRegIndex ura, urb, urc;
259 
260  MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
261  IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
262  : MicroOp(mnem, machInst, __opClass),
263  ura(_ura), urb(_urb), urc(_urc)
264  {
265  }
266 
267  std::string generateDisassembly(
268  Addr pc, const loader::SymbolTable *symtab) const override;
269 };
270 
274 class MicroIntMov : public MicroOp
275 {
276  protected:
278 
279  MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
280  RegIndex _ura, RegIndex _urb)
281  : MicroOp(mnem, machInst, __opClass),
282  ura(_ura), urb(_urb)
283  {
284  }
285 
286  std::string generateDisassembly(
287  Addr pc, const loader::SymbolTable *symtab) const override;
288 };
289 
293 class MicroIntImmOp : public MicroOp
294 {
295  protected:
297  int32_t imm;
298 
299  MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
300  RegIndex _ura, RegIndex _urb, int32_t _imm)
301  : MicroOp(mnem, machInst, __opClass),
302  ura(_ura), urb(_urb), imm(_imm)
303  {
304  }
305 
306  std::string generateDisassembly(
307  Addr pc, const loader::SymbolTable *symtab) const override;
308 };
309 
310 class MicroIntImmXOp : public MicroOpX
311 {
312  protected:
314  int64_t imm;
315 
316  MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
317  RegIndex _ura, RegIndex _urb, int64_t _imm)
318  : MicroOpX(mnem, machInst, __opClass),
319  ura(_ura), urb(_urb), imm(_imm)
320  {
321  }
322 
323  std::string generateDisassembly(
324  Addr pc, const loader::SymbolTable *symtab) const override;
325 };
326 
330 class MicroIntOp : public MicroOp
331 {
332  protected:
334 
335  MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
336  RegIndex _ura, RegIndex _urb, RegIndex _urc)
337  : MicroOp(mnem, machInst, __opClass),
338  ura(_ura), urb(_urb), urc(_urc)
339  {
340  }
341 
342  std::string generateDisassembly(
343  Addr pc, const loader::SymbolTable *symtab) const override;
344 };
345 
346 class MicroIntRegXOp : public MicroOp
347 {
348  protected:
351  uint32_t shiftAmt;
352 
353  MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
354  RegIndex _ura, RegIndex _urb, RegIndex _urc,
355  ArmExtendType _type, uint32_t _shiftAmt)
356  : MicroOp(mnem, machInst, __opClass),
357  ura(_ura), urb(_urb), urc(_urc),
358  type(_type), shiftAmt(_shiftAmt)
359  {
360  }
361 
362  std::string generateDisassembly(
363  Addr pc, const loader::SymbolTable *symtab) const override;
364 };
365 
369 class MicroIntRegOp : public MicroOp
370 {
371  protected:
373  int32_t shiftAmt;
374  ArmShiftType shiftType;
375 
376  MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
377  RegIndex _ura, RegIndex _urb, RegIndex _urc,
378  int32_t _shiftAmt, ArmShiftType _shiftType)
379  : MicroOp(mnem, machInst, __opClass),
380  ura(_ura), urb(_urb), urc(_urc),
381  shiftAmt(_shiftAmt), shiftType(_shiftType)
382  {
383  }
384 };
385 
389 class MicroMemOp : public MicroIntImmOp
390 {
391  protected:
392  bool up;
393  unsigned memAccessFlags;
394 
395  MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
396  RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
397  : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
398  up(_up), memAccessFlags(TLB::AlignWord)
399  {
400  }
401 
402  std::string generateDisassembly(
403  Addr pc, const loader::SymbolTable *symtab) const override;
404 };
405 
406 class MicroMemPairOp : public MicroOp
407 {
408  protected:
410  bool up;
411  int32_t imm;
412  unsigned memAccessFlags;
413 
414  MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
415  RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
416  bool _up, uint8_t _imm)
417  : MicroOp(mnem, machInst, __opClass),
418  dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
419  memAccessFlags(TLB::AlignWord)
420  {
421  }
422 
423  std::string generateDisassembly(
424  Addr pc, const loader::SymbolTable *symtab) const override;
425 };
426 
430 class MacroMemOp : public PredMacroOp
431 {
432  protected:
433  MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
434  IntRegIndex rn, bool index, bool up, bool user,
435  bool writeback, bool load, uint32_t reglist);
436 };
437 
441 class PairMemOp : public PredMacroOp
442 {
443  public:
444  enum AddrMode
445  {
449  };
450 
451  protected:
452  PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
453  uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
454  bool exclusive, bool acrel, int64_t imm, AddrMode mode,
455  IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
456 };
457 
459 {
460  protected:
461  BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
462  bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
463 };
464 
466 {
467  protected:
468  BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
469  bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
470 };
471 
473 {
474  protected:
475  BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
476  bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
477 };
478 
480 {
481  protected:
482  BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
483  bool load, IntRegIndex dest, IntRegIndex base,
484  IntRegIndex offset, ArmExtendType type, int64_t imm);
485 };
486 
488 {
489  protected:
490  BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
491  IntRegIndex dest, int64_t imm);
492 };
493 
497 class VldMultOp : public PredMacroOp
498 {
499  protected:
500  VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
501  unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
502  unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
503 };
504 
505 class VldSingleOp : public PredMacroOp
506 {
507  protected:
508  VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
509  bool all, unsigned elems, RegIndex rn, RegIndex vd,
510  unsigned regs, unsigned inc, uint32_t size,
511  uint32_t align, RegIndex rm, unsigned lane);
512 };
513 
517 class VstMultOp : public PredMacroOp
518 {
519  protected:
520  VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
521  unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
522  unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
523 };
524 
525 class VstSingleOp : public PredMacroOp
526 {
527  protected:
528  VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
529  bool all, unsigned elems, RegIndex rn, RegIndex vd,
530  unsigned regs, unsigned inc, uint32_t size,
531  uint32_t align, RegIndex rm, unsigned lane);
532 };
533 
538 {
539  protected:
540  MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
541  IntRegIndex rn, RegIndex vd, bool single, bool up,
542  bool writeback, bool load, uint32_t offset);
543 };
544 
545 } // namespace ArmISA
546 } // namespace gem5
547 
548 #endif //__ARCH_ARM_INSTS_MACROMEM_HH__
gem5::ArmISA::VldMultOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:205
gem5::ArmISA::MicroMemPairOp::MicroMemPairOp
MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, bool _up, uint8_t _imm)
Definition: macromem.hh:414
gem5::ArmISA::VldSingleOp64::VldSingleOp64
VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate=false)
Definition: macromem.cc:1291
gem5::ArmISA::MicroIntOp::ura
RegIndex ura
Definition: macromem.hh:333
gem5::ArmISA::number_of_ones
static unsigned int number_of_ones(int32_t val)
Definition: macromem.hh:54
gem5::ArmISA::MicroNeonMixLaneOp64::op1
RegIndex op1
Definition: macromem.hh:183
gem5::ArmISA::BigFpMemLitOp::BigFpMemLitOp
BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex dest, int64_t imm)
Definition: macromem.cc:447
gem5::ArmISA::MicroNeonMixOp
Microops for Neon load/store (de)interleaving.
Definition: macromem.hh:132
gem5::ArmISA::VldSingleOp64
Definition: macromem.hh:226
gem5::ArmISA::MicroIntImmOp::ura
RegIndex ura
Definition: macromem.hh:296
gem5::ArmISA::VstMultOp64::eSize
uint8_t eSize
Definition: macromem.hh:217
gem5::ArmISA::VldSingleOp64::replicate
bool replicate
Definition: macromem.hh:230
gem5::ArmISA::MicroIntMov
Microops of the form IntRegA = IntRegB.
Definition: macromem.hh:274
gem5::ArmISA::VstSingleOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:241
gem5::ArmISA::BigFpMemPostOp
Definition: macromem.hh:465
gem5::ArmISA::MicroNeonMixOp::op1
RegIndex op1
Definition: macromem.hh:135
gem5::ArmISA::MicroIntImmOp
Microops of the form IntRegA = IntRegB op Imm.
Definition: macromem.hh:293
gem5::ArmISA::MicroNeonMixOp64::eSize
uint8_t eSize
Definition: macromem.hh:167
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp
BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
Definition: macromem.cc:369
gem5::ArmISA::MicroIntRegXOp::urb
RegIndex urb
Definition: macromem.hh:349
gem5::ArmISA::MicroIntRegOp::ura
RegIndex ura
Definition: macromem.hh:372
gem5::ArmISA::MicroNeonMixLaneOp64::step
uint8_t step
Definition: macromem.hh:184
gem5::ArmISA::MicroNeonMixOp::step
uint32_t step
Definition: macromem.hh:136
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::MicroNeonMixOp64::numRegs
uint8_t numRegs
Definition: macromem.hh:167
gem5::ArmISA::up
Bitfield< 23 > up
Definition: types.hh:124
gem5::ArmISA::writeback
Bitfield< 21 > writeback
Definition: types.hh:126
gem5::ArmISA::VstMultOp
Base class for microcoded integer memory instructions.
Definition: macromem.hh:517
gem5::ArmISA::MicroNeonMemOp::imm
uint32_t imm
Definition: macromem.hh:118
gem5::ArmISA::MicroNeonMixOp64::op1
RegIndex op1
Definition: macromem.hh:166
gem5::ArmISA::MicroIntRegOp::urc
RegIndex urc
Definition: macromem.hh:372
gem5::ArmISA::MicroSetPCCPSR::ura
IntRegIndex ura
Definition: macromem.hh:258
gem5::ArmISA::MicroOp
Base class for Memory microops.
Definition: macromem.hh:68
gem5::ArmISA::MicroNeonMixLaneOp::lane
unsigned lane
Definition: macromem.hh:149
gem5::ArmISA::MacroMemOp
Base class for microcoded integer memory instructions.
Definition: macromem.hh:430
gem5::ArmISA::MicroOpX
Definition: macromem.hh:90
gem5::ArmISA::MicroMemOp
Memory microops which use IntReg + Imm addressing.
Definition: macromem.hh:389
gem5::ArmISA::MicroIntImmOp::MicroIntImmOp
MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, int32_t _imm)
Definition: macromem.hh:299
gem5::ArmISA::PairMemOp::AddrMd_PreIndex
@ AddrMd_PreIndex
Definition: macromem.hh:447
gem5::ArmISA::VldMultOp64::numRegs
uint8_t numRegs
Definition: macromem.hh:205
gem5::ArmISA::MicroIntRegOp::shiftType
ArmShiftType shiftType
Definition: macromem.hh:374
gem5::ArmISA::MicroNeonMixLaneOp::MicroNeonMixLaneOp
MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint32_t _step, unsigned _lane)
Definition: macromem.hh:151
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::MicroIntImmOp::urb
RegIndex urb
Definition: macromem.hh:296
gem5::ArmISA::MicroIntRegXOp::urc
RegIndex urc
Definition: macromem.hh:349
gem5::ArmISA::TLB
Definition: tlb.hh:109
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:215
gem5::ArmISA::PairMemOp::AddrMode
AddrMode
Definition: macromem.hh:444
gem5::ArmISA::MicroOpX::MicroOpX
MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
Definition: macromem.hh:93
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::VldMultOp64::wb
bool wb
Definition: macromem.hh:206
gem5::ArmISA::MicroNeonMixOp64::MicroNeonMixOp64
MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, uint8_t _numRegs, uint8_t _step)
Definition: macromem.hh:169
gem5::ArmISA::MicroMemPairOp::up
bool up
Definition: macromem.hh:410
gem5::ArmISA::MicroSetPCCPSR::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1545
tlb.hh
gem5::ArmISA::VstSingleOp
Definition: macromem.hh:525
gem5::ArmISA::MicroNeonMixLaneOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:184
gem5::ArmISA::MicroMemPairOp::urb
RegIndex urb
Definition: macromem.hh:409
gem5::ArmISA::VstMultOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:217
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::MicroMemPairOp::dest
RegIndex dest
Definition: macromem.hh:409
gem5::ArmISA::MicroNeonMixOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:167
gem5::ArmISA::MicroMemPairOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1612
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ArmISA::fp
Bitfield< 19, 16 > fp
Definition: misc_types.hh:176
gem5::ArmISA::VstMultOp::VstMultOp
VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned width, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm)
Definition: macromem.cc:823
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::MicroIntRegXOp::shiftAmt
uint32_t shiftAmt
Definition: macromem.hh:351
gem5::ArmISA::VstMultOp64
Definition: macromem.hh:214
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISA::MicroIntRegXOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1555
gem5::ArmISA::MicroNeonMixOp64
Microops for AArch64 NEON load/store (de)interleaving.
Definition: macromem.hh:163
gem5::ArmISA::VldSingleOp64::wb
bool wb
Definition: macromem.hh:230
gem5::ArmISA::MicroNeonMemOp::MicroNeonMemOp
MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _ura, uint32_t _imm)
Definition: macromem.hh:121
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
sc_dt::inc
void inc(scfx_mant &mant)
Definition: scfx_mant.hh:341
gem5::ArmISA::BigFpMemLitOp
Definition: macromem.hh:487
gem5::ArmISA::MicroIntRegOp
Microops of the form IntRegA = IntRegB op shifted IntRegC.
Definition: macromem.hh:369
gem5::ArmISA::MicroIntImmXOp::ura
RegIndex ura
Definition: macromem.hh:313
gem5::ArmISA::VstSingleOp::VstSingleOp
VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
Definition: macromem.cc:918
gem5::ArmISA::MicroIntRegXOp::MicroIntRegXOp
MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc, ArmExtendType _type, uint32_t _shiftAmt)
Definition: macromem.hh:353
gem5::ArmISA::VstSingleOp64::VstSingleOp64
VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate=false)
Definition: macromem.cc:1365
gem5::ArmISA::VstSingleOp64::wb
bool wb
Definition: macromem.hh:242
gem5::ArmISA::MicroIntRegOp::MicroIntRegOp
MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc, int32_t _shiftAmt, ArmShiftType _shiftType)
Definition: macromem.hh:376
gem5::ArmISA::MicroMemPairOp::imm
int32_t imm
Definition: macromem.hh:411
gem5::ArmISA::MicroIntImmXOp::MicroIntImmXOp
MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, int64_t _imm)
Definition: macromem.hh:316
gem5::ArmISA::MicroIntImmXOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1531
gem5::ArmISA::MicroIntRegXOp::ura
RegIndex ura
Definition: macromem.hh:349
gem5::ArmISA::MacroMemOp::MacroMemOp
MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, bool index, bool up, bool user, bool writeback, bool load, uint32_t reglist)
Definition: macromem.cc:57
gem5::ArmISA::MicroIntRegXOp
Definition: macromem.hh:346
gem5::ArmISA::MicroNeonMemOp::ura
RegIndex ura
Definition: macromem.hh:117
gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp
BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
Definition: macromem.cc:348
gem5::ArmISA::BigFpMemPreOp
Definition: macromem.hh:472
gem5::ArmISA::MicroNeonMixLaneOp64::lane
uint8_t lane
Definition: macromem.hh:184
gem5::ArmISA::MicroNeonMixOp::dest
RegIndex dest
Definition: macromem.hh:135
gem5::ArmISA::MicroIntOp
Microops of the form IntRegA = IntRegB op IntRegC.
Definition: macromem.hh:330
gem5::ArmISA::MicroNeonMixLaneOp64::MicroNeonMixLaneOp64
MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, uint8_t _lane, uint8_t _step, bool _replicate=false)
Definition: macromem.hh:187
gem5::ArmISA::BigFpMemImmOp
Definition: macromem.hh:458
gem5::ArmISA::MicroIntMov::urb
RegIndex urb
Definition: macromem.hh:277
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:71
gem5::ArmISA::MicroIntRegOp::urb
RegIndex urb
Definition: macromem.hh:372
gem5::ArmISA::MicroMemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1594
gem5::ArmISA::VstSingleOp64::eSize
uint8_t eSize
Definition: macromem.hh:241
gem5::ArmISA::MicroSetPCCPSR
Microops of the form PC = IntRegA CPSR = IntRegB.
Definition: macromem.hh:255
gem5::ArmISA::MicroIntImmXOp::imm
int64_t imm
Definition: macromem.hh:314
gem5::ArmISA::MicroMemPairOp
Definition: macromem.hh:406
gem5::ArmISA::VstSingleOp64::index
uint8_t index
Definition: macromem.hh:241
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::MicroNeonMemOp::dest
RegIndex dest
Definition: macromem.hh:117
gem5::ArmISA::rm
Bitfield< 3, 0 > rm
Definition: types.hh:118
gem5::ArmISA::MacroVFPMemOp
Base class for microcoded floating point memory instructions.
Definition: macromem.hh:537
gem5::ArmISA::MicroNeonMixLaneOp64::replicate
bool replicate
Definition: macromem.hh:185
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ArmISA::VldMultOp64::VldMultOp64
VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb)
Definition: macromem.cc:1121
gem5::ArmISA::VstMultOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:217
gem5::ArmISA::MicroNeonMixOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:167
gem5::ArmISA::MicroMemPairOp::memAccessFlags
unsigned memAccessFlags
Definition: macromem.hh:412
gem5::ArmISA::VldSingleOp64::eSize
uint8_t eSize
Definition: macromem.hh:229
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::ArmISA::VldSingleOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:229
gem5::ArmISA::MicroOp::MicroOp
MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
Definition: macromem.hh:71
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::ArmISA::MicroNeonMixOp64::dest
RegIndex dest
Definition: macromem.hh:166
gem5::ArmISA::MicroNeonMemOp::memAccessFlags
unsigned memAccessFlags
Definition: macromem.hh:119
gem5::ArmISA::MicroIntOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1580
gem5::ArmISA::BigFpMemRegOp
Definition: macromem.hh:479
gem5::ArmISA::VldMultOp64::eSize
uint8_t eSize
Definition: macromem.hh:205
gem5::ArmISA::MicroIntRegXOp::type
ArmExtendType type
Definition: macromem.hh:350
gem5::ArmISA::VstSingleOp64
Definition: macromem.hh:238
gem5::ArmISA::MicroNeonMemOp
Microops for Neon loads/stores.
Definition: macromem.hh:114
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::VstSingleOp64::replicate
bool replicate
Definition: macromem.hh:242
gem5::ArmISA::MicroNeonMixLaneOp64::dest
RegIndex dest
Definition: macromem.hh:183
pred_inst.hh
gem5::ArmISA::MicroNeonMixLaneOp64
Definition: macromem.hh:180
gem5::ArmISA::MicroSetPCCPSR::MicroSetPCCPSR
MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
Definition: macromem.hh:260
gem5::ArmISA::MicroNeonMixLaneOp
Definition: macromem.hh:146
gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp
BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, IntRegIndex offset, ArmExtendType type, int64_t imm)
Definition: macromem.cc:421
gem5::ArmISA::MicroMemOp::up
bool up
Definition: macromem.hh:392
gem5::ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:340
gem5::ArmISA::MicroIntOp::urb
RegIndex urb
Definition: macromem.hh:333
gem5::GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:181
gem5::ArmISA::MicroNeonMixLaneOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:184
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp
MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, RegIndex vd, bool single, bool up, bool writeback, bool load, uint32_t offset)
Definition: macromem.cc:1438
gem5::ArmISA::VstMultOp64::wb
bool wb
Definition: macromem.hh:218
gem5::ArmISA::VldMultOp64
Base classes for microcoded AArch64 NEON memory instructions.
Definition: macromem.hh:202
gem5::ArmISA::MicroNeonMixLaneOp64::eSize
uint8_t eSize
Definition: macromem.hh:184
gem5::ArmISA::MicroIntOp::urc
RegIndex urc
Definition: macromem.hh:333
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MicroIntRegOp::shiftAmt
int32_t shiftAmt
Definition: macromem.hh:373
gem5::ArmISA::PairMemOp::PairMemOp
PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, bool exclusive, bool acrel, int64_t imm, AddrMode mode, IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2)
Definition: macromem.cc:243
gem5::ArmISA::MicroNeonMixOp64::step
uint8_t step
Definition: macromem.hh:167
gem5::ArmISA::MicroNeonMixOp::MicroNeonMixOp
MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint32_t _step)
Definition: macromem.hh:138
gem5::ArmISA::MicroMemOp::MicroMemOp
MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
Definition: macromem.hh:395
gem5::ArmISA::MicroIntOp::MicroIntOp
MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc)
Definition: macromem.hh:335
gem5::ArmISA::VldMultOp::VldMultOp
VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm)
Definition: macromem.cc:460
gem5::ArmISA::PairMemOp::AddrMd_PostIndex
@ AddrMd_PostIndex
Definition: macromem.hh:448
gem5::ArmISA::VldMultOp
Base classes for microcoded integer memory instructions.
Definition: macromem.hh:497
gem5::ArmISA::MicroOpX::advancePC
void advancePC(PCState &pcState) const override
Definition: macromem.hh:99
gem5::ArmISA::VldSingleOp::VldSingleOp
VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
Definition: macromem.cc:555
gem5::ArmISA::VstMultOp64::VstMultOp64
VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb)
Definition: macromem.cc:1206
gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp
BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
Definition: macromem.cc:395
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MicroIntMov::MicroIntMov
MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb)
Definition: macromem.hh:279
gem5::ArmISA::VstSingleOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:241
gem5::ArmISA::MicroMemOp::memAccessFlags
unsigned memAccessFlags
Definition: macromem.hh:393
gem5::ArmISA::MicroIntImmXOp::urb
RegIndex urb
Definition: macromem.hh:313
gem5::ArmISA::MicroIntImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1517
gem5::ArmISA::MicroSetPCCPSR::urb
IntRegIndex urb
Definition: macromem.hh:258
gem5::ArmISA::MicroOp::advancePC
void advancePC(PCState &pcState) const override
Definition: macromem.hh:78
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:214
gem5::ArmISA::VldSingleOp64::index
uint8_t index
Definition: macromem.hh:229
gem5::ArmISA::MicroIntMov::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: macromem.cc:1568
gem5::ArmISA::MicroMemPairOp::dest2
RegIndex dest2
Definition: macromem.hh:409
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::PairMemOp::AddrMd_Offset
@ AddrMd_Offset
Definition: macromem.hh:446
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::VldSingleOp
Definition: macromem.hh:505
gem5::ArmISA::VldMultOp64::dataSize
uint8_t dataSize
Definition: macromem.hh:205
gem5::ArmISA::PairMemOp
Base class for pair load/store instructions.
Definition: macromem.hh:441
gem5::ArmISA::MicroIntImmOp::imm
int32_t imm
Definition: macromem.hh:297
gem5::ArmISA::MicroSetPCCPSR::urc
IntRegIndex urc
Definition: macromem.hh:258
gem5::ArmISA::MicroIntImmXOp
Definition: macromem.hh:310
gem5::ArmISA::rn
Bitfield< 19, 16 > rn
Definition: types.hh:113
gem5::ArmISA::VstMultOp64::numRegs
uint8_t numRegs
Definition: macromem.hh:217
gem5::ArmISA::MicroIntMov::ura
RegIndex ura
Definition: macromem.hh:277
gem5::ArmISA::VldSingleOp64::numStructElems
uint8_t numStructElems
Definition: macromem.hh:229
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73

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