gem5
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arch
sparc
insts
unimp.hh
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_SPARC_INSTS_UNIMP_HH__
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#define __ARCH_SPARC_INSTS_UNIMP_HH__
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#include <memory>
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#include "
arch/generic/debugfaults.hh
"
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#include "
arch/sparc/insts/static_inst.hh
"
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#include "
base/cprintf.hh
"
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namespace
gem5
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{
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namespace
SparcISA
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{
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//
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// Unimplemented instructions
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//
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class
FailUnimplemented
:
public
SparcStaticInst
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{
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public
:
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FailUnimplemented
(
const
char
*_mnemonic,
ExtMachInst
_machInst) :
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SparcStaticInst
(_mnemonic, _machInst, No_OpClass)
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{
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flags
[IsInvalid] =
true
;
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}
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Fault
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execute
(
ExecContext
*xc,
trace::InstRecord
*traceData)
const override
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{
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return
std::make_shared<GenericISA::M5PanicFault>(
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"attempt to execute unimplemented instruction '%s' (inst %#08x)"
,
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mnemonic
,
machInst
);
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}
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std::string
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generateDisassembly
(
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Addr
pc
,
const
loader::SymbolTable
*symtab)
const override
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{
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return
csprintf
(
"%-10s (unimplemented)"
,
mnemonic
);
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}
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};
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class
WarnUnimplemented
:
public
SparcStaticInst
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{
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private
:
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mutable
bool
warned
;
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public
:
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WarnUnimplemented
(
const
char
*_mnemonic,
ExtMachInst
_machInst) :
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SparcStaticInst
(_mnemonic, _machInst, No_OpClass),
warned
(false)
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{}
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Fault
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execute
(
ExecContext
*xc,
trace::InstRecord
*traceData)
const override
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{
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if
(!
warned
) {
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return
std::make_shared<GenericISA::M5WarnFault>(
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"instruction '%s' unimplemented\n"
,
mnemonic
);
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warned
=
true
;
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}
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return
NoFault
;
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}
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std::string
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generateDisassembly
(
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Addr
pc
,
const
loader::SymbolTable
*symtab)
const override
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{
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return
csprintf
(
"%-10s (unimplemented)"
,
mnemonic
);
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}
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};
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}
// namespace SparcISA
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}
// namespace gem5
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#endif
// __ARCH_SPARC_INSTS_UNIMP_HH__
static_inst.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition
exec_context.hh:72
gem5::SparcISA::FailUnimplemented
Static instruction class for unimplemented instructions that cause simulator termination.
Definition
unimp.hh:57
gem5::SparcISA::FailUnimplemented::FailUnimplemented
FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
Constructor.
Definition
unimp.hh:60
gem5::SparcISA::FailUnimplemented::execute
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition
unimp.hh:67
gem5::SparcISA::FailUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition
unimp.hh:75
gem5::SparcISA::SparcStaticInst
Base class for all SPARC static instructions.
Definition
static_inst.hh:94
gem5::SparcISA::SparcStaticInst::machInst
ExtMachInst machInst
Definition
static_inst.hh:96
gem5::SparcISA::WarnUnimplemented
Base class for unimplemented instructions that cause a warning to be printed (but do not terminate si...
Definition
unimp.hh:92
gem5::SparcISA::WarnUnimplemented::WarnUnimplemented
WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
Constructor.
Definition
unimp.hh:99
gem5::SparcISA::WarnUnimplemented::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition
unimp.hh:115
gem5::SparcISA::WarnUnimplemented::execute
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition
unimp.hh:104
gem5::SparcISA::WarnUnimplemented::warned
bool warned
Have we warned on this instruction yet?
Definition
unimp.hh:95
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition
static_inst.hh:268
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition
static_inst.hh:103
gem5::loader::SymbolTable
Definition
symtab.hh:152
gem5::trace::InstRecord
Definition
insttracer.hh:62
cprintf.hh
debugfaults.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition
pra_constants.hh:243
gem5::SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition
types.hh:42
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition
types.hh:249
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition
cprintf.hh:161
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition
types.hh:253
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