gem5 v24.1.0.1
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CHIGenericController.hh
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1/*
2 * Copyright (c) 2023 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __MEM_RUBY_PROTOCOL_CHI_CHIGenericController_HH__
39#define __MEM_RUBY_PROTOCOL_CHI_CHIGenericController_HH__
40
41#include <iostream>
42#include <sstream>
43#include <string>
44
47#include "mem/ruby/protocol/AccessPermission.hh"
50#include "params/CHIGenericController.hh"
51
52// Generated from SLICC
53#include "mem/ruby/protocol/CHI/CHIDataMsg.hh"
54#include "mem/ruby/protocol/CHI/CHIRequestMsg.hh"
55#include "mem/ruby/protocol/CHI/CHIResponseMsg.hh"
56#include "mem/ruby/protocol/CHI/Cache_Controller.hh"
57
58namespace gem5
59{
60
61namespace ruby
62{
63
65{
66 public:
69
70 void init() override;
71
72 MessageBuffer *getMandatoryQueue() const override;
73 MessageBuffer *getMemReqQueue() const override;
74 MessageBuffer *getMemRespQueue() const override;
75 void initNetQueues() override;
76
77 void print(std::ostream& out) const override;
78 void wakeup() override;
79 void resetStats() override;
80 void regStats() override;
81 void collateStats() override;
82
83 void recordCacheTrace(int cntrl, CacheRecorder* tr) override;
84 Sequencer* getCPUSequencer() const override;
85 DMASequencer* getDMASequencer() const override;
86 GPUCoalescer* getGPUCoalescer() const override;
87
88 void addSequencer(RubyPort* seq);
89
90 bool functionalReadBuffers(PacketPtr&) override;
92 int functionalWriteBuffers(PacketPtr&) override;
93
94 AccessPermission getAccessPermission(const Addr& param_addr) override;
95
96 void functionalRead(const Addr& param_addr, Packet* param_pkt,
97 WriteMask& param_mask) override;
98 int functionalWrite(const Addr& param_addr, Packet* param_pkt) override;
99
100 protected:
109
111
112 public:
113 const int cacheLineSize;
114 const int cacheLineBits;
117
118 // interface to generic requesters and responders
119
121 {
125 CHI_DAT = 3
126 };
127
128 using CHIRequestMsg = CHI::CHIRequestMsg;
129 using CHIResponseMsg = CHI::CHIResponseMsg;
130 using CHIDataMsg = CHI::CHIDataMsg;
131 using CHIRequestMsgPtr = std::shared_ptr<CHIRequestMsg>;
132 using CHIResponseMsgPtr = std::shared_ptr<CHIResponseMsg>;
133 using CHIDataMsgPtr = std::shared_ptr<CHIDataMsg>;
134
135 bool
137 {
138 return sendMessage(msg, reqOut);
139 }
140
141 bool
143 {
144 return sendMessage(msg, snpOut);
145 }
146
147 bool
149 {
150 return sendMessage(msg, rspOut);
151 }
152
153 bool
155 {
156 return sendMessage(msg, datOut);
157 }
158
159 protected:
160 virtual bool recvRequestMsg(const CHIRequestMsg *msg) = 0;
161 virtual bool recvSnoopMsg(const CHIRequestMsg *msg) = 0;
162 virtual bool recvResponseMsg(const CHIResponseMsg *msg) = 0;
163 virtual bool recvDataMsg(const CHIDataMsg *msg) = 0;
164
165 private:
166 template<typename MsgType>
168 const std::function<bool(const MsgType*)> &callback)
169 {
170 bool pending = false;
171 Tick cur_tick = curTick();
172 while (buffer->isReady(cur_tick)) {
173 const MsgType *msg =
174 dynamic_cast<const MsgType*>(buffer->peek());
175 assert(msg);
176 if (callback(msg))
177 buffer->dequeue(cur_tick);
178 else {
179 pending = true;
180 break;
181 }
182 }
183 return pending;
184 }
185
186 template<typename MessageType>
188 {
189 Tick cur_tick = curTick();
190 if (buffer->areNSlotsAvailable(1, cur_tick)) {
191 buffer->enqueue(msg, curTick(), cyclesToTicks(Cycles(1)),
194 return true;
195 } else {
196 return false;
197 }
198 }
199
200};
201
202} // namespace ruby
203} // namespace gem5
204
205#endif // __CHIGenericController_H__
ClockedObjectParams Params
Parameters of ClockedObject.
Tick cyclesToTicks(Cycles c) const
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool functionalReadBuffers(PacketPtr &) override
These functions are used by ruby system to read/write the data blocks that exist with in the controll...
void initNetQueues() override
Initialize the message buffers.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
virtual bool recvResponseMsg(const CHIResponseMsg *msg)=0
GPUCoalescer * getGPUCoalescer() const override
virtual bool recvSnoopMsg(const CHIRequestMsg *msg)=0
DMASequencer * getDMASequencer() const override
virtual bool recvRequestMsg(const CHIRequestMsg *msg)=0
int functionalWrite(const Addr &param_addr, Packet *param_pkt) override
void resetStats() override
Callback to reset stats.
std::shared_ptr< CHIDataMsg > CHIDataMsgPtr
bool sendSnoopMsg(CHIRequestMsgPtr msg)
Sequencer * getCPUSequencer() const override
void collateStats() override
Function for collating statistics from all the controllers of this particular type.
std::shared_ptr< CHIResponseMsg > CHIResponseMsgPtr
std::shared_ptr< CHIRequestMsg > CHIRequestMsgPtr
bool sendResponseMsg(CHIResponseMsgPtr msg)
int functionalWriteBuffers(PacketPtr &) override
The return value indicates the number of messages written with the data from the packet.
bool sendRequestMsg(CHIRequestMsgPtr msg)
PARAMS(CHIGenericController)
MessageBuffer * getMemReqQueue() const override
bool receiveAllRdyMessages(MessageBuffer *buffer, const std::function< bool(const MsgType *)> &callback)
MessageBuffer * getMandatoryQueue() const override
bool sendMessage(MessageType &msg, MessageBuffer *buffer)
void regStats() override
Callback to set stat parameters.
void print(std::ostream &out) const override
virtual bool recvDataMsg(const CHIDataMsg *msg)=0
void recordCacheTrace(int cntrl, CacheRecorder *tr) override
void functionalRead(const Addr &param_addr, Packet *param_pkt, WriteMask &param_mask) override
AccessPermission getAccessPermission(const Addr &param_addr) override
MessageBuffer * getMemRespQueue() const override
bool areNSlotsAvailable(unsigned int n, Tick curTime)
bool isReady(Tick current_time) const
const Message * peek() const
Function for extracting the message at the head of the message queue.
Tick dequeue(Tick current_time, bool decrement_messages=true)
Updates the delay cycles of the message at the head of the queue, removes it from the queue and retur...
void enqueue(MsgPtr message, Tick curTime, Tick delta, bool ruby_is_random, bool ruby_warmup, bool bypassStrictFIFO=false)
STL vector class.
Definition stl.hh:37
Bitfield< 0 > p
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58

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