gem5 v24.1.0.1
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CHIGenericController.cc
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1/*
2 * Copyright (c) 2023 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
39
40#include <sys/types.h>
41#include <unistd.h>
42
43#include <cassert>
44#include <sstream>
45#include <string>
46#include <typeinfo>
47
48#include "debug/RubyCHIGeneric.hh"
50#include "mem/ruby/protocol/MemoryMsg.hh"
53
54namespace gem5
55{
56
57namespace ruby
58{
59
60using namespace CHI;
61
64 reqOut(p.reqOut), snpOut(p.snpOut),
65 rspOut(p.rspOut), datOut(p.datOut),
66 reqIn(p.reqIn), snpIn(p.snpIn),
67 rspIn(p.rspIn), datIn(p.datIn),
68 cacheLineSize(p.ruby_system->getBlockSizeBytes()),
69 cacheLineBits(floorLog2(cacheLineSize)),
70 dataChannelSize(p.data_channel_size),
71 dataMsgsPerLine(cacheLineSize / p.data_channel_size)
72{
73 m_machineID.type = MachineType_Cache;
75 p.ruby_system->registerAbstractController(
76 this, std::make_unique<CHIProtocolInfo>());
77 p.ruby_system->m_num_controllers[m_machineID.type]++;
78 m_ruby_system = p.ruby_system;
79}
80
81void
106
107void
109{
111
112 rspIn->setConsumer(this);
113 datIn->setConsumer(this);
114 snpIn->setConsumer(this);
115 reqIn->setConsumer(this);
116
117 resetStats();
118}
119
120void
122{
123 assert(seq != nullptr);
124 sequencers.emplace_back(seq);
125}
126
127void
128CHIGenericController::print(std::ostream& out) const
129{
130 out << "[CHIGenericController " << m_version << "]";
131}
132
135{
136 // CHIGenericController doesn't have a CPUSequencer
137 return nullptr;
138}
139
142{
143 // CHIGenericController doesn't have a DMASequencer
144 return nullptr;
145}
146
149{
150 // CHIGenericController doesn't have a GPUCoalescer
151 return nullptr;
152}
153
156{
157 // CHIGenericController doesn't have a MandatoryQueue
158 return nullptr;
159}
160
163{
164 // CHIGenericController doesn't have a MemReqQueue
165 return nullptr;
166}
167
170{
171 // CHIGenericController doesn't have a MemRespQueue
172 return nullptr;
173}
174
175void
180
181void
186
187void
192
193
194void
196{
197 bool pending = false;
198
199 DPRINTF(RubyCHIGeneric, "wakeup: checking incoming rsp messages\n");
200 pending = pending || receiveAllRdyMessages<CHIResponseMsg>(rspIn,
201 [this](const CHIResponseMsg* msg){ return recvResponseMsg(msg); });
202
203 DPRINTF(RubyCHIGeneric, "wakeup: checking incoming dat messages\n");
204 pending = pending || receiveAllRdyMessages<CHIDataMsg>(datIn,
205 [this](const CHIDataMsg* msg){ return recvDataMsg(msg); });
206
207 DPRINTF(RubyCHIGeneric, "wakeup: checking incoming snp messages\n");
208 pending = pending || receiveAllRdyMessages<CHIRequestMsg>(snpIn,
209 [this](const CHIRequestMsg* msg){ return recvSnoopMsg(msg); });
210
211 DPRINTF(RubyCHIGeneric, "wakeup: checking incoming req messages\n");
212 pending = pending || receiveAllRdyMessages<CHIRequestMsg>(reqIn,
213 [this](const CHIRequestMsg* msg){ return recvRequestMsg(msg); });
214
215 if (pending) {
216 DPRINTF(RubyCHIGeneric, "wakeup: messages pending\n");
218 }
219}
220
221void
223{
224 panic("CHIGenericController doesn't implement recordCacheTrace");
225}
226
227AccessPermission
229{
230 return AccessPermission_NotPresent;
231}
232
233void
235 const Addr& param_addr, Packet* param_pkt, WriteMask& param_mask)
236{
237 panic("CHIGenericController doesn't expect functionalRead");
238}
239
240int
242 const Addr& param_addr, Packet* param_pkt)
243{
244 panic("CHIGenericController doesn't expect functionalRead");
245 return 0;
246}
247
248int
250{
251 int num_functional_writes = 0;
252 num_functional_writes += reqOut->functionalWrite(pkt);
253 num_functional_writes += snpOut->functionalWrite(pkt);
254 num_functional_writes += rspOut->functionalWrite(pkt);
255 num_functional_writes += datOut->functionalWrite(pkt);
256 num_functional_writes += reqIn->functionalWrite(pkt);
257 num_functional_writes += snpIn->functionalWrite(pkt);
258 num_functional_writes += rspIn->functionalWrite(pkt);
259 num_functional_writes += datIn->functionalWrite(pkt);
260 return num_functional_writes;
261}
262
263bool
265{
266 if (reqOut->functionalRead(pkt)) return true;
267 if (snpOut->functionalRead(pkt)) return true;
268 if (rspOut->functionalRead(pkt)) return true;
269 if (datOut->functionalRead(pkt)) return true;
270 if (reqIn->functionalRead(pkt)) return true;
271 if (snpIn->functionalRead(pkt)) return true;
272 if (rspIn->functionalRead(pkt)) return true;
273 if (datIn->functionalRead(pkt)) return true;
274 return false;
275}
276
277bool
279{
280 bool read = false;
281 if (reqOut->functionalRead(pkt, mask)) read = true;
282 if (snpOut->functionalRead(pkt, mask)) read = true;
283 if (rspOut->functionalRead(pkt, mask)) read = true;
284 if (datOut->functionalRead(pkt, mask)) read = true;
285 if (reqIn->functionalRead(pkt, mask)) read = true;
286 if (snpIn->functionalRead(pkt, mask)) read = true;
287 if (rspIn->functionalRead(pkt, mask)) read = true;
288 if (datIn->functionalRead(pkt, mask)) read = true;
289 return read;
290}
291
292} // namespace ruby
293} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
ClockedObjectParams Params
Parameters of ClockedObject.
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
virtual void regStats()
Callback to set stat parameters.
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
virtual void resetStats()=0
Callback to reset stats.
bool functionalReadBuffers(PacketPtr &) override
These functions are used by ruby system to read/write the data blocks that exist with in the controll...
void initNetQueues() override
Initialize the message buffers.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
virtual bool recvResponseMsg(const CHIResponseMsg *msg)=0
GPUCoalescer * getGPUCoalescer() const override
virtual bool recvSnoopMsg(const CHIRequestMsg *msg)=0
DMASequencer * getDMASequencer() const override
virtual bool recvRequestMsg(const CHIRequestMsg *msg)=0
int functionalWrite(const Addr &param_addr, Packet *param_pkt) override
void resetStats() override
Callback to reset stats.
Sequencer * getCPUSequencer() const override
void collateStats() override
Function for collating statistics from all the controllers of this particular type.
int functionalWriteBuffers(PacketPtr &) override
The return value indicates the number of messages written with the data from the packet.
MessageBuffer * getMemReqQueue() const override
MessageBuffer * getMandatoryQueue() const override
void regStats() override
Callback to set stat parameters.
void print(std::ostream &out) const override
virtual bool recvDataMsg(const CHIDataMsg *msg)=0
void recordCacheTrace(int cntrl, CacheRecorder *tr) override
void functionalRead(const Addr &param_addr, Packet *param_pkt, WriteMask &param_mask) override
AccessPermission getAccessPermission(const Addr &param_addr) override
MessageBuffer * getMemRespQueue() const override
void scheduleEvent(Cycles timeDelta)
Definition Consumer.cc:56
void setConsumer(Consumer *consumer)
bool functionalRead(Packet *pkt)
uint32_t functionalWrite(Packet *pkt)
void setToNetQueue(NodeID global_id, bool ordered, int netNumber, std::string vnet_type, MessageBuffer *b)
Definition Network.cc:211
virtual void setFromNetQueue(NodeID global_id, bool ordered, int netNumber, std::string vnet_type, MessageBuffer *b)
Definition Network.cc:224
int MachineType_base_number(const MachineType &obj)
static constexpr std::enable_if_t< std::is_integral_v< T >, int > floorLog2(T x)
Definition intmath.hh:59
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
Bitfield< 0 > p
Bitfield< 51, 12 > base
Definition pagetable.hh:141
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
NodeID num
range: 0 ... number of this machine's components in system - 1
Definition MachineID.hh:64

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