44 template <
class Types>
51 template <
class Types>
55 periphClockRateControl->set_mul_div(sys_counter_frq, 1);
58 template <
class Types>
63 panic_if(!gem5CpuCluster,
"Cluster should be of type CortexA76Cluster");
66 template <
class Types>
70 this->rvbaraddr[core]->set_state(0,
addr);
73 template <
class Types>
78 for (
auto &poweron_reset : this->poweron_reset) {
79 poweron_reset->signal_out.set_state(0,
true);
80 poweron_reset->signal_out.set_state(0,
false);
83 this->top_reset.signal_out.set_state(0,
true);
84 this->top_reset.signal_out.set_state(0,
false);
86 this->dbg_reset.signal_out.set_state(0,
true);
87 this->dbg_reset.signal_out.set_state(0,
false);
90 template <
class Types>
95 top_reset(
p.
name +
".top_reset", 0),
96 dbg_reset(
p.
name +
".dbg_reset", 0),
97 model_reset(
p.
name +
".model_reset", -1, this),
122 Base::cnthpirq[
i].bind(
cnthpirq[
i]->signal_in);
123 Base::cnthvirq[
i].bind(
cnthvirq[
i]->signal_in);
124 Base::cntpsirq[
i].bind(
cntpsirq[
i]->signal_in);
125 Base::cntvirq[
i].bind(
cntvirq[
i]->signal_in);
126 Base::commirq[
i].bind(
commirq[
i]->signal_in);
128 Base::pmuirq[
i].bind(
pmuirq[
i]->signal_in);
143 template <
class Types>
148 panic_if(Base::amba->transport_dbg(*trans) != trans->get_data_length(),
149 "Didn't send entire functional packet!");
153 template <
class Types>
157 Base::before_end_of_elaboration();
159 auto set_on_change = [
this](
162 auto *pin = gen->get(gem5CpuCluster->getCore(num)->getContext(0));
163 auto handler = [pin](
bool status)
165 status ? pin->raise() : pin->clear();
170 for (
int i = 0;
i < CoreCount;
i++) {
171 set_on_change(*cnthpirq[
i], gem5CpuCluster->params().cnthpirq,
i);
172 set_on_change(*cnthvirq[
i], gem5CpuCluster->params().cnthvirq,
i);
173 set_on_change(*cntpsirq[
i], gem5CpuCluster->params().cntpsirq,
i);
174 set_on_change(*cntvirq[
i], gem5CpuCluster->params().cntvirq,
i);
175 set_on_change(*commirq[
i], gem5CpuCluster->params().commirq,
i);
176 set_on_change(*ctidbgirq[
i], gem5CpuCluster->params().ctidbgirq,
i);
177 set_on_change(*pmuirq[
i], gem5CpuCluster->params().pmuirq,
i);
178 set_on_change(*vcpumntirq[
i], gem5CpuCluster->params().vcpumntirq,
i);
179 set_on_change(*cntpnsirq[
i], gem5CpuCluster->params().cntpnsirq,
i);
183 template <
class Types>
187 if (if_name ==
"redistributor")
188 return *redist.at(idx);
189 else if (if_name ==
"core_reset")
190 return *core_reset.at(idx);
191 else if (if_name ==
"poweron_reset")
192 return *poweron_reset.at(idx);
193 else if (if_name ==
"amba")
195 else if (if_name ==
"top_reset")
197 else if (if_name ==
"dbg_reset")
199 else if (if_name ==
"model_reset")
202 return Base::gem5_getPort(if_name, idx);
Base class for ARM GIC implementations.
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Ports are used to interface objects to each other.
Abstract superclass for simulation objects.
std::vector< std::unique_ptr< SignalReceiver > > cntvirq
typename Types::Base Base
amba_pv::signal_master_port< T > SignalInitiator
std::vector< std::unique_ptr< SignalReceiver > > cntpnsirq
std::vector< std::unique_ptr< SignalReceiver > > pmuirq
sc_gem5::TlmTargetBaseWrapper< 64, svp_gicv3_comms::gicv3_comms_fw_if, svp_gicv3_comms::gicv3_comms_bw_if, 1, sc_core::SC_ONE_OR_MORE_BOUND > TlmGicTarget
void setResetAddr(int core, Addr addr, bool secure) override
std::vector< std::unique_ptr< SignalInitiator< uint64_t > > > rvbaraddr
static const int CoreCount
void setCluster(SimObject *cluster) override
std::vector< std::unique_ptr< TlmGicTarget > > redist
std::vector< std::unique_ptr< SignalSender > > poweron_reset
std::vector< std::unique_ptr< SignalReceiver > > cnthpirq
std::vector< std::unique_ptr< SignalReceiver > > ctidbgirq
std::vector< std::unique_ptr< SignalSender > > core_reset
std::vector< std::unique_ptr< SignalReceiver > > cnthvirq
void before_end_of_elaboration() override
typename Types::Params Params
ClockRateControlInitiatorSocket clockRateControl
ClockRateControlInitiatorSocket periphClockRateControl
ScxEvsCortexA76(const Params &p)
void setClkPeriod(Tick clk_period) override
void sendFunc(PacketPtr pkt) override
std::vector< std::unique_ptr< SignalReceiver > > cntpsirq
std::vector< std::unique_ptr< SignalReceiver > > vcpumntirq
std::vector< std::unique_ptr< SignalReceiver > > commirq
Port & gem5_getPort(const std::string &if_name, int idx) override
void setSysCounterFrq(uint64_t sys_counter_frq) override
void onChange(OnChangeFunc func)
amba_pv::signal_master_port< bool > signal_out
virtual void bind(base_target_socket_type &s)
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t Tick
Tick count type.
std::string csprintf(const char *format, const Args &...args)
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
tlm::tlm_generic_payload * packet2payload(PacketPtr packet)
Convert a gem5 packet to TLM payload by copying all the relevant information to new payload.
const std::string & name()