gem5  v21.2.1.1
evs.cc
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27 
29 
32 #include "base/logging.hh"
33 #include "dev/arm/base_gic.hh"
34 #include "sim/core.hh"
36 
37 namespace gem5
38 {
39 
40 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
41 namespace fastmodel
42 {
43 
44 template <class Types>
45 void
47 {
48  clockRateControl->set_mul_div(sim_clock::as_int::s, clk_period);
49 }
50 
51 template <class Types>
52 void
54 {
55  periphClockRateControl->set_mul_div(sys_counter_frq, 1);
56 }
57 
58 template <class Types>
59 void
61 {
62  gem5CpuCluster = dynamic_cast<CortexA76Cluster *>(cluster);
63  panic_if(!gem5CpuCluster, "Cluster should be of type CortexA76Cluster");
64 }
65 
66 template <class Types>
67 void
69 {
70  this->rvbaraddr[core]->set_state(0, addr);
71 }
72 
73 template <class Types>
75  const sc_core::sc_module_name &mod_name, const Params &p) :
76  Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
77  params(p)
78 {
79  for (int i = 0; i < CoreCount; i++) {
80  redist.emplace_back(new TlmGicTarget(this->redistributor[i],
81  csprintf("%s.redistributor[%d]", name(), i), i));
82  cnthpirq.emplace_back(new SignalReceiver(csprintf("cnthpirq[%d]", i)));
83  cnthvirq.emplace_back(new SignalReceiver(csprintf("cnthvirq[%d]", i)));
84  cntpsirq.emplace_back(new SignalReceiver(csprintf("cntpsirq[%d]", i)));
85  cntvirq.emplace_back(new SignalReceiver(csprintf("cntvirq[%d]", i)));
86  commirq.emplace_back(new SignalReceiver(csprintf("commirq[%d]", i)));
87  ctidbgirq.emplace_back(
88  new SignalReceiver(csprintf("ctidbgirq[%d]", i)));
89  pmuirq.emplace_back(new SignalReceiver(csprintf("pmuirq[%d]", i)));
90  vcpumntirq.emplace_back(
91  new SignalReceiver(csprintf("vcpumntirq[%d]", i)));
92  cntpnsirq.emplace_back(
93  new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
94  rvbaraddr.emplace_back(new SignalInitiator<uint64_t>(
95  csprintf("rvbaraddr[%d]", i).c_str()));
96 
97  Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
98  Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
99  Base::cntpsirq[i].bind(cntpsirq[i]->signal_in);
100  Base::cntvirq[i].bind(cntvirq[i]->signal_in);
101  Base::commirq[i].bind(commirq[i]->signal_in);
102  Base::ctidbgirq[i].bind(ctidbgirq[i]->signal_in);
103  Base::pmuirq[i].bind(pmuirq[i]->signal_in);
104  Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
105  Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);
106  rvbaraddr[i]->bind(Base::rvbaraddr[i]);
107  }
108 
109  clockRateControl.bind(this->clock_rate_s);
110  periphClockRateControl.bind(this->periph_clock_rate_s);
111 }
112 
113 template <class Types>
114 void
116 {
117  auto *trans = sc_gem5::packet2payload(pkt);
118  panic_if(Base::amba->transport_dbg(*trans) != trans->get_data_length(),
119  "Didn't send entire functional packet!");
120  trans->release();
121 }
122 
123 template <class Types>
124 void
126 {
127  Base::before_end_of_elaboration();
128 
129  auto set_on_change = [this](
130  SignalReceiver &recv, ArmInterruptPinGen *gen, int num)
131  {
132  auto *pin = gen->get(gem5CpuCluster->getCore(num)->getContext(0));
133  auto handler = [pin](bool status)
134  {
135  status ? pin->raise() : pin->clear();
136  };
137  recv.onChange(handler);
138  };
139 
140  for (int i = 0; i < CoreCount; i++) {
141  set_on_change(*cnthpirq[i], gem5CpuCluster->params().cnthpirq, i);
142  set_on_change(*cnthvirq[i], gem5CpuCluster->params().cnthvirq, i);
143  set_on_change(*cntpsirq[i], gem5CpuCluster->params().cntpsirq, i);
144  set_on_change(*cntvirq[i], gem5CpuCluster->params().cntvirq, i);
145  set_on_change(*commirq[i], gem5CpuCluster->params().commirq, i);
146  set_on_change(*ctidbgirq[i], gem5CpuCluster->params().ctidbgirq, i);
147  set_on_change(*pmuirq[i], gem5CpuCluster->params().pmuirq, i);
148  set_on_change(*vcpumntirq[i], gem5CpuCluster->params().vcpumntirq, i);
149  set_on_change(*cntpnsirq[i], gem5CpuCluster->params().cntpnsirq, i);
150  }
151 }
152 
153 template <class Types>
154 Port &
155 ScxEvsCortexA76<Types>::gem5_getPort(const std::string &if_name, int idx)
156 {
157  if (if_name == "redistributor")
158  return *redist.at(idx);
159  else if (if_name == "amba")
160  return amba;
161  else
162  return Base::gem5_getPort(if_name, idx);
163 }
164 
169 
170 } // namespace fastmodel
171 } // namespace gem5
cortex_a76.hh
gem5::fastmodel::ScxEvsCortexA76::rvbaraddr
std::vector< std::unique_ptr< SignalInitiator< uint64_t > > > rvbaraddr
Definition: evs.hh:92
gem5::fastmodel::ScxEvsCortexA76::cntpsirq
std::vector< std::unique_ptr< SignalReceiver > > cntpsirq
Definition: evs.hh:85
gem5_to_tlm.hh
base_gic.hh
gem5::fastmodel::ScxEvsCortexA76::periphClockRateControl
ClockRateControlInitiatorSocket periphClockRateControl
Definition: evs.hh:70
gem5::fastmodel::ScxEvsCortexA76::setResetAddr
void setResetAddr(int core, Addr addr, bool secure) override
Definition: evs.cc:68
sc_gem5::packet2payload
tlm::tlm_generic_payload * packet2payload(PacketPtr packet)
Convert a gem5 packet to a TLM payload by copying all the relevant information to new tlm payload.
Definition: gem5_to_tlm.cc:128
gem5::fastmodel::ScxEvsCortexA76::pmuirq
std::vector< std::unique_ptr< SignalReceiver > > pmuirq
Definition: evs.hh:89
gem5::fastmodel::ScxEvsCortexA76::cnthpirq
std::vector< std::unique_ptr< SignalReceiver > > cnthpirq
Definition: evs.hh:83
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::sim_clock::as_int::s
Tick s
second
Definition: core.cc:68
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
cpu.hh
gem5::fastmodel::ScxEvsCortexA76::commirq
std::vector< std::unique_ptr< SignalReceiver > > commirq
Definition: evs.hh:87
evs.hh
gem5::fastmodel::ScxEvsCortexA76::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:60
gem5::fastmodel::ScxEvsCortexA76::cntpnsirq
std::vector< std::unique_ptr< SignalReceiver > > cntpnsirq
Definition: evs.hh:91
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::fastmodel::ScxEvsCortexA76::before_end_of_elaboration
void before_end_of_elaboration() override
Definition: evs.cc:125
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::fastmodel::ScxEvsCortexA76
Definition: evs.hh:60
gem5::fastmodel::ScxEvsCortexA76::CoreCount
static const int CoreCount
Definition: evs.hh:63
gem5::fastmodel::ScxEvsCortexA76::cntvirq
std::vector< std::unique_ptr< SignalReceiver > > cntvirq
Definition: evs.hh:86
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
name
const std::string & name()
Definition: trace.cc:49
gem5::fastmodel::ScxEvsCortexA76::ScxEvsCortexA76
ScxEvsCortexA76(const Params &p)
Definition: evs.hh:99
gem5::fastmodel::ScxEvsCortexA76::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:53
gem5::fastmodel::ScxEvsCortexA76::TlmGicTarget
sc_gem5::TlmTargetBaseWrapper< 64, svp_gicv3_comms::gicv3_comms_fw_if, svp_gicv3_comms::gicv3_comms_bw_if, 1, sc_core::SC_ONE_OR_MORE_BOUND > TlmGicTarget
Definition: evs.hh:75
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
tlm::tlm_base_initiator_socket::bind
virtual void bind(base_target_socket_type &s)
Definition: initiator_socket.hh:121
gem5::fastmodel::SignalReceiver::onChange
void onChange(OnChangeFunc func)
Definition: signal_receiver.hh:70
gem5::fastmodel::ScxEvsCortexA76::redist
std::vector< std::unique_ptr< TlmGicTarget > > redist
Definition: evs.hh:81
gem5::fastmodel::ScxEvsCortexA76::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:46
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::fastmodel::ScxEvsCortexA76::Base
typename Types::Base Base
Definition: evs.hh:64
gem5::fastmodel::ScxEvsCortexA76::vcpumntirq
std::vector< std::unique_ptr< SignalReceiver > > vcpumntirq
Definition: evs.hh:90
core.hh
gem5::fastmodel::ScxEvsCortexA76::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:115
gem5::fastmodel::ScxEvsCortexA76::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:69
logging.hh
gem5::fastmodel::CortexA76Cluster
Definition: cortex_a76.hh:83
gem5::fastmodel::ScxEvsCortexA76::SignalInitiator
amba_pv::signal_master_port< T > SignalInitiator
Definition: evs.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::fastmodel::ScxEvsCortexA76::Params
typename Types::Params Params
Definition: evs.hh:65
gem5::fastmodel::ScxEvsCortexA76::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:155
gem5::fastmodel::ScxEvsCortexA76::cnthvirq
std::vector< std::unique_ptr< SignalReceiver > > cnthvirq
Definition: evs.hh:84
gem5::fastmodel::SignalReceiver
Definition: signal_receiver.hh:47
gem5::fastmodel::ScxEvsCortexA76::ctidbgirq
std::vector< std::unique_ptr< SignalReceiver > > ctidbgirq
Definition: evs.hh:88
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmInterruptPinGen
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition: base_gic.hh:145

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