gem5  v21.2.0.0
evs.hh
Go to the documentation of this file.
1 /*
2  * Copyright 2019 Google, Inc.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are
6  * met: redistributions of source code must retain the above copyright
7  * notice, this list of conditions and the following disclaimer;
8  * redistributions in binary form must reproduce the above copyright
9  * notice, this list of conditions and the following disclaimer in the
10  * documentation and/or other materials provided with the distribution;
11  * neither the name of the copyright holders nor the names of its
12  * contributors may be used to endorse or promote products derived from
13  * this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__
30 
31 #include <memory>
32 
37 #include "mem/port_proxy.hh"
38 #include "params/FastModelScxEvsCortexA76x1.hh"
39 #include "params/FastModelScxEvsCortexA76x2.hh"
40 #include "params/FastModelScxEvsCortexA76x3.hh"
41 #include "params/FastModelScxEvsCortexA76x4.hh"
42 #include "scx_evs_CortexA76x1.h"
43 #include "scx_evs_CortexA76x2.h"
44 #include "scx_evs_CortexA76x3.h"
45 #include "scx_evs_CortexA76x4.h"
49 
50 namespace gem5
51 {
52 
53 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
54 namespace fastmodel
55 {
56 
57 class CortexA76Cluster;
58 
59 template <class Types>
61 {
62  private:
63  static const int CoreCount = Types::CoreCount;
64  using Base = typename Types::Base;
65  using Params = typename Types::Params;
66 
68 
71 
73  64, svp_gicv3_comms::gicv3_comms_fw_if,
74  svp_gicv3_comms::gicv3_comms_bw_if, 1,
76 
77  template <typename T>
78  using SignalInitiator = amba_pv::signal_master_port<T>;
79 
82 
93 
95 
96  const Params &params;
97 
98  public:
99  ScxEvsCortexA76(const Params &p) : ScxEvsCortexA76(p.name.c_str(), p) {}
100  ScxEvsCortexA76(const sc_core::sc_module_name &mod_name, const Params &p);
101 
102  void before_end_of_elaboration() override;
103  Port &gem5_getPort(const std::string &if_name, int idx) override;
104 
105  void
107  {
108  Base::end_of_elaboration();
109  Base::start_of_simulation();
110  }
111  void start_of_simulation() override {}
112 
113  void sendFunc(PacketPtr pkt) override;
114 
115  void setClkPeriod(Tick clk_period) override;
116 
117  void setSysCounterFrq(uint64_t sys_counter_frq) override;
118 
119  void setCluster(SimObject *cluster) override;
120 
121  void setResetAddr(int core, Addr addr, bool secure) override;
122 };
123 
125 {
126  using Base = scx_evs_CortexA76x1;
127  using Params = FastModelScxEvsCortexA76x1Params;
128  static const int CoreCount = 1;
129 };
131 extern template class ScxEvsCortexA76<ScxEvsCortexA76x1Types>;
132 
134 {
135  using Base = scx_evs_CortexA76x2;
136  using Params = FastModelScxEvsCortexA76x2Params;
137  static const int CoreCount = 2;
138 };
140 extern template class ScxEvsCortexA76<ScxEvsCortexA76x2Types>;
141 
143 {
144  using Base = scx_evs_CortexA76x3;
145  using Params = FastModelScxEvsCortexA76x3Params;
146  static const int CoreCount = 3;
147 };
149 extern template class ScxEvsCortexA76<ScxEvsCortexA76x3Types>;
150 
152 {
153  using Base = scx_evs_CortexA76x4;
154  using Params = FastModelScxEvsCortexA76x4Params;
155  static const int CoreCount = 4;
156 };
158 extern template class ScxEvsCortexA76<ScxEvsCortexA76x4Types>;
159 
160 } // namespace fastmodel
161 } // namespace gem5
162 
163 #endif // __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__
gem5::fastmodel::ScxEvsCortexA76::end_of_elaboration
void end_of_elaboration() override
Definition: evs.hh:106
gem5::fastmodel::ScxEvsCortexA76x4Types::Base
scx_evs_CortexA76x4 Base
Definition: evs.hh:153
sc_core::SC_ONE_OR_MORE_BOUND
@ SC_ONE_OR_MORE_BOUND
Definition: sc_port.hh:69
gem5::fastmodel::ScxEvsCortexA76x2Types
Definition: evs.hh:133
gem5::fastmodel::ScxEvsCortexA76x3Types
Definition: evs.hh:142
gem5::fastmodel::ScxEvsCortexA76::rvbaraddr
std::vector< std::unique_ptr< SignalInitiator< uint64_t > > > rvbaraddr
Definition: evs.hh:92
gem5::fastmodel::ScxEvsCortexA76::cntpsirq
std::vector< std::unique_ptr< SignalReceiver > > cntpsirq
Definition: evs.hh:85
gem5::fastmodel::ScxEvsCortexA76::params
const Params & params
Definition: evs.hh:96
gem5::fastmodel::ScxEvsCortexA76::gem5CpuCluster
CortexA76Cluster * gem5CpuCluster
Definition: evs.hh:94
gem5::fastmodel::ScxEvsCortexA76::periphClockRateControl
ClockRateControlInitiatorSocket periphClockRateControl
Definition: evs.hh:70
gem5::fastmodel::ScxEvsCortexA76::setResetAddr
void setResetAddr(int core, Addr addr, bool secure) override
Definition: evs.cc:68
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::fastmodel::ScxEvsCortexA76::pmuirq
std::vector< std::unique_ptr< SignalReceiver > > pmuirq
Definition: evs.hh:89
gem5::fastmodel::ScxEvsCortexA76::cnthpirq
std::vector< std::unique_ptr< SignalReceiver > > cnthpirq
Definition: evs.hh:83
gem5::fastmodel::ScxEvsCortexA76::start_of_simulation
void start_of_simulation() override
Definition: evs.hh:111
gem5::fastmodel::ScxEvsCortexA76::SC_HAS_PROCESS
SC_HAS_PROCESS(ScxEvsCortexA76)
std::vector
STL vector class.
Definition: stl.hh:37
gem5::fastmodel::ScxEvsCortexA76x2Types::Base
scx_evs_CortexA76x2 Base
Definition: evs.hh:135
cpu.hh
gem5::fastmodel::ScxEvsCortexA76::commirq
std::vector< std::unique_ptr< SignalReceiver > > commirq
Definition: evs.hh:87
gem5::ClockRateControlInitiatorSocket
Definition: exported_clock_rate_control.hh:63
sc_event.hh
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::fastmodel::ScxEvsCortexA76::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:60
gem5::fastmodel::ScxEvsCortexA76::cntpnsirq
std::vector< std::unique_ptr< SignalReceiver > > cntpnsirq
Definition: evs.hh:91
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::fastmodel::ScxEvsCortexA76::before_end_of_elaboration
void before_end_of_elaboration() override
Definition: evs.cc:125
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::fastmodel::ScxEvsCortexA76
Definition: evs.hh:60
port_proxy.hh
gem5::fastmodel::ScxEvsCortexA76::CoreCount
static const int CoreCount
Definition: evs.hh:63
gem5::fastmodel::ScxEvsCortexA76::cntvirq
std::vector< std::unique_ptr< SignalReceiver > > cntvirq
Definition: evs.hh:86
gem5::fastmodel::ScxEvsCortexA76x3Types::Base
scx_evs_CortexA76x3 Base
Definition: evs.hh:144
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::fastmodel::ScxEvsCortexA76x4Types
Definition: evs.hh:151
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::fastmodel::ScxEvsCortexA76x1Types
Definition: evs.hh:124
gem5::fastmodel::ScxEvsCortexA76x1Types::Base
scx_evs_CortexA76x1 Base
Definition: evs.hh:126
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
name
const std::string & name()
Definition: trace.cc:49
gem5::fastmodel::ScxEvsCortexA76::ScxEvsCortexA76
ScxEvsCortexA76(const Params &p)
Definition: evs.hh:99
sc_module.hh
gem5::fastmodel::ScxEvsCortexA76::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:53
amba_ports.hh
gem5::fastmodel::ScxEvsCortexA76x3Types::Params
FastModelScxEvsCortexA76x3Params Params
Definition: evs.hh:145
gem5::fastmodel::ScxEvsCortexA76::redist
std::vector< std::unique_ptr< TlmGicTarget > > redist
Definition: evs.hh:81
gem5::fastmodel::ScxEvsCortexA76::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:46
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
sc_gem5::TlmInitiatorBaseWrapper
Definition: tlm_port_wrapper.hh:40
gem5::fastmodel::ScxEvsCortexA76::Base
typename Types::Base Base
Definition: evs.hh:64
gem5::fastmodel::ScxEvsCortexA76::vcpumntirq
std::vector< std::unique_ptr< SignalReceiver > > vcpumntirq
Definition: evs.hh:90
gem5::fastmodel::ScxEvsCortexA76x1Types::Params
FastModelScxEvsCortexA76x1Params Params
Definition: evs.hh:127
gem5::fastmodel::ScxEvsCortexA76::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:115
gem5::fastmodel::ScxEvsCortexA76::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:69
gem5::fastmodel::ScxEvsCortexA76x2Types::Params
FastModelScxEvsCortexA76x2Params Params
Definition: evs.hh:136
exported_clock_rate_control.hh
gem5::fastmodel::CortexA76Cluster
Definition: cortex_a76.hh:83
gem5::fastmodel::ScxEvsCortexA76x4Types::Params
FastModelScxEvsCortexA76x4Params Params
Definition: evs.hh:154
tlm_port_wrapper.hh
gem5::fastmodel::ScxEvsCortexA76::SignalInitiator
amba_pv::signal_master_port< T > SignalInitiator
Definition: evs.hh:78
signal_receiver.hh
gem5::fastmodel::ScxEvsCortexA76x1Types::CoreCount
static const int CoreCount
Definition: evs.hh:128
sc_gem5::TlmTargetBaseWrapper
Definition: tlm_port_wrapper.hh:44
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::fastmodel::ScxEvsCortexA76::Params
typename Types::Params Params
Definition: evs.hh:65
gem5::fastmodel::ScxEvsCortexA76::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:155
gem5::fastmodel::ScxEvsCortexA76::amba
AmbaInitiator amba
Definition: evs.hh:80
gem5::fastmodel::ScxEvsCortexA76::cnthvirq
std::vector< std::unique_ptr< SignalReceiver > > cnthvirq
Definition: evs.hh:84
gem5::fastmodel::ScxEvsCortexA76::ctidbgirq
std::vector< std::unique_ptr< SignalReceiver > > ctidbgirq
Definition: evs.hh:88
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

Generated on Tue Dec 21 2021 11:34:18 for gem5 by doxygen 1.8.17