gem5  v22.0.0.1
evs.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__
30 
31 #include <memory>
32 
38 #include "dev/reset_port.hh"
39 #include "mem/port_proxy.hh"
40 #include "params/FastModelScxEvsCortexA76x1.hh"
41 #include "params/FastModelScxEvsCortexA76x2.hh"
42 #include "params/FastModelScxEvsCortexA76x3.hh"
43 #include "params/FastModelScxEvsCortexA76x4.hh"
44 #include "scx_evs_CortexA76x1.h"
45 #include "scx_evs_CortexA76x2.h"
46 #include "scx_evs_CortexA76x3.h"
47 #include "scx_evs_CortexA76x4.h"
51 
52 namespace gem5
53 {
54 
55 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
56 namespace fastmodel
57 {
58 
59 class CortexA76Cluster;
60 
61 template <class Types>
63 {
64  private:
65  static const int CoreCount = Types::CoreCount;
66  using Base = typename Types::Base;
67  using Params = typename Types::Params;
68 
70 
73 
75  64, svp_gicv3_comms::gicv3_comms_fw_if,
76  svp_gicv3_comms::gicv3_comms_bw_if, 1,
78 
79  template <typename T>
80  using SignalInitiator = amba_pv::signal_master_port<T>;
81 
84 
97 
99 
101 
103 
105 
106  const Params &params;
107 
108  public:
109  ScxEvsCortexA76(const Params &p) : ScxEvsCortexA76(p.name.c_str(), p) {}
110  ScxEvsCortexA76(const sc_core::sc_module_name &mod_name, const Params &p);
111 
112  void before_end_of_elaboration() override;
113  Port &gem5_getPort(const std::string &if_name, int idx) override;
114 
115  void
117  {
118  Base::end_of_elaboration();
119  Base::start_of_simulation();
120  }
121  void start_of_simulation() override {}
122 
123  void sendFunc(PacketPtr pkt) override;
124 
125  void setClkPeriod(Tick clk_period) override;
126 
127  void setSysCounterFrq(uint64_t sys_counter_frq) override;
128 
129  void setCluster(SimObject *cluster) override;
130 
131  void setResetAddr(int core, Addr addr, bool secure) override;
132 
133  void requestReset();
134 };
135 
137 {
138  using Base = scx_evs_CortexA76x1;
139  using Params = FastModelScxEvsCortexA76x1Params;
140  static const int CoreCount = 1;
141 };
143 extern template class ScxEvsCortexA76<ScxEvsCortexA76x1Types>;
144 
146 {
147  using Base = scx_evs_CortexA76x2;
148  using Params = FastModelScxEvsCortexA76x2Params;
149  static const int CoreCount = 2;
150 };
152 extern template class ScxEvsCortexA76<ScxEvsCortexA76x2Types>;
153 
155 {
156  using Base = scx_evs_CortexA76x3;
157  using Params = FastModelScxEvsCortexA76x3Params;
158  static const int CoreCount = 3;
159 };
161 extern template class ScxEvsCortexA76<ScxEvsCortexA76x3Types>;
162 
164 {
165  using Base = scx_evs_CortexA76x4;
166  using Params = FastModelScxEvsCortexA76x4Params;
167  static const int CoreCount = 4;
168 };
170 extern template class ScxEvsCortexA76<ScxEvsCortexA76x4Types>;
171 
172 } // namespace fastmodel
173 } // namespace gem5
174 
175 #endif // __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__
gem5::fastmodel::ScxEvsCortexA76::end_of_elaboration
void end_of_elaboration() override
Definition: evs.hh:116
gem5::fastmodel::ScxEvsCortexA76x4Types::Base
scx_evs_CortexA76x4 Base
Definition: evs.hh:165
sc_core::SC_ONE_OR_MORE_BOUND
@ SC_ONE_OR_MORE_BOUND
Definition: sc_port.hh:69
gem5::fastmodel::ScxEvsCortexA76x2Types
Definition: evs.hh:145
gem5::fastmodel::ScxEvsCortexA76x3Types
Definition: evs.hh:154
gem5::fastmodel::ScxEvsCortexA76::rvbaraddr
std::vector< std::unique_ptr< SignalInitiator< uint64_t > > > rvbaraddr
Definition: evs.hh:94
gem5::fastmodel::ScxEvsCortexA76::cntpsirq
std::vector< std::unique_ptr< SignalReceiver > > cntpsirq
Definition: evs.hh:87
gem5::fastmodel::ScxEvsCortexA76::params
const Params & params
Definition: evs.hh:106
gem5::fastmodel::ScxEvsCortexA76::gem5CpuCluster
CortexA76Cluster * gem5CpuCluster
Definition: evs.hh:104
gem5::fastmodel::ScxEvsCortexA76::requestReset
void requestReset()
Definition: evs.cc:75
gem5::fastmodel::ScxEvsCortexA76::periphClockRateControl
ClockRateControlInitiatorSocket periphClockRateControl
Definition: evs.hh:72
gem5::fastmodel::ScxEvsCortexA76::setResetAddr
void setResetAddr(int core, Addr addr, bool secure) override
Definition: evs.cc:68
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::fastmodel::ScxEvsCortexA76::pmuirq
std::vector< std::unique_ptr< SignalReceiver > > pmuirq
Definition: evs.hh:91
gem5::fastmodel::ScxEvsCortexA76::cnthpirq
std::vector< std::unique_ptr< SignalReceiver > > cnthpirq
Definition: evs.hh:85
gem5::fastmodel::ScxEvsCortexA76::start_of_simulation
void start_of_simulation() override
Definition: evs.hh:121
gem5::fastmodel::ScxEvsCortexA76::SC_HAS_PROCESS
SC_HAS_PROCESS(ScxEvsCortexA76)
std::vector
STL vector class.
Definition: stl.hh:37
signal_sender.hh
gem5::fastmodel::ScxEvsCortexA76x2Types::Base
scx_evs_CortexA76x2 Base
Definition: evs.hh:147
cpu.hh
gem5::fastmodel::ScxEvsCortexA76::commirq
std::vector< std::unique_ptr< SignalReceiver > > commirq
Definition: evs.hh:89
gem5::ClockRateControlInitiatorSocket
Definition: exported_clock_rate_control.hh:63
sc_event.hh
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::fastmodel::SignalSender
Definition: signal_sender.hh:45
gem5::fastmodel::ScxEvsCortexA76::top_reset
SignalSender top_reset
Definition: evs.hh:98
gem5::fastmodel::ScxEvsCortexA76::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:60
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::fastmodel::ScxEvsCortexA76::cntpnsirq
std::vector< std::unique_ptr< SignalReceiver > > cntpnsirq
Definition: evs.hh:93
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::fastmodel::ScxEvsCortexA76::before_end_of_elaboration
void before_end_of_elaboration() override
Definition: evs.cc:155
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::fastmodel::ScxEvsCortexA76
Definition: evs.hh:62
port_proxy.hh
gem5::fastmodel::ScxEvsCortexA76::CoreCount
static const int CoreCount
Definition: evs.hh:65
gem5::fastmodel::ScxEvsCortexA76::cntvirq
std::vector< std::unique_ptr< SignalReceiver > > cntvirq
Definition: evs.hh:88
gem5::fastmodel::ScxEvsCortexA76x3Types::Base
scx_evs_CortexA76x3 Base
Definition: evs.hh:156
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::fastmodel::ScxEvsCortexA76x4Types
Definition: evs.hh:163
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::fastmodel::ScxEvsCortexA76::poweron_reset
std::vector< std::unique_ptr< SignalSender > > poweron_reset
Definition: evs.hh:96
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::fastmodel::ScxEvsCortexA76x1Types
Definition: evs.hh:136
gem5::fastmodel::ScxEvsCortexA76x1Types::Base
scx_evs_CortexA76x1 Base
Definition: evs.hh:138
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
name
const std::string & name()
Definition: trace.cc:49
gem5::fastmodel::ScxEvsCortexA76::ScxEvsCortexA76
ScxEvsCortexA76(const Params &p)
Definition: evs.hh:109
sc_module.hh
gem5::fastmodel::ScxEvsCortexA76::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:53
amba_ports.hh
gem5::fastmodel::ScxEvsCortexA76x3Types::Params
FastModelScxEvsCortexA76x3Params Params
Definition: evs.hh:157
gem5::fastmodel::ScxEvsCortexA76::model_reset
ResetResponsePort< ScxEvsCortexA76 > model_reset
Definition: evs.hh:102
gem5::fastmodel::ScxEvsCortexA76::redist
std::vector< std::unique_ptr< TlmGicTarget > > redist
Definition: evs.hh:83
gem5::ResetResponsePort
Definition: reset_port.hh:46
gem5::fastmodel::ScxEvsCortexA76::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:46
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
sc_gem5::TlmInitiatorBaseWrapper
Definition: tlm_port_wrapper.hh:40
gem5::fastmodel::ScxEvsCortexA76::Base
typename Types::Base Base
Definition: evs.hh:66
gem5::fastmodel::ScxEvsCortexA76::vcpumntirq
std::vector< std::unique_ptr< SignalReceiver > > vcpumntirq
Definition: evs.hh:92
gem5::fastmodel::ScxEvsCortexA76x1Types::Params
FastModelScxEvsCortexA76x1Params Params
Definition: evs.hh:139
gem5::fastmodel::ScxEvsCortexA76::dbg_reset
SignalSender dbg_reset
Definition: evs.hh:100
gem5::fastmodel::ScxEvsCortexA76::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:145
gem5::fastmodel::ScxEvsCortexA76::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:71
gem5::fastmodel::ScxEvsCortexA76x2Types::Params
FastModelScxEvsCortexA76x2Params Params
Definition: evs.hh:148
exported_clock_rate_control.hh
gem5::fastmodel::CortexA76Cluster
Definition: cortex_a76.hh:83
gem5::fastmodel::ScxEvsCortexA76x4Types::Params
FastModelScxEvsCortexA76x4Params Params
Definition: evs.hh:166
tlm_port_wrapper.hh
reset_port.hh
gem5::fastmodel::ScxEvsCortexA76::SignalInitiator
amba_pv::signal_master_port< T > SignalInitiator
Definition: evs.hh:80
signal_receiver.hh
gem5::fastmodel::ScxEvsCortexA76x1Types::CoreCount
static const int CoreCount
Definition: evs.hh:140
sc_gem5::TlmTargetBaseWrapper
Definition: tlm_port_wrapper.hh:44
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::fastmodel::ScxEvsCortexA76::Params
typename Types::Params Params
Definition: evs.hh:67
gem5::fastmodel::ScxEvsCortexA76::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:185
gem5::fastmodel::ScxEvsCortexA76::amba
AmbaInitiator amba
Definition: evs.hh:82
gem5::fastmodel::ScxEvsCortexA76::cnthvirq
std::vector< std::unique_ptr< SignalReceiver > > cnthvirq
Definition: evs.hh:86
gem5::fastmodel::ScxEvsCortexA76::core_reset
std::vector< std::unique_ptr< SignalSender > > core_reset
Definition: evs.hh:95
gem5::fastmodel::ScxEvsCortexA76::ctidbgirq
std::vector< std::unique_ptr< SignalReceiver > > ctidbgirq
Definition: evs.hh:90
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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