gem5
v22.1.0.0
arch
arm
fastmodel
iris
tlb.hh
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* Copyright 2019 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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*/
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#ifndef __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
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#define __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
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#include "
arch/generic/tlb.hh
"
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#include "params/IrisTLB.hh"
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namespace
gem5
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{
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namespace
Iris
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{
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class
TLB
:
public
BaseTLB
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{
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public
:
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PARAMS
(IrisTLB)
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TLB
(const
Params
&
p
) :
BaseTLB
(
p
) {}
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void
demapPage
(
Addr
vaddr
, uint64_t asn)
override
{}
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void
flushAll
()
override
{}
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void
takeOverFrom
(
BaseTLB
*otlb)
override
{}
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Fault
translateFunctional
(
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const
RequestPtr
&req,
gem5::ThreadContext
*tc,
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BaseMMU::Mode
mode
)
override
;
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Fault
translateAtomic
(
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const
RequestPtr
&req,
gem5::ThreadContext
*tc,
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BaseMMU::Mode
mode
)
override
;
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void
translateTiming
(
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const
RequestPtr
&req,
gem5::ThreadContext
*tc,
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BaseMMU::Translation
*translation,
BaseMMU::Mode
mode
)
override
;
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Fault
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finalizePhysical
(
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const
RequestPtr
&req,
gem5::ThreadContext
*tc,
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BaseMMU::Mode
mode
)
const override
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{
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return
NoFault
;
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}
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};
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}
// namespace Iris
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}
// namespace gem5
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#endif
// __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
gem5::BaseMMU::Translation
Definition:
mmu.hh:59
gem5::BaseMMU::Mode
Mode
Definition:
mmu.hh:56
gem5::BaseTLB
Definition:
tlb.hh:59
gem5::Iris::TLB
Definition:
tlb.hh:41
gem5::Iris::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode) override
Definition:
tlb.cc:58
gem5::Iris::TLB::translateTiming
void translateTiming(const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Definition:
tlb.cc:65
gem5::Iris::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition:
tlb.hh:49
gem5::Iris::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode) override
Definition:
tlb.cc:39
gem5::Iris::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
Definition:
tlb.hh:48
gem5::Iris::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
Definition:
tlb.hh:62
gem5::Iris::TLB::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Definition:
tlb.hh:47
gem5::SimObject::Params
SimObjectParams Params
Definition:
sim_object.hh:170
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:89
tlb.hh
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition:
misc_types.hh:74
gem5::MipsISA::vaddr
vaddr
Definition:
pra_constants.hh:278
gem5::VegaISA::p
Bitfield< 54 > p
Definition:
pagetable.hh:70
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:38
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition:
types.hh:248
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition:
request.hh:92
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:147
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition:
types.hh:253
PARAMS
#define PARAMS(type)
Definition:
sim_object.hh:371
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