gem5  v21.1.0.2
decoder.hh
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40 
41 #ifndef __ARCH_ARM_DECODER_HH__
42 #define __ARCH_ARM_DECODER_HH__
43 
44 #include <cassert>
45 
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/types.hh"
49 #include "arch/generic/decoder.hh"
50 #include "base/types.hh"
51 #include "cpu/static_inst.hh"
52 #include "debug/Decode.hh"
53 #include "enums/DecoderFlavor.hh"
54 
55 namespace gem5
56 {
57 
58 namespace ArmISA
59 {
60 
61 class ISA;
62 class Decoder : public InstDecoder
63 {
64  protected:
65  //The extended machine instruction being generated
67  uint32_t data;
68  bool bigThumb;
69  bool instDone;
70  bool outOfBytes;
71  int offset;
72  bool foundIt;
73  ITSTATE itBits;
74 
75  int fpscrLen;
77 
82  int sveLen;
83 
84  enums::DecoderFlavor decoderFlavor;
85 
89 
94  void process();
95 
100  void consumeBytes(int numBytes);
101 
115 
127  {
128  StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
129  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
130  si->getName(), mach_inst);
131  return si;
132  }
133 
134  public: // Decoder API
135  Decoder(ISA* isa = nullptr);
136 
138  void reset();
139 
147  bool needMoreBytes() const { return outOfBytes; }
148 
157  bool instReady() const { return instDone; }
158 
185  void moreBytes(const PCState &pc, Addr fetchPC);
186 
199 
205  void takeOverFrom(Decoder *old) {}
206 
207 
208  public: // ARM-specific decoder state manipulation
209  void
210  setContext(FPSCR fpscr)
211  {
212  fpscrLen = fpscr.len;
213  fpscrStride = fpscr.stride;
214  }
215 
216  void
217  setSveLen(uint8_t len)
218  {
219  sveLen = len;
220  }
221 };
222 
223 } // namespace ArmISA
224 } // namespace gem5
225 
226 #endif // __ARCH_ARM_DECODER_HH__
gem5::ArmISA::Decoder::data
uint32_t data
Definition: decoder.hh:67
gem5::ArmISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Decode a machine instruction without calling the cache.
gem5::ArmISA::Decoder::takeOverFrom
void takeOverFrom(Decoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:205
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::ArmISA::Decoder::setContext
void setContext(FPSCR fpscr)
Definition: decoder.hh:210
gem5::ArmISA::ISA
Definition: isa.hh:68
decode_cache.hh
gem5::ArmISA::Decoder::offset
int offset
Definition: decoder.hh:71
gem5::ArmISA::Decoder::fpscrLen
int fpscrLen
Definition: decoder.hh:75
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::ArmISA::Decoder::needMoreBytes
bool needMoreBytes() const
Can the decoder accept more data?
Definition: decoder.hh:147
gem5::ArmISA::Decoder::setSveLen
void setSveLen(uint8_t len)
Definition: decoder.hh:217
gem5::ArmISA::Decoder::foundIt
bool foundIt
Definition: decoder.hh:72
gem5::ArmISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:87
types.hh
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC)
Feed data to the decoder.
Definition: decoder.cc:155
decoder.hh
gem5::ArmISA::Decoder::instDone
bool instDone
Definition: decoder.hh:69
gem5::InstDecoder
Definition: decoder.hh:39
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::Decoder::instReady
bool instReady() const
Is an instruction ready to be decoded?
Definition: decoder.hh:157
gem5::ArmISA::Decoder::sveLen
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition: decoder.hh:82
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::ArmISA::Decoder::consumeBytes
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:146
gem5::ArmISA::Decoder::decoderFlavor
enums::DecoderFlavor decoderFlavor
Definition: decoder.hh:84
gem5::ArmISA::Decoder::fpscrStride
int fpscrStride
Definition: decoder.hh:76
gem5::ArmISA::Decoder
Definition: decoder.hh:62
gem5::ArmISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:66
static_inst.hh
gem5::ArmISA::Decoder::process
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:79
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::Decoder::bigThumb
bool bigThumb
Definition: decoder.hh:68
types.hh
misc.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::Decoder::reset
void reset()
Reset the decoders internal state.
Definition: decoder.cc:68
gem5::ArmISA::Decoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:70
gem5::ArmISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition: decoder.cc:57
gem5::ArmISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:126
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::Decoder::itBits
ITSTATE itBits
Definition: decoder.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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