decoder.hh

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/*
 * Copyright (c) 2013-2014, 2021 Arm Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2012 Google
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_ARM_DECODER_HH__
#define __ARCH_ARM_DECODER_HH__
 
#include <cassert>
 
#include "arch/arm/regs/misc.hh"
#include "arch/arm/types.hh"
#include "arch/generic/decode_cache.hh"
#include "arch/generic/decoder.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
#include "enums/DecoderFlavor.hh"
#include "params/ArmDecoder.hh"
 
namespace gem5
{
 
class BaseISA;
 
namespace ArmISA
{
 
class Decoder : public InstDecoder
{
  public: // Public decoder parameters
    const bool dvmEnabled;
 
  protected:
    //The extended machine instruction being generated
    ExtMachInst emi;
    uint32_t data;
    bool bigThumb;
    int offset;
    bool foundIt;
    ITSTATE itBits;
 
    int fpscrLen;
    int fpscrStride;
 
    int sveLen;
 
    int smeLen;
 
    enums::DecoderFlavor decoderFlavor;
 
    static GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;
    friend class GenericISA::BasicDecodeCache<Decoder, ExtMachInst>;
 
    void process();
 
    void consumeBytes(int numBytes);
 
    StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
    StaticInstPtr
    decode(ExtMachInst mach_inst, Addr addr)
    {
        StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
        DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
                si->getName(), mach_inst);
        si->size((!emi.thumb || emi.bigThumb) ? 4 : 2);
        return si;
    }
 
  public: // Decoder API
    Decoder(const ArmDecoderParams &params);
 
    void reset() override;
 
    void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
 
    StaticInstPtr decode(PCStateBase &pc) override;
 
  public: // ARM-specific decoder state manipulation
    void
    setContext(FPSCR fpscr)
    {
        fpscrLen = fpscr.len;
        fpscrStride = fpscr.stride;
    }
 
    void
    setSveLen(uint8_t len)
    {
        sveLen = len;
    }
 
    void
    setSmeLen(uint8_t len)
    {
        smeLen = len;
    }
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif // __ARCH_ARM_DECODER_HH__