gem5  v21.1.0.2
Public Member Functions | Private Attributes | List of all members
gem5::DramRotGen Class Reference

#include <dram_rot_gen.hh>

Inheritance diagram for gem5::DramRotGen:
gem5::DramGen gem5::RandomGen gem5::StochasticGen gem5::BaseGen

Public Member Functions

 DramRotGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, enums::AddrMap addr_mapping, unsigned int nbr_of_ranks, unsigned int max_seq_count_per_rank)
 Create a DRAM address sequence generator. More...
 
PacketPtr getNextPacket ()
 Get the next generated packet. More...
 
- Public Member Functions inherited from gem5::DramGen
 DramGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, enums::AddrMap addr_mapping, unsigned int nbr_of_ranks)
 Create a DRAM address sequence generator. More...
 
void genStartAddr (unsigned int new_bank, unsigned int new_rank)
 Insert bank, rank, and column bits into packed address to create address for 1st command in a series. More...
 
- Public Member Functions inherited from gem5::RandomGen
 RandomGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit)
 Create a random address sequence generator. More...
 
void enter ()
 Enter this generator state. More...
 
PacketPtr getNextPacket ()
 Get the next generated packet. More...
 
Tick nextPacketTick (bool elastic, Tick delay) const
 Determine the tick when the next packet is available. More...
 
- Public Member Functions inherited from gem5::StochasticGen
 StochasticGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit)
 
- Public Member Functions inherited from gem5::BaseGen
 BaseGen (SimObject &obj, RequestorID requestor_id, Tick _duration)
 Create a base generator. More...
 
virtual ~BaseGen ()
 
std::string name () const
 Get the name, useful for DPRINTFs. More...
 
virtual void exit ()
 Exit this generator state. More...
 

Private Attributes

const unsigned int maxSeqCountPerRank
 Number of command series issued before the rank is changed. More...
 
unsigned int nextSeqCount
 Next packet series count used to set rank and bank, and update isRead Incremented at the start of a new packet series
More...
 

Additional Inherited Members

- Public Attributes inherited from gem5::BaseGen
const Tick duration
 Time to spend in this state. More...
 
- Protected Member Functions inherited from gem5::BaseGen
PacketPtr getPacket (Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
 Generate a new request and associated packet. More...
 
- Protected Attributes inherited from gem5::DramGen
const unsigned int numSeqPkts
 Number of sequential DRAM packets to be generated per cpu request. More...
 
unsigned int countNumSeqPkts
 Track number of sequential packets generated for a request
More...
 
Addr addr
 Address of request. More...
 
bool isRead
 Remember type of requests to be generated in series. More...
 
const unsigned int pageSize
 Page size of DRAM. More...
 
const unsigned int pageBits
 Number of page bits in DRAM address. More...
 
const unsigned int bankBits
 Number of bank bits in DRAM address. More...
 
const unsigned int blockBits
 Number of block bits in DRAM address. More...
 
const unsigned int nbrOfBanksDRAM
 Number of banks in DRAM. More...
 
const unsigned int nbrOfBanksUtil
 Number of banks to be utilized for a given configuration. More...
 
enums::AddrMap addrMapping
 Address mapping to be used. More...
 
const unsigned int rankBits
 Number of rank bits in DRAM address. More...
 
const unsigned int nbrOfRanks
 Number of ranks to be utilized for a given configuration. More...
 
- Protected Attributes inherited from gem5::RandomGen
Addr dataManipulated
 Counter to determine the amount of data manipulated. More...
 
- Protected Attributes inherited from gem5::StochasticGen
const Addr startAddr
 Start of address range. More...
 
const Addr endAddr
 End of address range. More...
 
const Addr blocksize
 Blocksize and address increment. More...
 
const Addr cacheLineSize
 Cache line size in the simulated system. More...
 
const Tick minPeriod
 Request generation period. More...
 
const Tick maxPeriod
 
const uint8_t readPercent
 Percent of generated transactions that should be reads. More...
 
const Addr dataLimit
 Maximum amount of data to manipulate. More...
 
- Protected Attributes inherited from gem5::BaseGen
const std::string _name
 Name to use for status and debug printing. More...
 
const RequestorID requestorId
 The RequestorID used for generating requests. More...
 

Detailed Description

Definition at line 56 of file dram_rot_gen.hh.

Constructor & Destructor Documentation

◆ DramRotGen()

gem5::DramRotGen::DramRotGen ( SimObject obj,
RequestorID  requestor_id,
Tick  _duration,
Addr  start_addr,
Addr  end_addr,
Addr  _blocksize,
Addr  cacheline_size,
Tick  min_period,
Tick  max_period,
uint8_t  read_percent,
Addr  data_limit,
unsigned int  num_seq_pkts,
unsigned int  page_size,
unsigned int  nbr_of_banks_DRAM,
unsigned int  nbr_of_banks_util,
enums::AddrMap  addr_mapping,
unsigned int  nbr_of_ranks,
unsigned int  max_seq_count_per_rank 
)
inline

Create a DRAM address sequence generator.

This sequence generator will rotate through: 1) Banks per rank 2) Command type (if applicable) 3) Ranks per channel

Parameters
objSimObject owning this sequence generator
requestor_idRequestorID related to the memory requests
_durationduration of this state before transitioning
start_addrStart address
end_addrEnd address
_blocksizeSize used for transactions injected
cacheline_sizecache line size in the system
min_periodLower limit of random inter-transaction time
max_periodUpper limit of random inter-transaction time
read_percentPercent of transactions that are reads
data_limitUpper limit on how much data to read/write
num_seq_pktsNumber of packets per stride, each of _blocksize
page_sizePage size (bytes) used in the DRAM
nbr_of_banks_DRAMTotal number of banks in DRAM
nbr_of_banks_utilNumber of banks to utilized, for N banks, we will use banks: 0->(N-1)
nbr_of_ranksNumber of ranks utilized,
addr_mappingAddress mapping to be used, assumes single channel system

Definition at line 88 of file dram_rot_gen.hh.

References gem5::BaseGen::_name, fatal, and gem5::StochasticGen::readPercent.

Member Function Documentation

◆ getNextPacket()

PacketPtr gem5::DramRotGen::getNextPacket ( )
virtual

Member Data Documentation

◆ maxSeqCountPerRank

const unsigned int gem5::DramRotGen::maxSeqCountPerRank
private

Number of command series issued before the rank is changed.

Should rotate to the next rank after rorating throughall the banks for each specified command type

Definition at line 121 of file dram_rot_gen.hh.

Referenced by getNextPacket().

◆ nextSeqCount

unsigned int gem5::DramRotGen::nextSeqCount
private

Next packet series count used to set rank and bank, and update isRead Incremented at the start of a new packet series

Definition at line 126 of file dram_rot_gen.hh.

Referenced by getNextPacket().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:27:30 for gem5 by doxygen 1.8.17