#include <dram_rot_gen.hh>

Inheritance diagram for gem5::DramRotGen:

Public Member Functions
	DramRotGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, enums::AddrMap addr_mapping, unsigned int nbr_of_ranks, unsigned int max_seq_count_per_rank)
	Create a DRAM address sequence generator.

PacketPtr	getNextPacket ()
	Get the next generated packet.

Public Member Functions inherited from gem5::DramGen
	DramGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, enums::AddrMap addr_mapping, unsigned int nbr_of_ranks)
	Create a DRAM address sequence generator.

void	genStartAddr (unsigned int new_bank, unsigned int new_rank)
	Insert bank, rank, and column bits into packed address to create address for 1st command in a series.

Public Member Functions inherited from gem5::RandomGen
	RandomGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit)
	Create a random address sequence generator.

void	enter ()
	Enter this generator state.

PacketPtr	getNextPacket ()
	Get the next generated packet.

Tick	nextPacketTick (bool elastic, Tick delay) const
	Determine the tick when the next packet is available.

Public Member Functions inherited from gem5::StochasticGen
	StochasticGen (SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit)

Public Member Functions inherited from gem5::BaseGen
	BaseGen (SimObject &obj, RequestorID requestor_id, Tick _duration)
	Create a base generator.

virtual	~BaseGen ()

std::string	name () const
	Get the name, useful for DPRINTFs.

virtual void	exit ()
	Exit this generator state.

Private Attributes
const unsigned int	maxSeqCountPerRank
	Number of command series issued before the rank is changed.

unsigned int	nextSeqCount
	Next packet series count used to set rank and bank, and update isRead Incremented at the start of a new packet series

Additional Inherited Members
Public Attributes inherited from gem5::BaseGen
const Tick	duration
	Time to spend in this state.

Protected Member Functions inherited from gem5::BaseGen
PacketPtr	getPacket (Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
	Generate a new request and associated packet.

Protected Attributes inherited from gem5::DramGen
const unsigned int	numSeqPkts
	Number of sequential DRAM packets to be generated per cpu request.

unsigned int	countNumSeqPkts
	Track number of sequential packets generated for a request

Addr	addr
	Address of request.

bool	isRead
	Remember type of requests to be generated in series.

const unsigned int	pageSize
	Page size of DRAM.

const unsigned int	pageBits
	Number of page bits in DRAM address.

const unsigned int	bankBits
	Number of bank bits in DRAM address.

const unsigned int	blockBits
	Number of block bits in DRAM address.

const unsigned int	nbrOfBanksDRAM
	Number of banks in DRAM.

const unsigned int	nbrOfBanksUtil
	Number of banks to be utilized for a given configuration.

enums::AddrMap	addrMapping
	Address mapping to be used.

const unsigned int	rankBits
	Number of rank bits in DRAM address.

const unsigned int	nbrOfRanks
	Number of ranks to be utilized for a given configuration.

Protected Attributes inherited from gem5::RandomGen
Addr	dataManipulated
	Counter to determine the amount of data manipulated.

Protected Attributes inherited from gem5::StochasticGen
const Addr	startAddr
	Start of address range.

const Addr	endAddr
	End of address range.

const Addr	blocksize
	Blocksize and address increment.

const Addr	cacheLineSize
	Cache line size in the simulated system.

const Tick	minPeriod
	Request generation period.

const Tick	maxPeriod

const uint8_t	readPercent
	Percent of generated transactions that should be reads.

const Addr	dataLimit
	Maximum amount of data to manipulate.

Protected Attributes inherited from gem5::BaseGen
const std::string	_name
	Name to use for status and debug printing.

const RequestorID	requestorId
	The RequestorID used for generating requests.

Detailed Description

Definition at line 56 of file dram_rot_gen.hh.

Constructor & Destructor Documentation

◆ DramRotGen()

gem5::DramRotGen::DramRotGen	(	SimObject &	obj,
		RequestorID	requestor_id,
		Tick	_duration,
		Addr	start_addr,
		Addr	end_addr,
		Addr	_blocksize,
		Addr	cacheline_size,
		Tick	min_period,
		Tick	max_period,
		uint8_t	read_percent,
		Addr	data_limit,
		unsigned int	num_seq_pkts,
		unsigned int	page_size,
		unsigned int	nbr_of_banks_DRAM,
		unsigned int	nbr_of_banks_util,
		enums::AddrMap	addr_mapping,
		unsigned int	nbr_of_ranks,
		unsigned int	max_seq_count_per_rank )

inline

Create a DRAM address sequence generator.

This sequence generator will rotate through: 1) Banks per rank 2) Command type (if applicable) 3) Ranks per channel

Parameters

obj	SimObject owning this sequence generator
requestor_id	RequestorID related to the memory requests
_duration	duration of this state before transitioning
start_addr	Start address
end_addr	End address
_blocksize	Size used for transactions injected
cacheline_size	cache line size in the system
min_period	Lower limit of random inter-transaction time
max_period	Upper limit of random inter-transaction time
read_percent	Percent of transactions that are reads
data_limit	Upper limit on how much data to read/write
num_seq_pkts	Number of packets per stride, each of _blocksize
page_size	Page size (bytes) used in the DRAM
nbr_of_banks_DRAM	Total number of banks in DRAM
nbr_of_banks_util	Number of banks to utilized, for N banks, we will use banks: 0->(N-1)
nbr_of_ranks	Number of ranks utilized,
addr_mapping	Address mapping to be used, assumes single channel system

Definition at line 88 of file dram_rot_gen.hh.

References gem5::BaseGen::_name, fatal, and gem5::StochasticGen::readPercent.

Member Function Documentation

◆ getNextPacket()

PacketPtr gem5::DramRotGen::getNextPacket ( )

virtual

Get the next generated packet.

Returns: A packet to be sent at the current tick

Reimplemented from gem5::DramGen.

Definition at line 51 of file dram_rot_gen.cc.

References gem5::DramGen::addr, gem5::DramGen::addrMapping, gem5::DramGen::bankBits, gem5::DramGen::blockBits, gem5::StochasticGen::blocksize, gem5::DramGen::countNumSeqPkts, gem5::RandomGen::dataManipulated, DPRINTF, gem5::DramGen::genStartAddr(), gem5::BaseGen::getPacket(), gem5::DramGen::isRead, maxSeqCountPerRank, gem5::DramGen::nbrOfBanksDRAM, gem5::DramGen::nbrOfBanksUtil, gem5::DramGen::nbrOfRanks, nextSeqCount, gem5::DramGen::numSeqPkts, gem5::DramGen::pageBits, gem5::DramGen::pageSize, gem5::DramGen::rankBits, gem5::StochasticGen::readPercent, gem5::MemCmd::ReadReq, gem5::replaceBits(), and gem5::MemCmd::WriteReq.

Member Data Documentation

◆ maxSeqCountPerRank

const unsigned int gem5::DramRotGen::maxSeqCountPerRank

private

Number of command series issued before the rank is changed.

Should rotate to the next rank after rorating throughall the banks for each specified command type

Definition at line 121 of file dram_rot_gen.hh.

Referenced by getNextPacket().

◆ nextSeqCount

unsigned int gem5::DramRotGen::nextSeqCount

private

Next packet series count used to set rank and bank, and update isRead Incremented at the start of a new packet series

Definition at line 126 of file dram_rot_gen.hh.

Referenced by getNextPacket().

The documentation for this class was generated from the following files:

cpu/testers/traffic_gen/dram_rot_gen.hh
cpu/testers/traffic_gen/dram_rot_gen.cc

Public Member Functions

Private Attributes

Additional Inherited Members