gem5  v21.1.0.2
dram_gen.cc
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37 
39 
40 #include <algorithm>
41 
42 #include "base/random.hh"
43 #include "base/trace.hh"
44 #include "debug/TrafficGen.hh"
45 #include "enums/AddrMap.hh"
46 
47 namespace gem5
48 {
49 
51  RequestorID requestor_id, Tick _duration,
52  Addr start_addr, Addr end_addr,
53  Addr _blocksize, Addr cacheline_size,
54  Tick min_period, Tick max_period,
55  uint8_t read_percent, Addr data_limit,
56  unsigned int num_seq_pkts, unsigned int page_size,
57  unsigned int nbr_of_banks_DRAM,
58  unsigned int nbr_of_banks_util,
59  enums::AddrMap addr_mapping,
60  unsigned int nbr_of_ranks)
61  : RandomGen(obj, requestor_id, _duration, start_addr, end_addr,
62  _blocksize, cacheline_size, min_period, max_period,
63  read_percent, data_limit),
64  numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
65  isRead(true), pageSize(page_size),
66  pageBits(floorLog2(page_size / _blocksize)),
67  bankBits(floorLog2(nbr_of_banks_DRAM)),
68  blockBits(floorLog2(_blocksize)),
69  nbrOfBanksDRAM(nbr_of_banks_DRAM),
70  nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping),
71  rankBits(floorLog2(nbr_of_ranks)),
72  nbrOfRanks(nbr_of_ranks)
73 {
74  if (nbr_of_banks_util > nbr_of_banks_DRAM)
75  fatal("Attempting to use more banks (%d) than "
76  "what is available (%d)\n",
77  nbr_of_banks_util, nbr_of_banks_DRAM);
78 }
79 
82 {
83  // if this is the first of the packets in series to be generated,
84  // start counting again
85  if (countNumSeqPkts == 0) {
87 
88  // choose if we generate a read or a write here
89  isRead = readPercent != 0 &&
90  (readPercent == 100 || random_mt.random(0, 100) < readPercent);
91 
92  assert((readPercent == 0 && !isRead) ||
93  (readPercent == 100 && isRead) ||
94  readPercent != 100);
95 
96  // pick a random bank
97  unsigned int new_bank =
98  random_mt.random<unsigned int>(0, nbrOfBanksUtil - 1);
99 
100  // pick a random rank
101  unsigned int new_rank =
102  random_mt.random<unsigned int>(0, nbrOfRanks - 1);
103 
104  // Generate the start address of the command series
105  // routine will update addr variable with bank, rank, and col
106  // bits updated for random traffic mode
107  genStartAddr(new_bank, new_rank);
108 
109  } else {
110  // increment the column by one
111  if (addrMapping == enums::RoRaBaCoCh ||
112  addrMapping == enums::RoRaBaChCo)
113  // Simply increment addr by blocksize to increment
114  // the column by one
115  addr += blocksize;
116 
117  else if (addrMapping == enums::RoCoRaBaCh) {
118  // Explicity increment the column bits
119  unsigned int new_col = ((addr / blocksize /
121  (pageSize / blocksize)) + 1;
123  blockBits + bankBits + rankBits, new_col);
124  }
125  }
126 
127  DPRINTF(TrafficGen, "DramGen::getNextPacket: %c to addr %x, "
128  "size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
130 
131  // create a new request packet
134 
135  // add the amount of data manipulated to the total
137 
138  // subtract the number of packets remained to be generated
139  --countNumSeqPkts;
140 
141  // return the generated packet
142  return pkt;
143 }
144 
145 void
146 DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
147 {
148  // start by picking a random address in the range
150 
151  // round down to start address of a block, i.e. a DRAM burst
152  addr -= addr % blocksize;
153 
154  // insert the bank bits at the right spot, and align the
155  // address to achieve the required hit length, this involves
156  // finding the appropriate start address such that all
157  // sequential packets target successive columns in the same
158  // page
159 
160  // for example, if we have a stride size of 192B, which means
161  // for LPDDR3 where burstsize = 32B we have numSeqPkts = 6,
162  // the address generated previously can be such that these
163  // 192B cross the page boundary, hence it needs to be aligned
164  // so that they all belong to the same page for page hit
165  unsigned int columns_per_page = pageSize / blocksize;
166 
167  // pick a random column, but ensure that there is room for
168  // numSeqPkts sequential columns in the same page
169  unsigned int new_col =
170  random_mt.random<unsigned int>(0, columns_per_page - numSeqPkts);
171 
172  if (addrMapping == enums::RoRaBaCoCh ||
173  addrMapping == enums::RoRaBaChCo) {
174  // Block bits, then page bits, then bank bits, then rank bits
176  blockBits + pageBits, new_bank);
177  replaceBits(addr, blockBits + pageBits - 1, blockBits, new_col);
178  if (rankBits != 0) {
180  blockBits + pageBits + bankBits, new_rank);
181  }
182  } else if (addrMapping == enums::RoCoRaBaCh) {
183  // Block bits, then bank bits, then rank bits, then page bits
184  replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
186  blockBits + bankBits + rankBits, new_col);
187  if (rankBits != 0) {
189  blockBits + bankBits, new_rank);
190  }
191  }
192 }
193 
194 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::RandomGen
The random generator is similar to the linear one, but does not generate sequential addresses.
Definition: random_gen.hh:60
gem5::DramGen::pageBits
const unsigned int pageBits
Number of page bits in DRAM address.
Definition: dram_gen.hh:127
gem5::StochasticGen::blocksize
const Addr blocksize
Blocksize and address increment.
Definition: base_gen.hh:157
dram_gen.hh
gem5::DramGen::addr
Addr addr
Address of request.
Definition: dram_gen.hh:118
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::RandomGen::dataManipulated
Addr dataManipulated
Counter to determine the amount of data manipulated.
Definition: random_gen.hh:106
random.hh
gem5::DramGen::bankBits
const unsigned int bankBits
Number of bank bits in DRAM address.
Definition: dram_gen.hh:130
gem5::DramGen::numSeqPkts
const unsigned int numSeqPkts
Number of sequential DRAM packets to be generated per cpu request.
Definition: dram_gen.hh:112
gem5::DramGen::pageSize
const unsigned int pageSize
Page size of DRAM.
Definition: dram_gen.hh:124
gem5::DramGen::nbrOfBanksDRAM
const unsigned int nbrOfBanksDRAM
Number of banks in DRAM.
Definition: dram_gen.hh:136
gem5::BaseGen::getPacket
PacketPtr getPacket(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
Generate a new request and associated packet.
Definition: base_gen.cc:55
gem5::StochasticGen::startAddr
const Addr startAddr
Start of address range.
Definition: base_gen.hh:151
gem5::Random::random
std::enable_if_t< std::is_integral< T >::value, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:90
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::StochasticGen::endAddr
const Addr endAddr
End of address range.
Definition: base_gen.hh:154
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::DramGen::countNumSeqPkts
unsigned int countNumSeqPkts
Track number of sequential packets generated for a request
Definition: dram_gen.hh:115
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::DramGen::nbrOfBanksUtil
const unsigned int nbrOfBanksUtil
Number of banks to be utilized for a given configuration.
Definition: dram_gen.hh:139
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::DramGen::addrMapping
enums::AddrMap addrMapping
Address mapping to be used.
Definition: dram_gen.hh:142
gem5::StochasticGen::readPercent
const uint8_t readPercent
Percent of generated transactions that should be reads.
Definition: base_gen.hh:169
gem5::TrafficGen
The traffic generator is a module that generates stimuli for the memory system, based on a collection...
Definition: traffic_gen.hh:70
gem5::floorLog2
static constexpr std::enable_if_t< std::is_integral< T >::value, int > floorLog2(T x)
Definition: intmath.hh:59
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::DramGen::genStartAddr
void genStartAddr(unsigned int new_bank, unsigned int new_rank)
Insert bank, rank, and column bits into packed address to create address for 1st command in a series.
Definition: dram_gen.cc:146
gem5::DramGen::DramGen
DramGen(SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, enums::AddrMap addr_mapping, unsigned int nbr_of_ranks)
Create a DRAM address sequence generator.
Definition: dram_gen.cc:50
gem5::DramGen::isRead
bool isRead
Remember type of requests to be generated in series.
Definition: dram_gen.hh:121
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
trace.hh
gem5::DramGen::getNextPacket
PacketPtr getNextPacket()
Get the next generated packet.
Definition: dram_gen.cc:81
gem5::DramGen::nbrOfRanks
const unsigned int nbrOfRanks
Number of ranks to be utilized for a given configuration.
Definition: dram_gen.hh:148
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::random_mt
Random random_mt
Definition: random.cc:99
gem5::DramGen::rankBits
const unsigned int rankBits
Number of rank bits in DRAM address.
Definition: dram_gen.hh:145
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::DramGen::blockBits
const unsigned int blockBits
Number of block bits in DRAM address.
Definition: dram_gen.hh:133

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