gem5  v21.1.0.2
dram_rot_gen.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012-2013, 2016-2017, 2019 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed here under. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
39 
40 #include <algorithm>
41 
42 #include "base/random.hh"
43 #include "base/trace.hh"
44 #include "debug/TrafficGen.hh"
45 #include "enums/AddrMap.hh"
46 
47 namespace gem5
48 {
49 
52 {
53  // if this is the first of the packets in series to be generated,
54  // start counting again
55  if (countNumSeqPkts == 0) {
57 
58  // choose if we generate a read or a write here
59  if (readPercent == 50) {
60  if ((nextSeqCount % nbrOfBanksUtil) == 0) {
61  // Change type after all banks have been rotated
62  // Otherwise, keep current value
63  isRead = !isRead;
64  }
65  } else {
66  // Set randomly based on percentage
67  isRead = readPercent != 0;
68  }
69 
70  assert((readPercent == 0 && !isRead) ||
71  (readPercent == 100 && isRead) ||
72  readPercent != 100);
73 
74  // Overwrite random bank value
75  // Rotate across banks
76  unsigned int new_bank = nextSeqCount % nbrOfBanksUtil;
77 
78  // Overwrite random rank value
79  // Will rotate to the next rank after rotating through all banks,
80  // for each specified command type.
81 
82  // Use modular function to ensure that calculated rank is within
83  // system limits after state transition
84  unsigned int new_rank = (nextSeqCount / maxSeqCountPerRank) %
85  nbrOfRanks;
86 
87  // Increment nextSeqCount
88  // Roll back to 0 after completing a full rotation across
89  // banks, command type, and ranks
90  nextSeqCount = (nextSeqCount + 1) %
92 
93  DPRINTF(TrafficGen, "DramRotGen::getNextPacket nextSeqCount: %d "
94  "new_rank: %d new_bank: %d\n",
95  nextSeqCount, new_rank, new_bank);
96 
97  // Generate the start address of the command series
98  // routine will update addr variable with bank, rank, and col
99  // bits updated for rotation scheme
100  genStartAddr(new_bank, new_rank);
101 
102  } else {
103  // increment the column by one
104  if (addrMapping == enums::RoRaBaCoCh ||
105  addrMapping == enums::RoRaBaChCo)
106  // Simply increment addr by blocksize to
107  // increment the column by one
108  addr += blocksize;
109 
110  else if (addrMapping == enums::RoCoRaBaCh) {
111  // Explicity increment the column bits
112 
113  unsigned int new_col = ((addr / blocksize /
115  (pageSize / blocksize)) + 1;
117  blockBits + bankBits + rankBits, new_col);
118  }
119  }
120 
121  DPRINTF(TrafficGen, "DramRotGen::getNextPacket: %c to addr %x, "
122  "size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
124 
125  // create a new request packet
128 
129  // add the amount of data manipulated to the total
131 
132  // subtract the number of packets remained to be generated
133  --countNumSeqPkts;
134 
135  // return the generated packet
136  return pkt;
137 }
138 
139 } // namespace gem5
gem5::DramGen::pageBits
const unsigned int pageBits
Number of page bits in DRAM address.
Definition: dram_gen.hh:127
gem5::StochasticGen::blocksize
const Addr blocksize
Blocksize and address increment.
Definition: base_gen.hh:157
gem5::DramGen::addr
Addr addr
Address of request.
Definition: dram_gen.hh:118
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::RandomGen::dataManipulated
Addr dataManipulated
Counter to determine the amount of data manipulated.
Definition: random_gen.hh:106
random.hh
gem5::DramGen::bankBits
const unsigned int bankBits
Number of bank bits in DRAM address.
Definition: dram_gen.hh:130
gem5::DramRotGen::maxSeqCountPerRank
const unsigned int maxSeqCountPerRank
Number of command series issued before the rank is changed.
Definition: dram_rot_gen.hh:121
gem5::DramGen::numSeqPkts
const unsigned int numSeqPkts
Number of sequential DRAM packets to be generated per cpu request.
Definition: dram_gen.hh:112
gem5::DramGen::pageSize
const unsigned int pageSize
Page size of DRAM.
Definition: dram_gen.hh:124
gem5::DramGen::nbrOfBanksDRAM
const unsigned int nbrOfBanksDRAM
Number of banks in DRAM.
Definition: dram_gen.hh:136
gem5::BaseGen::getPacket
PacketPtr getPacket(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
Generate a new request and associated packet.
Definition: base_gen.cc:55
gem5::PacketPtr
Packet * PacketPtr
Definition: thread_context.hh:75
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::DramGen::countNumSeqPkts
unsigned int countNumSeqPkts
Track number of sequential packets generated for a request
Definition: dram_gen.hh:115
gem5::DramRotGen::getNextPacket
PacketPtr getNextPacket()
Get the next generated packet.
Definition: dram_rot_gen.cc:51
gem5::DramGen::nbrOfBanksUtil
const unsigned int nbrOfBanksUtil
Number of banks to be utilized for a given configuration.
Definition: dram_gen.hh:139
dram_rot_gen.hh
gem5::DramGen::addrMapping
enums::AddrMap addrMapping
Address mapping to be used.
Definition: dram_gen.hh:142
gem5::StochasticGen::readPercent
const uint8_t readPercent
Percent of generated transactions that should be reads.
Definition: base_gen.hh:169
gem5::TrafficGen
The traffic generator is a module that generates stimuli for the memory system, based on a collection...
Definition: traffic_gen.hh:70
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::DramGen::genStartAddr
void genStartAddr(unsigned int new_bank, unsigned int new_rank)
Insert bank, rank, and column bits into packed address to create address for 1st command in a series.
Definition: dram_gen.cc:146
gem5::DramGen::isRead
bool isRead
Remember type of requests to be generated in series.
Definition: dram_gen.hh:121
trace.hh
gem5::DramGen::nbrOfRanks
const unsigned int nbrOfRanks
Number of ranks to be utilized for a given configuration.
Definition: dram_gen.hh:148
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::DramRotGen::nextSeqCount
unsigned int nextSeqCount
Next packet series count used to set rank and bank, and update isRead Incremented at the start of a n...
Definition: dram_rot_gen.hh:126
gem5::DramGen::rankBits
const unsigned int rankBits
Number of rank bits in DRAM address.
Definition: dram_gen.hh:145
gem5::DramGen::blockBits
const unsigned int blockBits
Number of block bits in DRAM address.
Definition: dram_gen.hh:133

Generated on Tue Sep 21 2021 12:25:09 for gem5 by doxygen 1.8.17