gem5  v21.1.0.2
cortex_r52.cc
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27 
29 
31 #include "base/logging.hh"
32 #include "dev/arm/base_gic.hh"
34 
35 namespace gem5
36 {
37 
38 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
39 namespace fastmodel
40 {
41 
42 void
44 {
45  cluster = _cluster;
46  num = _num;
47 
48  set_evs_param("CFGEND", params().CFGEND);
49  set_evs_param("CFGTE", params().CFGTE);
50  set_evs_param("RVBARADDR", params().RVBARADDR);
51  set_evs_param("ase-present", params().ase_present);
52  set_evs_param("dcache-size", params().dcache_size);
53  set_evs_param("flash.enable", params().flash_enable);
54  set_evs_param("icache-size", params().icache_size);
55  set_evs_param("llpp.base", params().llpp_base);
56  set_evs_param("llpp.size", params().llpp_size);
57  set_evs_param("max_code_cache_mb", params().max_code_cache_mb);
58  set_evs_param("min_sync_level", params().min_sync_level);
59  set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT);
60  // Use uint32_t, since the model doesn't like setting these as uint8_t.
61  set_evs_param<uint32_t>("semihosting-ARM_SVC",
62  params().semihosting_ARM_SVC);
63  set_evs_param<uint32_t>("semihosting-T32_HLT",
64  params().semihosting_T32_HLT);
65  set_evs_param<uint32_t>("semihosting-Thumb_SVC",
66  params().semihosting_Thumb_SVC);
67  set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line);
68  set_evs_param("semihosting-cwd", params().semihosting_cwd);
69  set_evs_param("semihosting-enable", params().semihosting_enable);
70  set_evs_param("semihosting-heap_base", params().semihosting_heap_base);
71  set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit);
72  set_evs_param("semihosting-stack_base", params().semihosting_stack_base);
73  set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit);
74  set_evs_param("tcm.a.enable", params().tcm_a_enable);
75  set_evs_param("tcm.a.size", params().tcm_a_size);
76  set_evs_param("tcm.b.size", params().tcm_b_size);
77  set_evs_param("tcm.c.size", params().tcm_c_size);
78  set_evs_param("vfp-dp-present", params().vfp_dp_present);
79  set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
80 }
81 
82 Port &
83 CortexR52::getPort(const std::string &if_name, PortID idx)
84 {
85  if (if_name == "ppi") {
86  // Since PPIs are indexed both by core and by number, modify the name
87  // to hold the core number.
88  return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
89  } else if (if_name == "amba" || if_name == "llpp" || if_name == "flash") {
90  // Since these ports are scalar per core, use the core number as the
91  // index. Also verify that that index is not being used.
92  assert(idx == InvalidPortID);
93  return evs->gem5_getPort(if_name, num);
94  } else {
95  return SimObject::getPort(if_name, idx);
96  }
97 }
98 
100  SimObject(p), cores(p.cores), evs(p.evs)
101 {
102  for (int i = 0; i < p.cores.size(); i++)
103  p.cores[i]->setCluster(this, i);
104 
105  Iris::BaseCpuEvs *e = dynamic_cast<Iris::BaseCpuEvs *>(evs);
106  panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
107  e->setCluster(this);
108 
109  set_evs_param("core.CLUSTER_ID", params().CLUSTER_ID);
110  set_evs_param("core.DBGROMADDR", params().DBGROMADDR);
111  set_evs_param("core.DBGROMADDRV", params().DBGROMADDRV);
112  set_evs_param("core.PERIPHBASE", params().PERIPHBASE);
113  set_evs_param("core.cluster_utid", params().cluster_utid);
114  set_evs_param("core.cpi_div", params().cpi_div);
115  set_evs_param("core.cpi_mul", params().cpi_mul);
116  set_evs_param("core.dcache-prefetch_enabled",
117  params().dcache_prefetch_enabled);
118  set_evs_param("core.dcache-read_access_latency",
119  params().dcache_read_access_latency);
120  set_evs_param("core.dcache-state_modelled",
121  params().dcache_state_modelled);
122  set_evs_param("core.dcache-write_access_latency",
123  params().dcache_write_access_latency);
124  set_evs_param("core.flash_protection_enable_at_reset",
125  params().flash_protection_enable_at_reset);
126  set_evs_param("core.has_flash_protection", params().has_flash_protection);
127  set_evs_param("core.icache-prefetch_enabled",
128  params().icache_prefetch_enabled);
129  set_evs_param("core.icache-read_access_latency",
130  params().icache_read_access_latency);
131  set_evs_param("core.icache-state_modelled",
132  params().icache_state_modelled);
133  set_evs_param("core.memory.ext_slave_base",
134  params().memory_ext_slave_base);
135  set_evs_param("core.memory.flash_base", params().memory_flash_base);
136  set_evs_param("core.memory.flash_size", params().memory_flash_size);
137  // Use uint32_t, since the model doesn't like setting these as uint8_t.
138  set_evs_param<uint32_t>("core.num_protection_regions_s1",
139  params().num_protection_regions_s1);
140  set_evs_param<uint32_t>("core.num_protection_regions_s2",
141  params().num_protection_regions_s2);
142  set_evs_param("core.num_spi", params().num_spi);
143  set_evs_param("core.ram_protection_enable_at_reset",
144  params().ram_protection_enable_at_reset);
145  set_evs_param("core.has_export_m_port", params().has_export_m_port);
146 }
147 
148 Port &
149 CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
150 {
151  if (if_name == "spi") {
152  return evs->gem5_getPort(if_name, idx);
153  } else {
154  return SimObject::getPort(if_name, idx);
155  }
156 }
157 
158 } // namespace fastmodel
159 } // namespace gem5
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::fastmodel::CortexR52Cluster::evs
sc_core::sc_module * evs
Definition: cortex_r52.hh:83
gem5::fastmodel::CortexR52::setCluster
void setCluster(CortexR52Cluster *_cluster, int _num)
Definition: cortex_r52.cc:43
gem5::fastmodel::CortexR52::cluster
CortexR52Cluster * cluster
Definition: cortex_r52.hh:61
gem5_to_tlm.hh
gem5::fastmodel::CortexR52::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:83
base_gic.hh
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::fastmodel::CortexR52Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:88
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
cpu.hh
gem5::Iris::BaseCPU::evs
sc_core::sc_module * evs
Definition: cpu.hh:90
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::fastmodel::CortexR52::num
int num
Definition: cortex_r52.hh:62
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
cortex_r52.hh
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::fastmodel::CortexR52Cluster
Definition: cortex_r52.hh:79
gem5::fastmodel::CortexR52::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:105
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
sc_core::sc_module::gem5_getPort
virtual gem5::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
logging.hh
gem5::fastmodel::CortexR52Cluster::CortexR52Cluster
CortexR52Cluster(const Params &p)
Definition: cortex_r52.cc:99
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::fastmodel::CortexR52Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:149

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