gem5  v21.1.0.2
pl011.cc
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1 /*
2  * Copyright (c) 2010, 2015 ARM Limited
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4  *
5  * The license below extends only to copyright in the software and shall
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14  * Copyright (c) 2005 The Regents of The University of Michigan
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40 
41 #include "dev/arm/pl011.hh"
42 
43 #include "base/trace.hh"
44 #include "debug/Checkpoint.hh"
45 #include "debug/Uart.hh"
46 #include "dev/arm/amba_device.hh"
47 #include "dev/arm/base_gic.hh"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 #include "params/Pl011.hh"
51 #include "sim/sim_exit.hh"
52 
53 namespace gem5
54 {
55 
56 Pl011::Pl011(const Pl011Params &p)
57  : Uart(p, 0x1000),
58  intEvent([this]{ generateInterrupt(); }, name()),
59  control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
60  imsc(0), rawInt(0),
61  endOnEOT(p.end_on_eot), interrupt(p.interrupt->get()),
62  intDelay(p.int_delay)
63 {
64 }
65 
66 Tick
68 {
69  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
70  assert(pkt->getSize() <= 4);
71 
72  Addr daddr = pkt->getAddr() - pioAddr;
73 
74  DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
75 
76  // use a temporary data since the uart registers are read/written with
77  // different size operations
78  //
79  uint32_t data = 0;
80 
81  switch(daddr) {
82  case UART_DR:
83  data = 0;
84  if (device->dataAvailable()) {
85  data = device->readData();
86  // Since we don't simulate a FIFO for incoming data, we
87  // assume it's empty and clear RXINTR and RTINTR.
89  if (device->dataAvailable()) {
90  DPRINTF(Uart, "Re-raising interrupt due to more data "
91  "after UART_DR read\n");
92  dataAvailable();
93  }
94  }
95  break;
96  case UART_RSR:
97  data = 0x0; // We never have errors
98  break;
99  case UART_FR:
100  data =
101  UART_FR_CTS | // Clear To Send
102  // Given we do not simulate a FIFO we are either empty or full.
104  UART_FR_TXFE; // TX FIFO empty
105 
106  DPRINTF(Uart,
107  "Reading FR register as %#x rawInt=0x%x "
108  "imsc=0x%x maskInt=0x%x\n",
109  data, rawInt, imsc, maskInt());
110  break;
111  case UART_CR:
112  data = control;
113  break;
114  case UART_IBRD:
115  data = ibrd;
116  break;
117  case UART_FBRD:
118  data = fbrd;
119  break;
120  case UART_LCRH:
121  data = lcrh;
122  break;
123  case UART_IFLS:
124  data = ifls;
125  break;
126  case UART_IMSC:
127  data = imsc;
128  break;
129  case UART_RIS:
130  data = rawInt;
131  DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
132  break;
133  case UART_MIS:
134  DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
135  data = maskInt();
136  break;
137  case UART_DMACR:
138  warn("PL011: DMA not supported\n");
139  data = 0x0; // DMA never enabled
140  break;
141  default:
142  if (readId(pkt, AMBA_ID, pioAddr)) {
143  // Hack for variable size accesses
144  data = pkt->getUintX(ByteOrder::little);
145  break;
146  }
147 
148  panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
149  break;
150  }
151 
152  pkt->setUintX(data, ByteOrder::little);
153  pkt->makeAtomicResponse();
154  return pioDelay;
155 }
156 
157 Tick
159 {
160 
161  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
162  assert(pkt->getSize() <= 4);
163 
164  Addr daddr = pkt->getAddr() - pioAddr;
165 
166  DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
167  pkt->getLE<uint8_t>(), pkt->getSize());
168 
169  // use a temporary data since the uart registers are read/written with
170  // different size operations
171  //
172  const uint32_t data = pkt->getUintX(ByteOrder::little);
173 
174  switch (daddr) {
175  case UART_DR:
176  if ((data & 0xFF) == 0x04 && endOnEOT)
177  exitSimLoop("UART received EOT", 0);
178 
179  device->writeData(data & 0xFF);
180  // We're supposed to clear TXINTR when this register is
181  // written to, however. since we're also infinitely fast, we
182  // need to immediately raise it again.
185  break;
186  case UART_ECR: // clears errors, ignore
187  break;
188  case UART_CR:
189  control = data;
190  break;
191  case UART_IBRD:
192  ibrd = data;
193  break;
194  case UART_FBRD:
195  fbrd = data;
196  break;
197  case UART_LCRH:
198  lcrh = data;
199  break;
200  case UART_IFLS:
201  ifls = data;
202  break;
203  case UART_IMSC:
204  DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
206  break;
207 
208  case UART_ICR:
209  DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
211  if (device->dataAvailable()) {
212  DPRINTF(Uart, "Re-raising interrupt due to more data after "
213  "UART_ICR write\n");
214  dataAvailable();
215  }
216  break;
217  case UART_DMACR:
218  // DMA is not supported, so panic if anyome tries to enable it.
219  // Bits 0, 1, 2 enables DMA on RX, TX, ERR respectively, others res0.
220  if (data & 0x7) {
221  panic("Tried to enable DMA on PL011\n");
222  }
223  warn("PL011: DMA not supported\n");
224  break;
225  default:
226  panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
227  break;
228  }
229  pkt->makeAtomicResponse();
230  return pioDelay;
231 }
232 
233 void
235 {
236  /*@todo ignore the fifo, just say we have data now
237  * We might want to fix this, or we might not care */
238  DPRINTF(Uart, "Data available, scheduling interrupt\n");
240 }
241 
242 void
244 {
245  DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
246  imsc, rawInt, maskInt());
247 
248  if (maskInt()) {
249  interrupt->raise();
250  DPRINTF(Uart, " -- Generated\n");
251  }
252 }
253 
254 void
255 Pl011::setInterrupts(uint16_t ints, uint16_t mask)
256 {
257  const bool old_ints(!!maskInt());
258 
259  imsc = mask;
260  rawInt = ints;
261 
262  if (!old_ints && maskInt()) {
263  if (!intEvent.scheduled())
265  } else if (old_ints && !maskInt()) {
266  interrupt->clear();
267  }
268 }
269 
270 
271 
272 void
274 {
275  DPRINTF(Checkpoint, "Serializing Arm PL011\n");
281 
282  // Preserve backwards compatibility by giving these silly names.
283  paramOut(cp, "imsc_serial", imsc);
284  paramOut(cp, "rawInt_serial", rawInt);
285 }
286 
287 void
289 {
290  DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
291 
297 
298  // Preserve backwards compatibility by giving these silly names.
299  paramIn(cp, "imsc_serial", imsc);
300  paramIn(cp, "rawInt_serial", rawInt);
301 }
302 
303 } // namespace gem5
gem5::Pl011::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pl011.cc:288
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Pl011::UART_LCRH
static const int UART_LCRH
Definition: pl011.hh:131
gem5::Pl011::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: pl011.cc:158
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
warn
#define warn(...)
Definition: logging.hh:245
gem5::Pl011::imsc
uint16_t imsc
interrupt mask register.
Definition: pl011.hh:171
gem5::Pl011::clearInterrupts
void clearInterrupts(uint16_t ints)
Convenience function to clear interrupts.
Definition: pl011.hh:110
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:334
gem5::Pl011::UART_IBRD
static const int UART_IBRD
Definition: pl011.hh:129
data
const char data[]
Definition: circlebuf.test.cc:48
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::Pl011::AMBA_ID
static const uint64_t AMBA_ID
Definition: pl011.hh:119
gem5::Pl011::UART_FR_TXFE
static const int UART_FR_TXFE
Definition: pl011.hh:128
amba_device.hh
gem5::CheckpointIn
Definition: serialize.hh:68
base_gic.hh
gem5::Pl011::UART_FBRD
static const int UART_FBRD
Definition: pl011.hh:130
gem5::Pl011::dataAvailable
void dataAvailable() override
Inform the uart that there is data available.
Definition: pl011.cc:234
gem5::Pl011::UART_RSR
static const int UART_RSR
Definition: pl011.hh:121
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::Pl011::Pl011
Pl011(const Pl011Params &p)
Definition: pl011.cc:56
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::Pl011::UART_CR
static const int UART_CR
Definition: pl011.hh:132
gem5::SerialDevice::dataAvailable
virtual bool dataAvailable() const =0
Check if there is pending data from the serial device.
sim_exit.hh
gem5::Pl011::lcrh
uint16_t lcrh
Line control register.
Definition: pl011.hh:164
gem5::Pl011::setInterruptMask
void setInterruptMask(uint16_t mask)
Convenience function to update the interrupt mask.
Definition: pl011.hh:96
gem5::exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
packet.hh
gem5::Pl011::UART_MIS
static const int UART_MIS
Definition: pl011.hh:136
gem5::Pl011::ibrd
uint16_t ibrd
integer baud rate divisor.
Definition: pl011.hh:160
gem5::Pl011::UART_ECR
static const int UART_ECR
Definition: pl011.hh:122
gem5::SerialDevice::writeData
virtual void writeData(uint8_t c)=0
Transmit a character from the host interface to the device.
gem5::Pl011::UART_IFLS
static const int UART_IFLS
Definition: pl011.hh:133
gem5::Uart
Definition: uart.hh:49
gem5::Pl011::interrupt
ArmInterruptPin *const interrupt
Definition: pl011.hh:180
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Pl011::UART_RIS
static const int UART_RIS
Definition: pl011.hh:135
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
gem5::Pl011::fbrd
uint16_t fbrd
fractional baud rate divisor.
Definition: pl011.hh:156
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::Pl011::UART_DR
static const int UART_DR
Definition: pl011.hh:120
gem5::Pl011::UART_ICR
static const int UART_ICR
Definition: pl011.hh:137
gem5::Uart::device
SerialDevice * device
Definition: uart.hh:54
gem5::Pl011::control
uint16_t control
Definition: pl011.hh:152
gem5::Pl011::UART_TXINTR
static const uint16_t UART_TXINTR
Definition: pl011.hh:145
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
pl011.hh
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::Pl011::UART_IMSC
static const int UART_IMSC
Definition: pl011.hh:134
packet_access.hh
gem5::Pl011::UART_FR_RXFE
static const int UART_FR_RXFE
Definition: pl011.hh:125
gem5::Pl011::ifls
uint16_t ifls
interrupt fifo level register.
Definition: pl011.hh:168
gem5::Pl011::UART_DMACR
static const int UART_DMACR
Definition: pl011.hh:138
gem5::Pl011::UART_RTINTR
static const uint16_t UART_RTINTR
Definition: pl011.hh:146
gem5::Pl011::generateInterrupt
void generateInterrupt()
Function to generate interrupt.
Definition: pl011.cc:243
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
gem5::Pl011::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pl011.cc:273
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::Pl011::setInterrupts
void setInterrupts(uint16_t ints, uint16_t mask)
Assign new interrupt values and update interrupt signals.
Definition: pl011.cc:255
gem5::Pl011::intEvent
EventFunctionWrapper intEvent
Wrapper to create an event out of the thing.
Definition: pl011.hh:116
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Pl011::UART_FR
static const int UART_FR
Definition: pl011.hh:123
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
gem5::Pl011::UART_FR_CTS
static const int UART_FR_CTS
Definition: pl011.hh:124
gem5::AmbaDevice::readId
bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
Definition: amba_device.cc:75
trace.hh
gem5::Pl011::maskInt
uint16_t maskInt() const
Masked interrupt status register.
Definition: pl011.hh:113
gem5::Pl011::rawInt
uint16_t rawInt
raw interrupt status register
Definition: pl011.hh:174
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::Pl011::raiseInterrupts
void raiseInterrupts(uint16_t ints)
Convenience function to raise a new interrupt.
Definition: pl011.hh:103
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Pl011::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: pl011.cc:67
gem5::Packet::setUintX
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition: packet.cc:351
gem5::SerialDevice::readData
virtual uint8_t readData()=0
Read a character from the device.
gem5::Pl011::endOnEOT
const bool endOnEOT
Should the simulation end on an EOT.
Definition: pl011.hh:178
gem5::Pl011::UART_RXINTR
static const uint16_t UART_RXINTR
Definition: pl011.hh:144
gem5::Pl011::intDelay
const Tick intDelay
Delay before interrupting.
Definition: pl011.hh:183
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::Pl011::UART_FR_RXFF
static const int UART_FR_RXFF
Definition: pl011.hh:127
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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