gem5  v21.2.1.1
isa.cc
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1 /*
2  * Copyright (c) 2016 RISC-V Foundation
3  * Copyright (c) 2016 The University of Virginia
4  * Copyright (c) 2020 Barkhausen Institut
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30 
31 #include "arch/riscv/isa.hh"
32 
33 #include <ctime>
34 #include <set>
35 #include <sstream>
36 
37 #include "arch/riscv/interrupts.hh"
38 #include "arch/riscv/mmu.hh"
39 #include "arch/riscv/pagetable.hh"
40 #include "arch/riscv/pmp.hh"
41 #include "arch/riscv/regs/float.hh"
42 #include "arch/riscv/regs/int.hh"
43 #include "arch/riscv/regs/misc.hh"
44 #include "base/bitfield.hh"
45 #include "base/compiler.hh"
46 #include "base/logging.hh"
47 #include "base/trace.hh"
48 #include "cpu/base.hh"
49 #include "debug/Checkpoint.hh"
50 #include "debug/LLSC.hh"
51 #include "debug/RiscvMisc.hh"
52 #include "mem/packet.hh"
53 #include "mem/request.hh"
54 #include "params/RiscvISA.hh"
55 #include "sim/pseudo_inst.hh"
56 
57 namespace gem5
58 {
59 
60 namespace RiscvISA
61 {
62 
63 [[maybe_unused]] const std::array<const char *, NUM_MISCREGS> MiscRegNames = {{
64  [MISCREG_PRV] = "PRV",
65  [MISCREG_ISA] = "ISA",
66  [MISCREG_VENDORID] = "VENDORID",
67  [MISCREG_ARCHID] = "ARCHID",
68  [MISCREG_IMPID] = "IMPID",
69  [MISCREG_HARTID] = "HARTID",
70  [MISCREG_STATUS] = "STATUS",
71  [MISCREG_IP] = "IP",
72  [MISCREG_IE] = "IE",
73  [MISCREG_CYCLE] = "CYCLE",
74  [MISCREG_TIME] = "TIME",
75  [MISCREG_INSTRET] = "INSTRET",
76  [MISCREG_HPMCOUNTER03] = "HPMCOUNTER03",
77  [MISCREG_HPMCOUNTER04] = "HPMCOUNTER04",
78  [MISCREG_HPMCOUNTER05] = "HPMCOUNTER05",
79  [MISCREG_HPMCOUNTER06] = "HPMCOUNTER06",
80  [MISCREG_HPMCOUNTER07] = "HPMCOUNTER07",
81  [MISCREG_HPMCOUNTER08] = "HPMCOUNTER08",
82  [MISCREG_HPMCOUNTER09] = "HPMCOUNTER09",
83  [MISCREG_HPMCOUNTER10] = "HPMCOUNTER10",
84  [MISCREG_HPMCOUNTER11] = "HPMCOUNTER11",
85  [MISCREG_HPMCOUNTER12] = "HPMCOUNTER12",
86  [MISCREG_HPMCOUNTER13] = "HPMCOUNTER13",
87  [MISCREG_HPMCOUNTER14] = "HPMCOUNTER14",
88  [MISCREG_HPMCOUNTER15] = "HPMCOUNTER15",
89  [MISCREG_HPMCOUNTER16] = "HPMCOUNTER16",
90  [MISCREG_HPMCOUNTER17] = "HPMCOUNTER17",
91  [MISCREG_HPMCOUNTER18] = "HPMCOUNTER18",
92  [MISCREG_HPMCOUNTER19] = "HPMCOUNTER19",
93  [MISCREG_HPMCOUNTER20] = "HPMCOUNTER20",
94  [MISCREG_HPMCOUNTER21] = "HPMCOUNTER21",
95  [MISCREG_HPMCOUNTER22] = "HPMCOUNTER22",
96  [MISCREG_HPMCOUNTER23] = "HPMCOUNTER23",
97  [MISCREG_HPMCOUNTER24] = "HPMCOUNTER24",
98  [MISCREG_HPMCOUNTER25] = "HPMCOUNTER25",
99  [MISCREG_HPMCOUNTER26] = "HPMCOUNTER26",
100  [MISCREG_HPMCOUNTER27] = "HPMCOUNTER27",
101  [MISCREG_HPMCOUNTER28] = "HPMCOUNTER28",
102  [MISCREG_HPMCOUNTER29] = "HPMCOUNTER29",
103  [MISCREG_HPMCOUNTER30] = "HPMCOUNTER30",
104  [MISCREG_HPMCOUNTER31] = "HPMCOUNTER31",
105  [MISCREG_HPMEVENT03] = "HPMEVENT03",
106  [MISCREG_HPMEVENT04] = "HPMEVENT04",
107  [MISCREG_HPMEVENT05] = "HPMEVENT05",
108  [MISCREG_HPMEVENT06] = "HPMEVENT06",
109  [MISCREG_HPMEVENT07] = "HPMEVENT07",
110  [MISCREG_HPMEVENT08] = "HPMEVENT08",
111  [MISCREG_HPMEVENT09] = "HPMEVENT09",
112  [MISCREG_HPMEVENT10] = "HPMEVENT10",
113  [MISCREG_HPMEVENT11] = "HPMEVENT11",
114  [MISCREG_HPMEVENT12] = "HPMEVENT12",
115  [MISCREG_HPMEVENT13] = "HPMEVENT13",
116  [MISCREG_HPMEVENT14] = "HPMEVENT14",
117  [MISCREG_HPMEVENT15] = "HPMEVENT15",
118  [MISCREG_HPMEVENT16] = "HPMEVENT16",
119  [MISCREG_HPMEVENT17] = "HPMEVENT17",
120  [MISCREG_HPMEVENT18] = "HPMEVENT18",
121  [MISCREG_HPMEVENT19] = "HPMEVENT19",
122  [MISCREG_HPMEVENT20] = "HPMEVENT20",
123  [MISCREG_HPMEVENT21] = "HPMEVENT21",
124  [MISCREG_HPMEVENT22] = "HPMEVENT22",
125  [MISCREG_HPMEVENT23] = "HPMEVENT23",
126  [MISCREG_HPMEVENT24] = "HPMEVENT24",
127  [MISCREG_HPMEVENT25] = "HPMEVENT25",
128  [MISCREG_HPMEVENT26] = "HPMEVENT26",
129  [MISCREG_HPMEVENT27] = "HPMEVENT27",
130  [MISCREG_HPMEVENT28] = "HPMEVENT28",
131  [MISCREG_HPMEVENT29] = "HPMEVENT29",
132  [MISCREG_HPMEVENT30] = "HPMEVENT30",
133  [MISCREG_HPMEVENT31] = "HPMEVENT31",
134  [MISCREG_TSELECT] = "TSELECT",
135  [MISCREG_TDATA1] = "TDATA1",
136  [MISCREG_TDATA2] = "TDATA2",
137  [MISCREG_TDATA3] = "TDATA3",
138  [MISCREG_DCSR] = "DCSR",
139  [MISCREG_DPC] = "DPC",
140  [MISCREG_DSCRATCH] = "DSCRATCH",
141 
142  [MISCREG_MEDELEG] = "MEDELEG",
143  [MISCREG_MIDELEG] = "MIDELEG",
144  [MISCREG_MTVEC] = "MTVEC",
145  [MISCREG_MCOUNTEREN] = "MCOUNTEREN",
146  [MISCREG_MSCRATCH] = "MSCRATCH",
147  [MISCREG_MEPC] = "MEPC",
148  [MISCREG_MCAUSE] = "MCAUSE",
149  [MISCREG_MTVAL] = "MTVAL",
150  [MISCREG_PMPCFG0] = "PMPCFG0",
151  // pmpcfg1 rv32 only
152  [MISCREG_PMPCFG2] = "PMPCFG2",
153  // pmpcfg3 rv32 only
154  [MISCREG_PMPADDR00] = "PMPADDR00",
155  [MISCREG_PMPADDR01] = "PMPADDR01",
156  [MISCREG_PMPADDR02] = "PMPADDR02",
157  [MISCREG_PMPADDR03] = "PMPADDR03",
158  [MISCREG_PMPADDR04] = "PMPADDR04",
159  [MISCREG_PMPADDR05] = "PMPADDR05",
160  [MISCREG_PMPADDR06] = "PMPADDR06",
161  [MISCREG_PMPADDR07] = "PMPADDR07",
162  [MISCREG_PMPADDR08] = "PMPADDR08",
163  [MISCREG_PMPADDR09] = "PMPADDR09",
164  [MISCREG_PMPADDR10] = "PMPADDR10",
165  [MISCREG_PMPADDR11] = "PMPADDR11",
166  [MISCREG_PMPADDR12] = "PMPADDR12",
167  [MISCREG_PMPADDR13] = "PMPADDR13",
168  [MISCREG_PMPADDR14] = "PMPADDR14",
169  [MISCREG_PMPADDR15] = "PMPADDR15",
170 
171  [MISCREG_SEDELEG] = "SEDELEG",
172  [MISCREG_SIDELEG] = "SIDELEG",
173  [MISCREG_STVEC] = "STVEC",
174  [MISCREG_SCOUNTEREN] = "SCOUNTEREN",
175  [MISCREG_SSCRATCH] = "SSCRATCH",
176  [MISCREG_SEPC] = "SEPC",
177  [MISCREG_SCAUSE] = "SCAUSE",
178  [MISCREG_STVAL] = "STVAL",
179  [MISCREG_SATP] = "SATP",
180 
181  [MISCREG_UTVEC] = "UTVEC",
182  [MISCREG_USCRATCH] = "USCRATCH",
183  [MISCREG_UEPC] = "UEPC",
184  [MISCREG_UCAUSE] = "UCAUSE",
185  [MISCREG_UTVAL] = "UTVAL",
186  [MISCREG_FFLAGS] = "FFLAGS",
187  [MISCREG_FRM] = "FRM",
188 
189  [MISCREG_NMIVEC] = "NMIVEC",
190  [MISCREG_NMIE] = "NMIE",
191  [MISCREG_NMIP] = "NMIP",
192 }};
193 
195 {
196  _regClasses.emplace_back(NumIntRegs, 0);
197  _regClasses.emplace_back(NumFloatRegs);
198  _regClasses.emplace_back(1); // Not applicable to RISCV
199  _regClasses.emplace_back(2); // Not applicable to RISCV
200  _regClasses.emplace_back(1); // Not applicable to RISCV
201  _regClasses.emplace_back(0); // Not applicable to RISCV
202  _regClasses.emplace_back(NUM_MISCREGS);
203 
204  miscRegFile.resize(NUM_MISCREGS);
205  clear();
206 }
207 
208 bool ISA::inUserMode() const
209 {
210  return miscRegFile[MISCREG_PRV] == PRV_U;
211 }
212 
213 void
215 {
216  // First loop through the integer registers.
217  for (int i = 0; i < NumIntRegs; ++i)
218  tc->setIntReg(i, src->readIntReg(i));
219 
220  // Second loop through the float registers.
221  for (int i = 0; i < NumFloatRegs; ++i)
222  tc->setFloatReg(i, src->readFloatReg(i));
223 
224  // Lastly copy PC/NPC
225  tc->pcState(src->pcState());
226 }
227 
229 {
230  std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
231 
233  miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x14112D;
237  miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
238  (1ULL << FS_OFFSET);
241  // don't set it to zero; software may try to determine the supported
242  // triggers, starting at zero. simply set a different value here.
244  // NMI is always enabled.
246 }
247 
248 bool
249 ISA::hpmCounterEnabled(int misc_reg) const
250 {
251  int hpmcounter = misc_reg - MISCREG_CYCLE;
252  if (hpmcounter < 0 || hpmcounter > 31)
253  panic("Illegal HPM counter %d\n", hpmcounter);
254  int counteren;
255  switch (readMiscRegNoEffect(MISCREG_PRV)) {
256  case PRV_M:
257  return true;
258  case PRV_S:
259  counteren = MISCREG_MCOUNTEREN;
260  break;
261  case PRV_U:
262  counteren = MISCREG_SCOUNTEREN;
263  break;
264  default:
265  panic("Unknown privilege level %d\n", miscRegFile[MISCREG_PRV]);
266  return false;
267  }
268  return (miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
269 }
270 
271 RegVal
272 ISA::readMiscRegNoEffect(int misc_reg) const
273 {
274  if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
275  // Illegal CSR
276  panic("Illegal CSR index %#x\n", misc_reg);
277  return -1;
278  }
279  DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#x.\n",
280  MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]);
281  return miscRegFile[misc_reg];
282 }
283 
284 RegVal
285 ISA::readMiscReg(int misc_reg)
286 {
287  switch (misc_reg) {
288  case MISCREG_HARTID:
289  return tc->contextId();
290  case MISCREG_CYCLE:
292  DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
293  tc->getCpuPtr()->curCycle());
294  return tc->getCpuPtr()->curCycle();
295  } else {
296  warn("Cycle counter disabled.\n");
297  return 0;
298  }
299  case MISCREG_TIME:
301  DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
302  std::time(nullptr));
304  } else {
305  warn("Wall clock disabled.\n");
306  return 0;
307  }
308  case MISCREG_INSTRET:
310  DPRINTF(RiscvMisc, "Instruction counter at: %llu.\n",
311  tc->getCpuPtr()->totalInsts());
312  return tc->getCpuPtr()->totalInsts();
313  } else {
314  warn("Instruction counter disabled.\n");
315  return 0;
316  }
317  case MISCREG_IP:
318  {
319  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
320  tc->getCpuPtr()->getInterruptController(tc->threadId()));
321  return ic->readIP();
322  }
323  case MISCREG_IE:
324  {
325  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
326  tc->getCpuPtr()->getInterruptController(tc->threadId()));
327  return ic->readIE();
328  }
329  case MISCREG_SEPC:
330  case MISCREG_MEPC:
331  {
332  auto misa = readMiscRegNoEffect(MISCREG_ISA);
333  auto val = readMiscRegNoEffect(misc_reg);
334  // if compressed instructions are disabled, epc[1] is set to 0
335  if ((misa & ISA_EXT_C_MASK) == 0)
336  return mbits(val, 63, 2);
337  // epc[0] is always 0
338  else
339  return mbits(val, 63, 1);
340  }
341  default:
342  // Try reading HPM counters
343  // As a placeholder, all HPM counters are just cycle counters
344  if (misc_reg >= MISCREG_HPMCOUNTER03 &&
345  misc_reg <= MISCREG_HPMCOUNTER31) {
346  if (hpmCounterEnabled(misc_reg)) {
347  DPRINTF(RiscvMisc, "HPM counter %d: %llu.\n",
348  misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle());
349  return tc->getCpuPtr()->curCycle();
350  } else {
351  warn("HPM counter %d disabled.\n", misc_reg - MISCREG_CYCLE);
352  return 0;
353  }
354  }
355  return readMiscRegNoEffect(misc_reg);
356  }
357 }
358 
359 void
361 {
362  if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
363  // Illegal CSR
364  panic("Illegal CSR index %#x\n", misc_reg);
365  }
366  DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n",
367  MiscRegNames[misc_reg], misc_reg, val);
368  miscRegFile[misc_reg] = val;
369 }
370 
371 void
372 ISA::setMiscReg(int misc_reg, RegVal val)
373 {
374  if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
375  // Ignore writes to HPM counters for now
376  warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
377  } else {
378  switch (misc_reg) {
379 
380  // From section 3.7.1 of RISCV priv. specs
381  // V1.12, the odd-numbered configuration
382  // registers are illegal for RV64 and
383  // each 64 bit CFG register hold configurations
384  // for 8 PMP entries.
385 
386  case MISCREG_PMPCFG0:
387  case MISCREG_PMPCFG2:
388  {
389  // PMP registers should only be modified in M mode
391 
392  // Specs do not seem to mention what should be
393  // configured first, cfg or address regs!
394  // qemu seems to update the tables when
395  // pmp addr regs are written (with the assumption
396  // that cfg regs are already written)
397 
398  for (int i=0; i < sizeof(val); i++) {
399 
400  uint8_t cfg_val = (val >> (8*i)) & 0xff;
401  auto mmu = dynamic_cast<RiscvISA::MMU *>
402  (tc->getMMUPtr());
403 
404  // Form pmp_index using the index i and
405  // PMPCFG register number
406  // Note: MISCREG_PMPCFG2 - MISCREG_PMPCFG0 = 1
407  // 8*(misc_reg-MISCREG_PMPCFG0) will be useful
408  // if a system contains more than 16 PMP entries
409  uint32_t pmp_index = i+(8*(misc_reg-MISCREG_PMPCFG0));
410  mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
411  }
412 
413  setMiscRegNoEffect(misc_reg, val);
414  }
415  break;
417  {
418  // PMP registers should only be modified in M mode
420 
421  auto mmu = dynamic_cast<RiscvISA::MMU *>
422  (tc->getMMUPtr());
423  uint32_t pmp_index = misc_reg-MISCREG_PMPADDR00;
424  mmu->getPMP()->pmpUpdateAddr(pmp_index, val);
425 
426  setMiscRegNoEffect(misc_reg, val);
427  }
428  break;
429 
430  case MISCREG_IP:
431  {
432  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
433  tc->getCpuPtr()->getInterruptController(tc->threadId()));
434  ic->setIP(val);
435  }
436  break;
437  case MISCREG_IE:
438  {
439  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
440  tc->getCpuPtr()->getInterruptController(tc->threadId()));
441  ic->setIE(val);
442  }
443  break;
444  case MISCREG_SATP:
445  {
446  // we only support bare and Sv39 mode; setting a different mode
447  // shall have no effect (see 4.1.12 in priv ISA manual)
448  SATP cur_val = readMiscRegNoEffect(misc_reg);
449  SATP new_val = val;
450  if (new_val.mode != AddrXlateMode::BARE &&
451  new_val.mode != AddrXlateMode::SV39)
452  new_val.mode = cur_val.mode;
453  setMiscRegNoEffect(misc_reg, new_val);
454  }
455  break;
456  case MISCREG_TSELECT:
457  {
458  // we don't support debugging, so always set a different value
459  // than written
460  setMiscRegNoEffect(misc_reg, val + 1);
461  }
462  break;
463  case MISCREG_ISA:
464  {
465  auto cur_val = readMiscRegNoEffect(misc_reg);
466  // only allow to disable compressed instructions
467  // if the following instruction is 4-byte aligned
468  if ((val & ISA_EXT_C_MASK) == 0 &&
470  2, 0) != 0) {
471  val |= cur_val & ISA_EXT_C_MASK;
472  }
473  setMiscRegNoEffect(misc_reg, val);
474  }
475  break;
476  case MISCREG_STATUS:
477  {
478  // SXL and UXL are hard-wired to 64 bit
479  auto cur = readMiscRegNoEffect(misc_reg);
481  val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
482  setMiscRegNoEffect(misc_reg, val);
483  }
484  break;
485  default:
486  setMiscRegNoEffect(misc_reg, val);
487  }
488  }
489 }
490 
491 void
493 {
494  DPRINTF(Checkpoint, "Serializing Riscv Misc Registers\n");
496 }
497 
498 void
500 {
501  DPRINTF(Checkpoint, "Unserializing Riscv Misc Registers\n");
503 }
504 
505 const int WARN_FAILURE = 10000;
506 
507 // RISC-V allows multiple locks per hart, but each SC has to unlock the most
508 // recent one, so we use a stack here.
509 std::unordered_map<int, std::stack<Addr>> locked_addrs;
510 
511 void
513 {
514  std::stack<Addr>& locked_addr_stack = locked_addrs[tc->contextId()];
515 
516  if (locked_addr_stack.empty())
517  return;
518  Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
519  DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
520  if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
521  locked_addr_stack.pop();
522 }
523 
524 
525 void
527 {
528  std::stack<Addr>& locked_addr_stack = locked_addrs[tc->contextId()];
529 
530  locked_addr_stack.push(req->getPaddr() & ~0xF);
531  DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
532  req->contextId(), req->getPaddr() & ~0xF);
533 }
534 
535 bool
536 ISA::handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
537 {
538  std::stack<Addr>& locked_addr_stack = locked_addrs[tc->contextId()];
539 
540  // Normally RISC-V uses zero to indicate success and nonzero to indicate
541  // failure (right now only 1 is reserved), but in gem5 zero indicates
542  // failure and one indicates success, so here we conform to that (it should
543  // be switched in the instruction's implementation)
544 
545  DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
546  locked_addr_stack.empty() ? "yes" : "no");
547  if (!locked_addr_stack.empty()) {
548  DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
549  req->getPaddr() & ~0xF);
550  DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
551  locked_addr_stack.top());
552  }
553  if (locked_addr_stack.empty()
554  || locked_addr_stack.top() != ((req->getPaddr() & ~0xF))) {
555  req->setExtraData(0);
556  int stCondFailures = tc->readStCondFailures();
557  tc->setStCondFailures(++stCondFailures);
558  if (stCondFailures % WARN_FAILURE == 0) {
559  warn("%i: context %d: %d consecutive SC failures.\n",
560  curTick(), tc->contextId(), stCondFailures);
561  }
562  return false;
563  }
564  if (req->isUncacheable()) {
565  req->setExtraData(2);
566  }
567  return true;
568 }
569 
570 void
572 {
573  tc->getCpuPtr()->wakeup(tc->threadId());
574 }
575 
576 } // namespace RiscvISA
577 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::RiscvISA::MISCREG_HPMCOUNTER31
@ MISCREG_HPMCOUNTER31
Definition: misc.hh:105
gem5::RiscvISA::MISCREG_HPMEVENT11
@ MISCREG_HPMEVENT11
Definition: misc.hh:114
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:56
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:71
gem5::RiscvISA::MISCREG_HPMCOUNTER09
@ MISCREG_HPMCOUNTER09
Definition: misc.hh:83
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:57
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
warn
#define warn(...)
Definition: logging.hh:246
gem5::RiscvISA::MISCREG_PMPADDR11
@ MISCREG_PMPADDR11
Definition: misc.hh:166
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::MISCREG_HPMEVENT16
@ MISCREG_HPMEVENT16
Definition: misc.hh:119
gem5::RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: misc.hh:376
gem5::RiscvISA::MISCREG_HPMCOUNTER27
@ MISCREG_HPMCOUNTER27
Definition: misc.hh:101
gem5::RiscvISA::MISCREG_HPMCOUNTER08
@ MISCREG_HPMCOUNTER08
Definition: misc.hh:82
gem5::RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:93
gem5::RiscvISA::MISCREG_HPMCOUNTER12
@ MISCREG_HPMCOUNTER12
Definition: misc.hh:86
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:304
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::RiscvISA::MISCREG_SIDELEG
@ MISCREG_SIDELEG
Definition: misc.hh:173
gem5::RiscvISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.cc:208
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
pseudo_inst.hh
gem5::RiscvISA::MISCREG_SSCRATCH
@ MISCREG_SSCRATCH
Definition: misc.hh:176
gem5::RiscvISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:214
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RiscvISA::MISCREG_HPMEVENT19
@ MISCREG_HPMEVENT19
Definition: misc.hh:122
gem5::RiscvISA::MMU
Definition: mmu.hh:54
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::RiscvISA::MISCREG_PMPADDR09
@ MISCREG_PMPADDR09
Definition: misc.hh:164
gem5::RiscvISA::MISCREG_HPMCOUNTER26
@ MISCREG_HPMCOUNTER26
Definition: misc.hh:100
gem5::RiscvISA::MISCREG_MTVAL
@ MISCREG_MTVAL
Definition: misc.hh:150
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::RiscvISA::MISCREG_HPMEVENT15
@ MISCREG_HPMEVENT15
Definition: misc.hh:118
gem5::RiscvISA::MISCREG_HPMEVENT05
@ MISCREG_HPMEVENT05
Definition: misc.hh:108
gem5::RiscvISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:60
interrupts.hh
gem5::RiscvISA::MISCREG_SEDELEG
@ MISCREG_SEDELEG
Definition: misc.hh:172
gem5::RiscvISA::MISCREG_HPMCOUNTER07
@ MISCREG_HPMCOUNTER07
Definition: misc.hh:81
gem5::RiscvISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:200
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::RiscvISA::MISCREG_DPC
@ MISCREG_DPC
Definition: misc.hh:140
gem5::RiscvISA::MISCREG_ISA
@ MISCREG_ISA
Definition: misc.hh:66
gem5::RiscvISA::MISCREG_IE
@ MISCREG_IE
Definition: misc.hh:73
gem5::RiscvISA::MISCREG_HPMEVENT14
@ MISCREG_HPMEVENT14
Definition: misc.hh:117
float.hh
gem5::RiscvISA::MISCREG_CYCLE
@ MISCREG_CYCLE
Definition: misc.hh:74
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::RiscvISA::MISCREG_HPMCOUNTER14
@ MISCREG_HPMCOUNTER14
Definition: misc.hh:88
gem5::RiscvISA::ISA::Params
RiscvISAParams Params
Definition: isa.hh:76
gem5::RiscvISA::locked_addrs
std::unordered_map< int, std::stack< Addr > > locked_addrs
Definition: isa.cc:509
isa.hh
request.hh
gem5::RiscvISA::MISCREG_HPMEVENT22
@ MISCREG_HPMEVENT22
Definition: misc.hh:125
gem5::RiscvISA::MISCREG_HPMCOUNTER13
@ MISCREG_HPMCOUNTER13
Definition: misc.hh:87
gem5::RiscvISA::MISCREG_HPMEVENT09
@ MISCREG_HPMEVENT09
Definition: misc.hh:112
misc.hh
gem5::RiscvISA::STATUS_UXL_MASK
const RegVal STATUS_UXL_MASK
Definition: misc.hh:600
gem5::RiscvISA::MISCREG_PMPADDR12
@ MISCREG_PMPADDR12
Definition: misc.hh:167
packet.hh
gem5::RiscvISA::MISCREG_SCAUSE
@ MISCREG_SCAUSE
Definition: misc.hh:178
gem5::RiscvISA::MISCREG_NMIE
@ MISCREG_NMIE
Definition: misc.hh:196
gem5::RiscvISA::MISCREG_HPMCOUNTER06
@ MISCREG_HPMCOUNTER06
Definition: misc.hh:80
gem5::RiscvISA::MISCREG_MEDELEG
@ MISCREG_MEDELEG
Definition: misc.hh:143
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
gem5::RiscvISA::MISCREG_DSCRATCH
@ MISCREG_DSCRATCH
Definition: misc.hh:141
gem5::RiscvISA::MISCREG_HPMEVENT29
@ MISCREG_HPMEVENT29
Definition: misc.hh:132
gem5::RiscvISA::FS_OFFSET
const off_t FS_OFFSET
Definition: misc.hh:590
gem5::RiscvISA::MISCREG_PMPADDR01
@ MISCREG_PMPADDR01
Definition: misc.hh:156
gem5::RiscvISA::MISCREG_INSTRET
@ MISCREG_INSTRET
Definition: misc.hh:76
pmp.hh
gem5::RiscvISA::MISCREG_HPMCOUNTER29
@ MISCREG_HPMCOUNTER29
Definition: misc.hh:103
gem5::RiscvISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:285
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
bitfield.hh
gem5::RiscvISA::MISCREG_PMPADDR05
@ MISCREG_PMPADDR05
Definition: misc.hh:160
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::RiscvISA::MISCREG_HPMEVENT24
@ MISCREG_HPMEVENT24
Definition: misc.hh:127
gem5::GenericISA::PCStateWithNext::npc
Addr npc() const
Definition: pcstate.hh:266
gem5::RiscvISA::MISCREG_HPMCOUNTER25
@ MISCREG_HPMCOUNTER25
Definition: misc.hh:99
gem5::RiscvISA::SXL_OFFSET
const off_t SXL_OFFSET
Definition: misc.hh:588
gem5::RiscvISA::MISCREG_HPMEVENT31
@ MISCREG_HPMEVENT31
Definition: misc.hh:134
gem5::RiscvISA::MISCREG_FRM
@ MISCREG_FRM
Definition: misc.hh:188
gem5::RiscvISA::MISCREG_SEPC
@ MISCREG_SEPC
Definition: misc.hh:177
gem5::RiscvISA::MISCREG_MSCRATCH
@ MISCREG_MSCRATCH
Definition: misc.hh:147
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RiscvISA::MISCREG_HPMCOUNTER18
@ MISCREG_HPMCOUNTER18
Definition: misc.hh:92
gem5::RiscvISA::MISCREG_IMPID
@ MISCREG_IMPID
Definition: misc.hh:69
gem5::RiscvISA::MISCREG_HPMCOUNTER17
@ MISCREG_HPMCOUNTER17
Definition: misc.hh:91
gem5::RiscvISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:499
gem5::RiscvISA::MISCREG_PMPADDR00
@ MISCREG_PMPADDR00
Definition: misc.hh:155
gem5::RiscvISA::STATUS_SXL_MASK
const RegVal STATUS_SXL_MASK
Definition: misc.hh:599
gem5::RiscvISA::MISCREG_HPMCOUNTER23
@ MISCREG_HPMCOUNTER23
Definition: misc.hh:97
gem5::RiscvISA::MISCREG_VENDORID
@ MISCREG_VENDORID
Definition: misc.hh:67
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:180
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::RiscvISA::MISCREG_PMPADDR08
@ MISCREG_PMPADDR08
Definition: misc.hh:163
gem5::RiscvISA::MISCREG_HPMEVENT21
@ MISCREG_HPMEVENT21
Definition: misc.hh:124
gem5::RiscvISA::MISCREG_HPMEVENT08
@ MISCREG_HPMEVENT08
Definition: misc.hh:111
gem5::RiscvISA::ISA::clear
void clear()
Definition: isa.cc:228
gem5::RiscvISA::MISCREG_MCAUSE
@ MISCREG_MCAUSE
Definition: misc.hh:149
gem5::RiscvISA::MISCREG_HPMEVENT13
@ MISCREG_HPMEVENT13
Definition: misc.hh:116
gem5::RiscvISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:272
gem5::RiscvISA::MISCREG_HPMEVENT20
@ MISCREG_HPMEVENT20
Definition: misc.hh:123
gem5::RiscvISA::MISCREG_HPMEVENT07
@ MISCREG_HPMEVENT07
Definition: misc.hh:110
gem5::RiscvISA::MISCREG_TDATA1
@ MISCREG_TDATA1
Definition: misc.hh:136
gem5::RiscvISA::MISCREG_HPMEVENT30
@ MISCREG_HPMEVENT30
Definition: misc.hh:133
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
gem5::RiscvISA::ISA::miscRegFile
std::vector< RegVal > miscRegFile
Definition: isa.hh:71
gem5::RiscvISA::MISCREG_PMPCFG2
@ MISCREG_PMPCFG2
Definition: misc.hh:153
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::MISCREG_TDATA3
@ MISCREG_TDATA3
Definition: misc.hh:138
gem5::RiscvISA::MISCREG_TSELECT
@ MISCREG_TSELECT
Definition: misc.hh:135
gem5::RiscvISA::MISCREG_HPMEVENT17
@ MISCREG_HPMEVENT17
Definition: misc.hh:120
gem5::RiscvISA::MISCREG_USCRATCH
@ MISCREG_USCRATCH
Definition: misc.hh:183
gem5::ThreadContext::readStCondFailures
virtual unsigned readStCondFailures() const =0
gem5::RiscvISA::ISA::handleLockedRead
void handleLockedRead(const RequestPtr &req) override
Definition: isa.cc:526
gem5::RiscvISA::Interrupts
Definition: interrupts.hh:56
gem5::RiscvISA::MISCREG_NMIVEC
@ MISCREG_NMIVEC
Definition: misc.hh:194
gem5::RiscvISA::MISCREG_HPMCOUNTER04
@ MISCREG_HPMCOUNTER04
Definition: misc.hh:78
gem5::RiscvISA::MISCREG_PMPADDR15
@ MISCREG_PMPADDR15
Definition: misc.hh:170
gem5::RiscvISA::ISA::handleLockedSnoop
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
Definition: isa.cc:512
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::MISCREG_PMPADDR03
@ MISCREG_PMPADDR03
Definition: misc.hh:158
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::RiscvISA::MISCREG_PMPADDR10
@ MISCREG_PMPADDR10
Definition: misc.hh:165
gem5::RiscvISA::MISCREG_HPMEVENT27
@ MISCREG_HPMEVENT27
Definition: misc.hh:130
gem5::RiscvISA::MISCREG_HPMEVENT12
@ MISCREG_HPMEVENT12
Definition: misc.hh:115
gem5::RiscvISA::MISCREG_MEPC
@ MISCREG_MEPC
Definition: misc.hh:148
gem5::RiscvISA::MISCREG_HARTID
@ MISCREG_HARTID
Definition: misc.hh:70
gem5::RiscvISA::MISCREG_HPMCOUNTER22
@ MISCREG_HPMCOUNTER22
Definition: misc.hh:96
gem5::RiscvISA::MISCREG_HPMCOUNTER03
@ MISCREG_HPMCOUNTER03
Definition: misc.hh:77
gem5::RiscvISA::MISCREG_PMPADDR07
@ MISCREG_PMPADDR07
Definition: misc.hh:162
gem5::RiscvISA::MISCREG_HPMEVENT10
@ MISCREG_HPMEVENT10
Definition: misc.hh:113
gem5::RiscvISA::MISCREG_HPMEVENT26
@ MISCREG_HPMEVENT26
Definition: misc.hh:129
gem5::RiscvISA::MISCREG_ARCHID
@ MISCREG_ARCHID
Definition: misc.hh:68
mmu.hh
gem5::RiscvISA::MISCREG_UTVEC
@ MISCREG_UTVEC
Definition: misc.hh:182
base.hh
gem5::RiscvISA::MISCREG_HPMCOUNTER21
@ MISCREG_HPMCOUNTER21
Definition: misc.hh:95
gem5::RiscvISA::MISCREG_HPMEVENT23
@ MISCREG_HPMEVENT23
Definition: misc.hh:126
gem5::RiscvISA::MISCREG_PMPADDR06
@ MISCREG_PMPADDR06
Definition: misc.hh:161
gem5::RiscvISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:492
gem5::RiscvISA::MISCREG_PMPCFG0
@ MISCREG_PMPCFG0
Definition: misc.hh:151
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::RiscvISA::ISA::globalClearExclusive
void globalClearExclusive() override
Definition: isa.cc:571
gem5::RiscvISA::MISCREG_PMPADDR04
@ MISCREG_PMPADDR04
Definition: misc.hh:159
gem5::RiscvISA::MISCREG_PMPADDR14
@ MISCREG_PMPADDR14
Definition: misc.hh:169
logging.hh
gem5::RiscvISA::MISCREG_TIME
@ MISCREG_TIME
Definition: misc.hh:75
gem5::RiscvISA::MiscRegNames
const std::array< const char *, NUM_MISCREGS > MiscRegNames
Definition: isa.cc:63
gem5::RiscvISA::MISCREG_UEPC
@ MISCREG_UEPC
Definition: misc.hh:184
gem5::RiscvISA::UXL_OFFSET
const off_t UXL_OFFSET
Definition: misc.hh:589
gem5::RiscvISA::MISCREG_HPMEVENT25
@ MISCREG_HPMEVENT25
Definition: misc.hh:128
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RiscvISA::MISCREG_MIDELEG
@ MISCREG_MIDELEG
Definition: misc.hh:144
gem5::RiscvISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:372
gem5::RiscvISA::MISCREG_PMPADDR02
@ MISCREG_PMPADDR02
Definition: misc.hh:157
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:55
gem5::RiscvISA::MISCREG_STVAL
@ MISCREG_STVAL
Definition: misc.hh:179
gem5::RiscvISA::MISCREG_HPMCOUNTER10
@ MISCREG_HPMCOUNTER10
Definition: misc.hh:84
gem5::ThreadContext::threadId
virtual int threadId() const =0
trace.hh
gem5::RiscvISA::MISCREG_UCAUSE
@ MISCREG_UCAUSE
Definition: misc.hh:185
gem5::RiscvISA::MISCREG_HPMCOUNTER24
@ MISCREG_HPMCOUNTER24
Definition: misc.hh:98
gem5::RiscvISA::WARN_FAILURE
const int WARN_FAILURE
Definition: isa.cc:505
gem5::RiscvISA::ISA::handleLockedWrite
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
Definition: isa.cc:536
gem5::RiscvISA::MISCREG_HPMCOUNTER30
@ MISCREG_HPMCOUNTER30
Definition: misc.hh:104
gem5::BaseISA
Definition: isa.hh:57
gem5::RiscvISA::MISCREG_UTVAL
@ MISCREG_UTVAL
Definition: misc.hh:186
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::RiscvISA::MISCREG_HPMCOUNTER16
@ MISCREG_HPMCOUNTER16
Definition: misc.hh:90
gem5::ThreadContext::setStCondFailures
virtual void setStCondFailures(unsigned sc_failures)=0
gem5::RiscvISA::MISCREG_MCOUNTEREN
@ MISCREG_MCOUNTEREN
Definition: misc.hh:146
gem5::RiscvISA::MISCREG_HPMEVENT28
@ MISCREG_HPMEVENT28
Definition: misc.hh:131
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RiscvISA::MISCREG_PRV
@ MISCREG_PRV
Definition: misc.hh:65
gem5::RiscvISA::ISA_EXT_C_MASK
const RegVal ISA_EXT_C_MASK
Definition: misc.hh:595
int.hh
gem5::RiscvISA::MISCREG_HPMEVENT18
@ MISCREG_HPMEVENT18
Definition: misc.hh:121
gem5::RiscvISA::MISCREG_HPMCOUNTER19
@ MISCREG_HPMCOUNTER19
Definition: misc.hh:93
gem5::RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::RiscvISA::ISA::hpmCounterEnabled
bool hpmCounterEnabled(int counter) const
Definition: isa.cc:249
gem5::RiscvISA::MISCREG_PMPADDR13
@ MISCREG_PMPADDR13
Definition: misc.hh:168
gem5::RiscvISA::MISCREG_TDATA2
@ MISCREG_TDATA2
Definition: misc.hh:137
gem5::RiscvISA::MISCREG_HPMEVENT04
@ MISCREG_HPMEVENT04
Definition: misc.hh:107
gem5::RiscvISA::MISCREG_FFLAGS
@ MISCREG_FFLAGS
Definition: misc.hh:187
pagetable.hh
gem5::RiscvISA::MISCREG_DCSR
@ MISCREG_DCSR
Definition: misc.hh:139
gem5::RiscvISA::MISCREG_IP
@ MISCREG_IP
Definition: misc.hh:72
gem5::RiscvISA::MISCREG_STVEC
@ MISCREG_STVEC
Definition: misc.hh:174
gem5::RiscvISA::MISCREG_HPMEVENT06
@ MISCREG_HPMEVENT06
Definition: misc.hh:109
gem5::RiscvISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:194
gem5::RiscvISA::MISCREG_HPMCOUNTER15
@ MISCREG_HPMCOUNTER15
Definition: misc.hh:89
gem5::RiscvISA::MISCREG_NMIP
@ MISCREG_NMIP
Definition: misc.hh:198
gem5::RiscvISA::MISCREG_MTVEC
@ MISCREG_MTVEC
Definition: misc.hh:145
gem5::RiscvISA::MISCREG_SCOUNTEREN
@ MISCREG_SCOUNTEREN
Definition: misc.hh:175
gem5::RiscvISA::MISCREG_HPMCOUNTER11
@ MISCREG_HPMCOUNTER11
Definition: misc.hh:85
gem5::RiscvISA::MISCREG_HPMCOUNTER05
@ MISCREG_HPMCOUNTER05
Definition: misc.hh:79
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::RiscvISA::MISCREG_HPMCOUNTER28
@ MISCREG_HPMCOUNTER28
Definition: misc.hh:102
gem5::RiscvISA::MISCREG_HPMCOUNTER20
@ MISCREG_HPMCOUNTER20
Definition: misc.hh:94
gem5::RiscvISA::MISCREG_HPMEVENT03
@ MISCREG_HPMEVENT03
Definition: misc.hh:106
gem5::RiscvISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:360

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