49 #include "debug/Checkpoint.hh"
50 #include "debug/LLSC.hh"
51 #include "debug/RiscvMisc.hh"
54 #include "params/RiscvISA.hh"
63 [[maybe_unused]]
const std::array<const char *, NUM_MISCREGS>
MiscRegNames = {{
207 BaseISA(
p), checkAlignment(
p.check_alignment)
265 if (hpmcounter < 0 || hpmcounter > 31)
266 panic(
"Illegal HPM counter %d\n", hpmcounter);
281 return (
miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
289 DPRINTF(RiscvMisc,
"Reading MiscReg %s (%d): %#x.\n",
302 DPRINTF(RiscvMisc,
"Cycle counter at: %llu.\n",
306 warn(
"Cycle counter disabled.\n");
311 DPRINTF(RiscvMisc,
"Wall-clock counter at: %llu.\n",
315 warn(
"Wall clock disabled.\n");
320 DPRINTF(RiscvMisc,
"Instruction counter at: %llu.\n",
324 warn(
"Instruction counter disabled.\n");
380 DPRINTF(RiscvMisc,
"HPM counter %d: %llu.\n",
397 DPRINTF(RiscvMisc,
"Setting MiscReg %s (%d) to %#x.\n",
407 warn(
"Ignoring write to %s.\n",
CSRData.at(idx).name);
429 for (
int i=0;
i <
sizeof(
val);
i++) {
431 uint8_t cfg_val = (
val >> (8*
i)) & 0xff;
441 mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
455 mmu->getPMP()->pmpUpdateAddr(pmp_index,
val);
481 if (new_val.mode != AddrXlateMode::BARE &&
482 new_val.mode != AddrXlateMode::SV39)
483 new_val.mode = cur_val.mode;
525 DPRINTF(Checkpoint,
"Serializing Riscv Misc Registers\n");
532 DPRINTF(Checkpoint,
"Unserializing Riscv Misc Registers\n");
549 DPRINTF(LLSC,
"Locked snoop on address %x.\n", snoop_addr);
550 if ((load_reservation_addr & cacheBlockMask) == snoop_addr)
560 load_reservation_addr = req->getPaddr() & ~0xF;
561 DPRINTF(LLSC,
"[cid:%d]: Reserved address %x.\n",
562 req->contextId(), req->getPaddr() & ~0xF);
576 DPRINTF(LLSC,
"[cid:%d]: load_reservation_addrs empty? %s.\n",
578 lr_addr_empty ?
"yes" :
"no");
579 if (!lr_addr_empty) {
580 DPRINTF(LLSC,
"[cid:%d]: addr = %x.\n", req->contextId(),
581 req->getPaddr() & ~0xF);
582 DPRINTF(LLSC,
"[cid:%d]: last locked addr = %x.\n", req->contextId(),
583 load_reservation_addr);
586 || load_reservation_addr != ((req->getPaddr() & ~0xF))) {
587 req->setExtraData(0);
591 warn(
"%i: context %d: %d consecutive SC failures.\n",
596 if (req->isUncacheable()) {
597 req->setExtraData(2);
617 return os <<
"PRV_U";
619 return os <<
"PRV_S";
621 return os <<
"PRV_M";
623 return os <<
"PRV_<invalid>";
virtual Counter totalInsts() const =0
virtual void wakeup(ThreadID tid)=0
BaseInterrupts * getInterruptController(ThreadID tid)
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
void setMiscReg(RegIndex idx, RegVal val) override
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
RegVal readMiscReg(RegIndex idx) override
void globalClearExclusive() override
void serialize(CheckpointOut &cp) const override
Serialize an object.
void setMiscRegNoEffect(RegIndex idx, RegVal val) override
RegVal readMiscRegNoEffect(RegIndex idx) const override
bool hpmCounterEnabled(int counter) const
void copyRegsFrom(ThreadContext *src) override
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
std::vector< RegVal > miscRegFile
bool inUserMode() const override
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void handleLockedRead(const RequestPtr &req) override
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId ®) const
virtual const PCStateBase & pcState() const =0
virtual void setReg(const RegId ®, RegVal val)
virtual BaseCPU * getCpuPtr()=0
virtual void setStCondFailures(unsigned sc_failures)=0
virtual unsigned readStCondFailures() const =0
virtual int threadId() const =0
virtual ContextID contextId() const =0
virtual BaseMMU * getMMUPtr()=0
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
#define panic(...)
This implements a cprintf based panic() function.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
#define UNSERIALIZE_CONTAINER(member)
#define SERIALIZE_CONTAINER(member)
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
constexpr RegClass vecElemClass
constexpr RegClass vecPredRegClass
constexpr RegClass vecRegClass
constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs)
const RegVal STATUS_SXL_MASK
const RegVal STATUS_UXL_MASK
const std::unordered_map< int, CSRMetadata > CSRData
constexpr RegClass intRegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)
const std::array< const char *, NUM_MISCREGS > MiscRegNames
const RegVal ISA_EXT_C_MASK
const Addr INVALID_RESERVATION_ADDR
std::unordered_map< int, Addr > load_reservation_addrs
constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< Request > RequestPtr
constexpr char CCRegClassName[]
constexpr char VecPredRegClassName[]
Tick curTick()
The universal simulation clock.
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
constexpr char VecRegClassName[]
@ CCRegClass
Condition-code register.
@ VecRegClass
Vector Register.
@ VecElemClass
Vector Register Native Elem lane.
constexpr char VecElemClassName[]
Declaration of the Packet class.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
std::ostream & operator<<(std::ostream &os, gem5::RiscvISA::PrivilegeMode pm)