gem5  v21.1.0.2
isa.cc
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1 /*
2  * Copyright (c) 2016 RISC-V Foundation
3  * Copyright (c) 2016 The University of Virginia
4  * Copyright (c) 2020 Barkhausen Institut
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30 
31 #include "arch/riscv/isa.hh"
32 
33 #include <ctime>
34 #include <set>
35 #include <sstream>
36 
37 #include "arch/riscv/interrupts.hh"
38 #include "arch/riscv/mmu.hh"
39 #include "arch/riscv/pagetable.hh"
40 #include "arch/riscv/pmp.hh"
41 #include "arch/riscv/regs/float.hh"
42 #include "arch/riscv/regs/int.hh"
43 #include "arch/riscv/regs/misc.hh"
44 #include "base/bitfield.hh"
45 #include "base/compiler.hh"
46 #include "cpu/base.hh"
47 #include "debug/Checkpoint.hh"
48 #include "debug/RiscvMisc.hh"
49 #include "params/RiscvISA.hh"
50 #include "sim/pseudo_inst.hh"
51 
52 namespace gem5
53 {
54 
55 namespace RiscvISA
56 {
57 
58 GEM5_VAR_USED const std::array<const char *, NUM_MISCREGS> MiscRegNames = {{
59  [MISCREG_PRV] = "PRV",
60  [MISCREG_ISA] = "ISA",
61  [MISCREG_VENDORID] = "VENDORID",
62  [MISCREG_ARCHID] = "ARCHID",
63  [MISCREG_IMPID] = "IMPID",
64  [MISCREG_HARTID] = "HARTID",
65  [MISCREG_STATUS] = "STATUS",
66  [MISCREG_IP] = "IP",
67  [MISCREG_IE] = "IE",
68  [MISCREG_CYCLE] = "CYCLE",
69  [MISCREG_TIME] = "TIME",
70  [MISCREG_INSTRET] = "INSTRET",
71  [MISCREG_HPMCOUNTER03] = "HPMCOUNTER03",
72  [MISCREG_HPMCOUNTER04] = "HPMCOUNTER04",
73  [MISCREG_HPMCOUNTER05] = "HPMCOUNTER05",
74  [MISCREG_HPMCOUNTER06] = "HPMCOUNTER06",
75  [MISCREG_HPMCOUNTER07] = "HPMCOUNTER07",
76  [MISCREG_HPMCOUNTER08] = "HPMCOUNTER08",
77  [MISCREG_HPMCOUNTER09] = "HPMCOUNTER09",
78  [MISCREG_HPMCOUNTER10] = "HPMCOUNTER10",
79  [MISCREG_HPMCOUNTER11] = "HPMCOUNTER11",
80  [MISCREG_HPMCOUNTER12] = "HPMCOUNTER12",
81  [MISCREG_HPMCOUNTER13] = "HPMCOUNTER13",
82  [MISCREG_HPMCOUNTER14] = "HPMCOUNTER14",
83  [MISCREG_HPMCOUNTER15] = "HPMCOUNTER15",
84  [MISCREG_HPMCOUNTER16] = "HPMCOUNTER16",
85  [MISCREG_HPMCOUNTER17] = "HPMCOUNTER17",
86  [MISCREG_HPMCOUNTER18] = "HPMCOUNTER18",
87  [MISCREG_HPMCOUNTER19] = "HPMCOUNTER19",
88  [MISCREG_HPMCOUNTER20] = "HPMCOUNTER20",
89  [MISCREG_HPMCOUNTER21] = "HPMCOUNTER21",
90  [MISCREG_HPMCOUNTER22] = "HPMCOUNTER22",
91  [MISCREG_HPMCOUNTER23] = "HPMCOUNTER23",
92  [MISCREG_HPMCOUNTER24] = "HPMCOUNTER24",
93  [MISCREG_HPMCOUNTER25] = "HPMCOUNTER25",
94  [MISCREG_HPMCOUNTER26] = "HPMCOUNTER26",
95  [MISCREG_HPMCOUNTER27] = "HPMCOUNTER27",
96  [MISCREG_HPMCOUNTER28] = "HPMCOUNTER28",
97  [MISCREG_HPMCOUNTER29] = "HPMCOUNTER29",
98  [MISCREG_HPMCOUNTER30] = "HPMCOUNTER30",
99  [MISCREG_HPMCOUNTER31] = "HPMCOUNTER31",
100  [MISCREG_HPMEVENT03] = "HPMEVENT03",
101  [MISCREG_HPMEVENT04] = "HPMEVENT04",
102  [MISCREG_HPMEVENT05] = "HPMEVENT05",
103  [MISCREG_HPMEVENT06] = "HPMEVENT06",
104  [MISCREG_HPMEVENT07] = "HPMEVENT07",
105  [MISCREG_HPMEVENT08] = "HPMEVENT08",
106  [MISCREG_HPMEVENT09] = "HPMEVENT09",
107  [MISCREG_HPMEVENT10] = "HPMEVENT10",
108  [MISCREG_HPMEVENT11] = "HPMEVENT11",
109  [MISCREG_HPMEVENT12] = "HPMEVENT12",
110  [MISCREG_HPMEVENT13] = "HPMEVENT13",
111  [MISCREG_HPMEVENT14] = "HPMEVENT14",
112  [MISCREG_HPMEVENT15] = "HPMEVENT15",
113  [MISCREG_HPMEVENT16] = "HPMEVENT16",
114  [MISCREG_HPMEVENT17] = "HPMEVENT17",
115  [MISCREG_HPMEVENT18] = "HPMEVENT18",
116  [MISCREG_HPMEVENT19] = "HPMEVENT19",
117  [MISCREG_HPMEVENT20] = "HPMEVENT20",
118  [MISCREG_HPMEVENT21] = "HPMEVENT21",
119  [MISCREG_HPMEVENT22] = "HPMEVENT22",
120  [MISCREG_HPMEVENT23] = "HPMEVENT23",
121  [MISCREG_HPMEVENT24] = "HPMEVENT24",
122  [MISCREG_HPMEVENT25] = "HPMEVENT25",
123  [MISCREG_HPMEVENT26] = "HPMEVENT26",
124  [MISCREG_HPMEVENT27] = "HPMEVENT27",
125  [MISCREG_HPMEVENT28] = "HPMEVENT28",
126  [MISCREG_HPMEVENT29] = "HPMEVENT29",
127  [MISCREG_HPMEVENT30] = "HPMEVENT30",
128  [MISCREG_HPMEVENT31] = "HPMEVENT31",
129  [MISCREG_TSELECT] = "TSELECT",
130  [MISCREG_TDATA1] = "TDATA1",
131  [MISCREG_TDATA2] = "TDATA2",
132  [MISCREG_TDATA3] = "TDATA3",
133  [MISCREG_DCSR] = "DCSR",
134  [MISCREG_DPC] = "DPC",
135  [MISCREG_DSCRATCH] = "DSCRATCH",
136 
137  [MISCREG_MEDELEG] = "MEDELEG",
138  [MISCREG_MIDELEG] = "MIDELEG",
139  [MISCREG_MTVEC] = "MTVEC",
140  [MISCREG_MCOUNTEREN] = "MCOUNTEREN",
141  [MISCREG_MSCRATCH] = "MSCRATCH",
142  [MISCREG_MEPC] = "MEPC",
143  [MISCREG_MCAUSE] = "MCAUSE",
144  [MISCREG_MTVAL] = "MTVAL",
145  [MISCREG_PMPCFG0] = "PMPCFG0",
146  // pmpcfg1 rv32 only
147  [MISCREG_PMPCFG2] = "PMPCFG2",
148  // pmpcfg3 rv32 only
149  [MISCREG_PMPADDR00] = "PMPADDR00",
150  [MISCREG_PMPADDR01] = "PMPADDR01",
151  [MISCREG_PMPADDR02] = "PMPADDR02",
152  [MISCREG_PMPADDR03] = "PMPADDR03",
153  [MISCREG_PMPADDR04] = "PMPADDR04",
154  [MISCREG_PMPADDR05] = "PMPADDR05",
155  [MISCREG_PMPADDR06] = "PMPADDR06",
156  [MISCREG_PMPADDR07] = "PMPADDR07",
157  [MISCREG_PMPADDR08] = "PMPADDR08",
158  [MISCREG_PMPADDR09] = "PMPADDR09",
159  [MISCREG_PMPADDR10] = "PMPADDR10",
160  [MISCREG_PMPADDR11] = "PMPADDR11",
161  [MISCREG_PMPADDR12] = "PMPADDR12",
162  [MISCREG_PMPADDR13] = "PMPADDR13",
163  [MISCREG_PMPADDR14] = "PMPADDR14",
164  [MISCREG_PMPADDR15] = "PMPADDR15",
165 
166  [MISCREG_SEDELEG] = "SEDELEG",
167  [MISCREG_SIDELEG] = "SIDELEG",
168  [MISCREG_STVEC] = "STVEC",
169  [MISCREG_SCOUNTEREN] = "SCOUNTEREN",
170  [MISCREG_SSCRATCH] = "SSCRATCH",
171  [MISCREG_SEPC] = "SEPC",
172  [MISCREG_SCAUSE] = "SCAUSE",
173  [MISCREG_STVAL] = "STVAL",
174  [MISCREG_SATP] = "SATP",
175 
176  [MISCREG_UTVEC] = "UTVEC",
177  [MISCREG_USCRATCH] = "USCRATCH",
178  [MISCREG_UEPC] = "UEPC",
179  [MISCREG_UCAUSE] = "UCAUSE",
180  [MISCREG_UTVAL] = "UTVAL",
181  [MISCREG_FFLAGS] = "FFLAGS",
182  [MISCREG_FRM] = "FRM",
183 }};
184 
186 {
187  _regClasses.emplace_back(NumIntRegs, 0);
188  _regClasses.emplace_back(NumFloatRegs);
189  _regClasses.emplace_back(1); // Not applicable to RISCV
190  _regClasses.emplace_back(2); // Not applicable to RISCV
191  _regClasses.emplace_back(1); // Not applicable to RISCV
192  _regClasses.emplace_back(0); // Not applicable to RISCV
193  _regClasses.emplace_back(NUM_MISCREGS);
194 
195  miscRegFile.resize(NUM_MISCREGS);
196  clear();
197 }
198 
199 void
201 {
202  // First loop through the integer registers.
203  for (int i = 0; i < NumIntRegs; ++i)
204  tc->setIntReg(i, src->readIntReg(i));
205 
206  // Second loop through the float registers.
207  for (int i = 0; i < NumFloatRegs; ++i)
208  tc->setFloatReg(i, src->readFloatReg(i));
209 
210  // Lastly copy PC/NPC
211  tc->pcState(src->pcState());
212 }
213 
215 {
216  std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
217 
219  miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x14112D;
223  miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
224  (1ULL << FS_OFFSET);
227  // don't set it to zero; software may try to determine the supported
228  // triggers, starting at zero. simply set a different value here.
230 }
231 
232 bool
233 ISA::hpmCounterEnabled(int misc_reg) const
234 {
235  int hpmcounter = misc_reg - MISCREG_CYCLE;
236  if (hpmcounter < 0 || hpmcounter > 31)
237  panic("Illegal HPM counter %d\n", hpmcounter);
238  int counteren;
239  switch (readMiscRegNoEffect(MISCREG_PRV)) {
240  case PRV_M:
241  return true;
242  case PRV_S:
243  counteren = MISCREG_MCOUNTEREN;
244  break;
245  case PRV_U:
246  counteren = MISCREG_SCOUNTEREN;
247  break;
248  default:
249  panic("Unknown privilege level %d\n", miscRegFile[MISCREG_PRV]);
250  return false;
251  }
252  return (miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
253 }
254 
255 RegVal
256 ISA::readMiscRegNoEffect(int misc_reg) const
257 {
258  if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
259  // Illegal CSR
260  panic("Illegal CSR index %#x\n", misc_reg);
261  return -1;
262  }
263  DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#x.\n",
264  MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]);
265  return miscRegFile[misc_reg];
266 }
267 
268 RegVal
269 ISA::readMiscReg(int misc_reg)
270 {
271  switch (misc_reg) {
272  case MISCREG_HARTID:
273  return tc->contextId();
274  case MISCREG_CYCLE:
276  DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
277  tc->getCpuPtr()->curCycle());
278  return tc->getCpuPtr()->curCycle();
279  } else {
280  warn("Cycle counter disabled.\n");
281  return 0;
282  }
283  case MISCREG_TIME:
285  DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
286  std::time(nullptr));
288  } else {
289  warn("Wall clock disabled.\n");
290  return 0;
291  }
292  case MISCREG_INSTRET:
294  DPRINTF(RiscvMisc, "Instruction counter at: %llu.\n",
295  tc->getCpuPtr()->totalInsts());
296  return tc->getCpuPtr()->totalInsts();
297  } else {
298  warn("Instruction counter disabled.\n");
299  return 0;
300  }
301  case MISCREG_IP:
302  {
303  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
305  return ic->readIP();
306  }
307  case MISCREG_IE:
308  {
309  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
311  return ic->readIE();
312  }
313  case MISCREG_SEPC:
314  case MISCREG_MEPC:
315  {
316  auto misa = readMiscRegNoEffect(MISCREG_ISA);
317  auto val = readMiscRegNoEffect(misc_reg);
318  // if compressed instructions are disabled, epc[1] is set to 0
319  if ((misa & ISA_EXT_C_MASK) == 0)
320  return mbits(val, 63, 2);
321  // epc[0] is always 0
322  else
323  return mbits(val, 63, 1);
324  }
325  default:
326  // Try reading HPM counters
327  // As a placeholder, all HPM counters are just cycle counters
328  if (misc_reg >= MISCREG_HPMCOUNTER03 &&
329  misc_reg <= MISCREG_HPMCOUNTER31) {
330  if (hpmCounterEnabled(misc_reg)) {
331  DPRINTF(RiscvMisc, "HPM counter %d: %llu.\n",
332  misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle());
333  return tc->getCpuPtr()->curCycle();
334  } else {
335  warn("HPM counter %d disabled.\n", misc_reg - MISCREG_CYCLE);
336  return 0;
337  }
338  }
339  return readMiscRegNoEffect(misc_reg);
340  }
341 }
342 
343 void
345 {
346  if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
347  // Illegal CSR
348  panic("Illegal CSR index %#x\n", misc_reg);
349  }
350  DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n",
351  MiscRegNames[misc_reg], misc_reg, val);
352  miscRegFile[misc_reg] = val;
353 }
354 
355 void
356 ISA::setMiscReg(int misc_reg, RegVal val)
357 {
358  if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
359  // Ignore writes to HPM counters for now
360  warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
361  } else {
362  switch (misc_reg) {
363 
364  // From section 3.7.1 of RISCV priv. specs
365  // V1.12, the odd-numbered configuration
366  // registers are illegal for RV64 and
367  // each 64 bit CFG register hold configurations
368  // for 8 PMP entries.
369 
370  case MISCREG_PMPCFG0:
371  case MISCREG_PMPCFG2:
372  {
373  // PMP registers should only be modified in M mode
375 
376  // Specs do not seem to mention what should be
377  // configured first, cfg or address regs!
378  // qemu seems to update the tables when
379  // pmp addr regs are written (with the assumption
380  // that cfg regs are already written)
381 
382  for (int i=0; i < sizeof(val); i++) {
383 
384  uint8_t cfg_val = (val >> (8*i)) & 0xff;
385  auto mmu = dynamic_cast<RiscvISA::MMU *>
386  (tc->getMMUPtr());
387 
388  // Form pmp_index using the index i and
389  // PMPCFG register number
390  // Note: MISCREG_PMPCFG2 - MISCREG_PMPCFG0 = 1
391  // 8*(misc_reg-MISCREG_PMPCFG0) will be useful
392  // if a system contains more than 16 PMP entries
393  uint32_t pmp_index = i+(8*(misc_reg-MISCREG_PMPCFG0));
394  mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
395  }
396 
397  setMiscRegNoEffect(misc_reg, val);
398  }
399  break;
401  {
402  // PMP registers should only be modified in M mode
404 
405  auto mmu = dynamic_cast<RiscvISA::MMU *>
406  (tc->getMMUPtr());
407  uint32_t pmp_index = misc_reg-MISCREG_PMPADDR00;
408  mmu->getPMP()->pmpUpdateAddr(pmp_index, val);
409 
410  setMiscRegNoEffect(misc_reg, val);
411  }
412  break;
413 
414  case MISCREG_IP:
415  {
416  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
418  ic->setIP(val);
419  }
420  break;
421  case MISCREG_IE:
422  {
423  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
425  ic->setIE(val);
426  }
427  break;
428  case MISCREG_SATP:
429  {
430  // we only support bare and Sv39 mode; setting a different mode
431  // shall have no effect (see 4.1.12 in priv ISA manual)
432  SATP cur_val = readMiscRegNoEffect(misc_reg);
433  SATP new_val = val;
434  if (new_val.mode != AddrXlateMode::BARE &&
435  new_val.mode != AddrXlateMode::SV39)
436  new_val.mode = cur_val.mode;
437  setMiscRegNoEffect(misc_reg, new_val);
438  }
439  break;
440  case MISCREG_TSELECT:
441  {
442  // we don't support debugging, so always set a different value
443  // than written
444  setMiscRegNoEffect(misc_reg, val + 1);
445  }
446  break;
447  case MISCREG_ISA:
448  {
449  auto cur_val = readMiscRegNoEffect(misc_reg);
450  // only allow to disable compressed instructions
451  // if the following instruction is 4-byte aligned
452  if ((val & ISA_EXT_C_MASK) == 0 &&
453  bits(tc->pcState().npc(), 2, 0) != 0)
454  val |= cur_val & ISA_EXT_C_MASK;
455  setMiscRegNoEffect(misc_reg, val);
456  }
457  break;
458  case MISCREG_STATUS:
459  {
460  // SXL and UXL are hard-wired to 64 bit
461  auto cur = readMiscRegNoEffect(misc_reg);
463  val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
464  setMiscRegNoEffect(misc_reg, val);
465  }
466  break;
467  default:
468  setMiscRegNoEffect(misc_reg, val);
469  }
470  }
471 }
472 
473 void
475 {
476  DPRINTF(Checkpoint, "Serializing Riscv Misc Registers\n");
478 }
479 
480 void
482 {
483  DPRINTF(Checkpoint, "Unserializing Riscv Misc Registers\n");
485 }
486 
487 } // namespace RiscvISA
488 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::RiscvISA::MISCREG_HPMCOUNTER31
@ MISCREG_HPMCOUNTER31
Definition: misc.hh:105
gem5::RiscvISA::MISCREG_HPMEVENT11
@ MISCREG_HPMEVENT11
Definition: misc.hh:114
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:55
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:71
gem5::RiscvISA::MISCREG_HPMCOUNTER09
@ MISCREG_HPMCOUNTER09
Definition: misc.hh:83
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:56
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
warn
#define warn(...)
Definition: logging.hh:245
gem5::RiscvISA::MISCREG_PMPADDR11
@ MISCREG_PMPADDR11
Definition: misc.hh:166
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::MISCREG_HPMEVENT16
@ MISCREG_HPMEVENT16
Definition: misc.hh:119
gem5::RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: misc.hh:366
gem5::RiscvISA::MISCREG_HPMCOUNTER27
@ MISCREG_HPMCOUNTER27
Definition: misc.hh:101
gem5::RiscvISA::MISCREG_HPMCOUNTER08
@ MISCREG_HPMCOUNTER08
Definition: misc.hh:82
gem5::RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:93
gem5::Clocked::curCycle
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Definition: clocked_object.hh:195
gem5::RiscvISA::MISCREG_HPMCOUNTER12
@ MISCREG_HPMCOUNTER12
Definition: misc.hh:86
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:266
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::RiscvISA::MISCREG_SIDELEG
@ MISCREG_SIDELEG
Definition: misc.hh:173
gem5::BaseCPU::getInterruptController
BaseInterrupts * getInterruptController(ThreadID tid)
Definition: base.hh:229
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
pseudo_inst.hh
gem5::RiscvISA::MISCREG_SSCRATCH
@ MISCREG_SSCRATCH
Definition: misc.hh:176
gem5::RiscvISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:200
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RiscvISA::MISCREG_HPMEVENT19
@ MISCREG_HPMEVENT19
Definition: misc.hh:122
gem5::RiscvISA::MMU
Definition: mmu.hh:53
gem5::RiscvISA::MISCREG_PMPADDR09
@ MISCREG_PMPADDR09
Definition: misc.hh:164
gem5::RiscvISA::MISCREG_HPMCOUNTER26
@ MISCREG_HPMCOUNTER26
Definition: misc.hh:100
gem5::RiscvISA::MISCREG_MTVAL
@ MISCREG_MTVAL
Definition: misc.hh:150
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::RiscvISA::MISCREG_HPMEVENT15
@ MISCREG_HPMEVENT15
Definition: misc.hh:118
gem5::RiscvISA::MISCREG_HPMEVENT05
@ MISCREG_HPMEVENT05
Definition: misc.hh:108
gem5::RiscvISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:60
interrupts.hh
gem5::RiscvISA::MISCREG_SEDELEG
@ MISCREG_SEDELEG
Definition: misc.hh:172
gem5::RiscvISA::MISCREG_HPMCOUNTER07
@ MISCREG_HPMCOUNTER07
Definition: misc.hh:81
gem5::RiscvISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:190
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::RiscvISA::MISCREG_DPC
@ MISCREG_DPC
Definition: misc.hh:140
gem5::RiscvISA::MISCREG_ISA
@ MISCREG_ISA
Definition: misc.hh:66
gem5::RiscvISA::MISCREG_IE
@ MISCREG_IE
Definition: misc.hh:73
gem5::RiscvISA::MISCREG_HPMEVENT14
@ MISCREG_HPMEVENT14
Definition: misc.hh:117
float.hh
gem5::RiscvISA::MISCREG_CYCLE
@ MISCREG_CYCLE
Definition: misc.hh:74
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::RiscvISA::MISCREG_HPMCOUNTER14
@ MISCREG_HPMCOUNTER14
Definition: misc.hh:88
gem5::RiscvISA::ISA::Params
RiscvISAParams Params
Definition: isa.hh:75
isa.hh
gem5::RiscvISA::MISCREG_HPMEVENT22
@ MISCREG_HPMEVENT22
Definition: misc.hh:125
gem5::RiscvISA::MISCREG_HPMCOUNTER13
@ MISCREG_HPMCOUNTER13
Definition: misc.hh:87
gem5::BaseCPU::totalInsts
virtual Counter totalInsts() const =0
gem5::RiscvISA::MISCREG_HPMEVENT09
@ MISCREG_HPMEVENT09
Definition: misc.hh:112
misc.hh
gem5::RiscvISA::STATUS_UXL_MASK
const RegVal STATUS_UXL_MASK
Definition: misc.hh:590
gem5::RiscvISA::MISCREG_PMPADDR12
@ MISCREG_PMPADDR12
Definition: misc.hh:167
gem5::RiscvISA::MISCREG_SCAUSE
@ MISCREG_SCAUSE
Definition: misc.hh:178
gem5::RiscvISA::MISCREG_HPMCOUNTER06
@ MISCREG_HPMCOUNTER06
Definition: misc.hh:80
gem5::RiscvISA::MISCREG_MEDELEG
@ MISCREG_MEDELEG
Definition: misc.hh:143
gem5::RiscvISA::MISCREG_DSCRATCH
@ MISCREG_DSCRATCH
Definition: misc.hh:141
gem5::RiscvISA::MISCREG_HPMEVENT29
@ MISCREG_HPMEVENT29
Definition: misc.hh:132
gem5::RiscvISA::FS_OFFSET
const off_t FS_OFFSET
Definition: misc.hh:580
gem5::RiscvISA::MISCREG_PMPADDR01
@ MISCREG_PMPADDR01
Definition: misc.hh:156
gem5::RiscvISA::MISCREG_INSTRET
@ MISCREG_INSTRET
Definition: misc.hh:76
pmp.hh
gem5::RiscvISA::MISCREG_HPMCOUNTER29
@ MISCREG_HPMCOUNTER29
Definition: misc.hh:103
gem5::RiscvISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:269
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:64
bitfield.hh
gem5::RiscvISA::MISCREG_PMPADDR05
@ MISCREG_PMPADDR05
Definition: misc.hh:160
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::RiscvISA::MISCREG_HPMEVENT24
@ MISCREG_HPMEVENT24
Definition: misc.hh:127
gem5::RiscvISA::MISCREG_HPMCOUNTER25
@ MISCREG_HPMCOUNTER25
Definition: misc.hh:99
gem5::RiscvISA::SXL_OFFSET
const off_t SXL_OFFSET
Definition: misc.hh:578
gem5::RiscvISA::MISCREG_HPMEVENT31
@ MISCREG_HPMEVENT31
Definition: misc.hh:134
gem5::RiscvISA::MiscRegNames
const GEM5_VAR_USED std::array< const char *, NUM_MISCREGS > MiscRegNames
Definition: isa.cc:58
gem5::RiscvISA::MISCREG_FRM
@ MISCREG_FRM
Definition: misc.hh:188
gem5::RiscvISA::MISCREG_SEPC
@ MISCREG_SEPC
Definition: misc.hh:177
gem5::RiscvISA::MISCREG_MSCRATCH
@ MISCREG_MSCRATCH
Definition: misc.hh:147
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::RiscvISA::MISCREG_HPMCOUNTER18
@ MISCREG_HPMCOUNTER18
Definition: misc.hh:92
gem5::RiscvISA::MISCREG_IMPID
@ MISCREG_IMPID
Definition: misc.hh:69
gem5::RiscvISA::MISCREG_HPMCOUNTER17
@ MISCREG_HPMCOUNTER17
Definition: misc.hh:91
gem5::RiscvISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:481
gem5::RiscvISA::MISCREG_PMPADDR00
@ MISCREG_PMPADDR00
Definition: misc.hh:155
gem5::RiscvISA::STATUS_SXL_MASK
const RegVal STATUS_SXL_MASK
Definition: misc.hh:589
gem5::RiscvISA::MISCREG_HPMCOUNTER23
@ MISCREG_HPMCOUNTER23
Definition: misc.hh:97
gem5::RiscvISA::MISCREG_VENDORID
@ MISCREG_VENDORID
Definition: misc.hh:67
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:180
gem5::RiscvISA::MISCREG_PMPADDR08
@ MISCREG_PMPADDR08
Definition: misc.hh:163
gem5::RiscvISA::MISCREG_HPMEVENT21
@ MISCREG_HPMEVENT21
Definition: misc.hh:124
gem5::RiscvISA::MISCREG_HPMEVENT08
@ MISCREG_HPMEVENT08
Definition: misc.hh:111
gem5::RiscvISA::ISA::clear
void clear()
Definition: isa.cc:214
gem5::RiscvISA::MISCREG_MCAUSE
@ MISCREG_MCAUSE
Definition: misc.hh:149
gem5::RiscvISA::MISCREG_HPMEVENT13
@ MISCREG_HPMEVENT13
Definition: misc.hh:116
gem5::RiscvISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:256
gem5::RiscvISA::MISCREG_HPMEVENT20
@ MISCREG_HPMEVENT20
Definition: misc.hh:123
gem5::RiscvISA::MISCREG_HPMEVENT07
@ MISCREG_HPMEVENT07
Definition: misc.hh:110
gem5::RiscvISA::MISCREG_TDATA1
@ MISCREG_TDATA1
Definition: misc.hh:136
gem5::RiscvISA::MISCREG_HPMEVENT30
@ MISCREG_HPMEVENT30
Definition: misc.hh:133
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
gem5::RiscvISA::ISA::miscRegFile
std::vector< RegVal > miscRegFile
Definition: isa.hh:70
gem5::RiscvISA::MISCREG_PMPCFG2
@ MISCREG_PMPCFG2
Definition: misc.hh:153
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::MISCREG_TDATA3
@ MISCREG_TDATA3
Definition: misc.hh:138
gem5::RiscvISA::MISCREG_TSELECT
@ MISCREG_TSELECT
Definition: misc.hh:135
gem5::RiscvISA::MISCREG_HPMEVENT17
@ MISCREG_HPMEVENT17
Definition: misc.hh:120
gem5::RiscvISA::MISCREG_USCRATCH
@ MISCREG_USCRATCH
Definition: misc.hh:183
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::RiscvISA::Interrupts
Definition: interrupts.hh:56
gem5::RiscvISA::MISCREG_HPMCOUNTER04
@ MISCREG_HPMCOUNTER04
Definition: misc.hh:78
gem5::RiscvISA::MISCREG_PMPADDR15
@ MISCREG_PMPADDR15
Definition: misc.hh:170
gem5::RiscvISA::MISCREG_PMPADDR03
@ MISCREG_PMPADDR03
Definition: misc.hh:158
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::RiscvISA::MISCREG_PMPADDR10
@ MISCREG_PMPADDR10
Definition: misc.hh:165
gem5::RiscvISA::MISCREG_HPMEVENT27
@ MISCREG_HPMEVENT27
Definition: misc.hh:130
gem5::RiscvISA::MISCREG_HPMEVENT12
@ MISCREG_HPMEVENT12
Definition: misc.hh:115
gem5::RiscvISA::MISCREG_MEPC
@ MISCREG_MEPC
Definition: misc.hh:148
gem5::RiscvISA::MISCREG_HARTID
@ MISCREG_HARTID
Definition: misc.hh:70
gem5::RiscvISA::MISCREG_HPMCOUNTER22
@ MISCREG_HPMCOUNTER22
Definition: misc.hh:96
gem5::RiscvISA::MISCREG_HPMCOUNTER03
@ MISCREG_HPMCOUNTER03
Definition: misc.hh:77
gem5::RiscvISA::MISCREG_PMPADDR07
@ MISCREG_PMPADDR07
Definition: misc.hh:162
gem5::RiscvISA::MISCREG_HPMEVENT10
@ MISCREG_HPMEVENT10
Definition: misc.hh:113
gem5::RiscvISA::MISCREG_HPMEVENT26
@ MISCREG_HPMEVENT26
Definition: misc.hh:129
gem5::RiscvISA::MISCREG_ARCHID
@ MISCREG_ARCHID
Definition: misc.hh:68
mmu.hh
gem5::RiscvISA::MISCREG_UTVEC
@ MISCREG_UTVEC
Definition: misc.hh:182
base.hh
gem5::RiscvISA::MISCREG_HPMCOUNTER21
@ MISCREG_HPMCOUNTER21
Definition: misc.hh:95
gem5::RiscvISA::MISCREG_HPMEVENT23
@ MISCREG_HPMEVENT23
Definition: misc.hh:126
gem5::RiscvISA::MISCREG_PMPADDR06
@ MISCREG_PMPADDR06
Definition: misc.hh:161
gem5::RiscvISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:474
gem5::RiscvISA::MISCREG_PMPCFG0
@ MISCREG_PMPCFG0
Definition: misc.hh:151
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::RiscvISA::MISCREG_PMPADDR04
@ MISCREG_PMPADDR04
Definition: misc.hh:159
gem5::RiscvISA::MISCREG_PMPADDR14
@ MISCREG_PMPADDR14
Definition: misc.hh:169
gem5::RiscvISA::MISCREG_TIME
@ MISCREG_TIME
Definition: misc.hh:75
gem5::RiscvISA::MISCREG_UEPC
@ MISCREG_UEPC
Definition: misc.hh:184
gem5::RiscvISA::UXL_OFFSET
const off_t UXL_OFFSET
Definition: misc.hh:579
gem5::RiscvISA::MISCREG_HPMEVENT25
@ MISCREG_HPMEVENT25
Definition: misc.hh:128
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RiscvISA::MISCREG_MIDELEG
@ MISCREG_MIDELEG
Definition: misc.hh:144
gem5::RiscvISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:356
gem5::RiscvISA::MISCREG_PMPADDR02
@ MISCREG_PMPADDR02
Definition: misc.hh:157
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:54
gem5::RiscvISA::MISCREG_STVAL
@ MISCREG_STVAL
Definition: misc.hh:179
gem5::RiscvISA::MISCREG_HPMCOUNTER10
@ MISCREG_HPMCOUNTER10
Definition: misc.hh:84
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::RiscvISA::MISCREG_UCAUSE
@ MISCREG_UCAUSE
Definition: misc.hh:185
gem5::RiscvISA::MISCREG_HPMCOUNTER24
@ MISCREG_HPMCOUNTER24
Definition: misc.hh:98
gem5::RiscvISA::MISCREG_HPMCOUNTER30
@ MISCREG_HPMCOUNTER30
Definition: misc.hh:104
gem5::BaseISA
Definition: isa.hh:54
gem5::RiscvISA::MISCREG_UTVAL
@ MISCREG_UTVAL
Definition: misc.hh:186
gem5::RiscvISA::MISCREG_HPMCOUNTER16
@ MISCREG_HPMCOUNTER16
Definition: misc.hh:90
gem5::RiscvISA::MISCREG_MCOUNTEREN
@ MISCREG_MCOUNTEREN
Definition: misc.hh:146
gem5::RiscvISA::MISCREG_HPMEVENT28
@ MISCREG_HPMEVENT28
Definition: misc.hh:131
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::MISCREG_PRV
@ MISCREG_PRV
Definition: misc.hh:65
gem5::RiscvISA::ISA_EXT_C_MASK
const RegVal ISA_EXT_C_MASK
Definition: misc.hh:585
int.hh
gem5::RiscvISA::MISCREG_HPMEVENT18
@ MISCREG_HPMEVENT18
Definition: misc.hh:121
gem5::RiscvISA::MISCREG_HPMCOUNTER19
@ MISCREG_HPMCOUNTER19
Definition: misc.hh:93
gem5::RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::RiscvISA::ISA::hpmCounterEnabled
bool hpmCounterEnabled(int counter) const
Definition: isa.cc:233
gem5::RiscvISA::MISCREG_PMPADDR13
@ MISCREG_PMPADDR13
Definition: misc.hh:168
gem5::RiscvISA::MISCREG_TDATA2
@ MISCREG_TDATA2
Definition: misc.hh:137
gem5::RiscvISA::MISCREG_HPMEVENT04
@ MISCREG_HPMEVENT04
Definition: misc.hh:107
gem5::RiscvISA::MISCREG_FFLAGS
@ MISCREG_FFLAGS
Definition: misc.hh:187
pagetable.hh
gem5::RiscvISA::MISCREG_DCSR
@ MISCREG_DCSR
Definition: misc.hh:139
gem5::RiscvISA::MISCREG_IP
@ MISCREG_IP
Definition: misc.hh:72
gem5::RiscvISA::MISCREG_STVEC
@ MISCREG_STVEC
Definition: misc.hh:174
gem5::RiscvISA::MISCREG_HPMEVENT06
@ MISCREG_HPMEVENT06
Definition: misc.hh:109
gem5::RiscvISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:185
gem5::RiscvISA::MISCREG_HPMCOUNTER15
@ MISCREG_HPMCOUNTER15
Definition: misc.hh:89
gem5::RiscvISA::MISCREG_MTVEC
@ MISCREG_MTVEC
Definition: misc.hh:145
gem5::RiscvISA::MISCREG_SCOUNTEREN
@ MISCREG_SCOUNTEREN
Definition: misc.hh:175
gem5::RiscvISA::MISCREG_HPMCOUNTER11
@ MISCREG_HPMCOUNTER11
Definition: misc.hh:85
gem5::RiscvISA::MISCREG_HPMCOUNTER05
@ MISCREG_HPMCOUNTER05
Definition: misc.hh:79
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::RiscvISA::MISCREG_HPMCOUNTER28
@ MISCREG_HPMCOUNTER28
Definition: misc.hh:102
gem5::RiscvISA::MISCREG_HPMCOUNTER20
@ MISCREG_HPMCOUNTER20
Definition: misc.hh:94
gem5::RiscvISA::MISCREG_HPMEVENT03
@ MISCREG_HPMEVENT03
Definition: misc.hh:106
gem5::RiscvISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:344

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