gem5  v22.0.0.2
isa.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2016 RISC-V Foundation
3  * Copyright (c) 2016 The University of Virginia
4  * Copyright (c) 2020 Barkhausen Institut
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are
9  * met: redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer;
11  * redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution;
14  * neither the name of the copyright holders nor the names of its
15  * contributors may be used to endorse or promote products derived from
16  * this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include "arch/riscv/isa.hh"
32 
33 #include <ctime>
34 #include <set>
35 #include <sstream>
36 
37 #include "arch/riscv/interrupts.hh"
38 #include "arch/riscv/mmu.hh"
39 #include "arch/riscv/pagetable.hh"
40 #include "arch/riscv/pmp.hh"
41 #include "arch/riscv/regs/float.hh"
42 #include "arch/riscv/regs/int.hh"
43 #include "arch/riscv/regs/misc.hh"
44 #include "base/bitfield.hh"
45 #include "base/compiler.hh"
46 #include "base/logging.hh"
47 #include "base/trace.hh"
48 #include "cpu/base.hh"
49 #include "debug/Checkpoint.hh"
50 #include "debug/FloatRegs.hh"
51 #include "debug/IntRegs.hh"
52 #include "debug/LLSC.hh"
53 #include "debug/MiscRegs.hh"
54 #include "debug/RiscvMisc.hh"
55 #include "mem/packet.hh"
56 #include "mem/request.hh"
57 #include "params/RiscvISA.hh"
58 #include "sim/pseudo_inst.hh"
59 
60 namespace gem5
61 {
62 
63 namespace RiscvISA
64 {
65 
66 [[maybe_unused]] const std::array<const char *, NUM_MISCREGS> MiscRegNames = {{
67  [MISCREG_PRV] = "PRV",
68  [MISCREG_ISA] = "ISA",
69  [MISCREG_VENDORID] = "VENDORID",
70  [MISCREG_ARCHID] = "ARCHID",
71  [MISCREG_IMPID] = "IMPID",
72  [MISCREG_HARTID] = "HARTID",
73  [MISCREG_STATUS] = "STATUS",
74  [MISCREG_IP] = "IP",
75  [MISCREG_IE] = "IE",
76  [MISCREG_CYCLE] = "CYCLE",
77  [MISCREG_TIME] = "TIME",
78  [MISCREG_INSTRET] = "INSTRET",
79  [MISCREG_HPMCOUNTER03] = "HPMCOUNTER03",
80  [MISCREG_HPMCOUNTER04] = "HPMCOUNTER04",
81  [MISCREG_HPMCOUNTER05] = "HPMCOUNTER05",
82  [MISCREG_HPMCOUNTER06] = "HPMCOUNTER06",
83  [MISCREG_HPMCOUNTER07] = "HPMCOUNTER07",
84  [MISCREG_HPMCOUNTER08] = "HPMCOUNTER08",
85  [MISCREG_HPMCOUNTER09] = "HPMCOUNTER09",
86  [MISCREG_HPMCOUNTER10] = "HPMCOUNTER10",
87  [MISCREG_HPMCOUNTER11] = "HPMCOUNTER11",
88  [MISCREG_HPMCOUNTER12] = "HPMCOUNTER12",
89  [MISCREG_HPMCOUNTER13] = "HPMCOUNTER13",
90  [MISCREG_HPMCOUNTER14] = "HPMCOUNTER14",
91  [MISCREG_HPMCOUNTER15] = "HPMCOUNTER15",
92  [MISCREG_HPMCOUNTER16] = "HPMCOUNTER16",
93  [MISCREG_HPMCOUNTER17] = "HPMCOUNTER17",
94  [MISCREG_HPMCOUNTER18] = "HPMCOUNTER18",
95  [MISCREG_HPMCOUNTER19] = "HPMCOUNTER19",
96  [MISCREG_HPMCOUNTER20] = "HPMCOUNTER20",
97  [MISCREG_HPMCOUNTER21] = "HPMCOUNTER21",
98  [MISCREG_HPMCOUNTER22] = "HPMCOUNTER22",
99  [MISCREG_HPMCOUNTER23] = "HPMCOUNTER23",
100  [MISCREG_HPMCOUNTER24] = "HPMCOUNTER24",
101  [MISCREG_HPMCOUNTER25] = "HPMCOUNTER25",
102  [MISCREG_HPMCOUNTER26] = "HPMCOUNTER26",
103  [MISCREG_HPMCOUNTER27] = "HPMCOUNTER27",
104  [MISCREG_HPMCOUNTER28] = "HPMCOUNTER28",
105  [MISCREG_HPMCOUNTER29] = "HPMCOUNTER29",
106  [MISCREG_HPMCOUNTER30] = "HPMCOUNTER30",
107  [MISCREG_HPMCOUNTER31] = "HPMCOUNTER31",
108  [MISCREG_HPMEVENT03] = "HPMEVENT03",
109  [MISCREG_HPMEVENT04] = "HPMEVENT04",
110  [MISCREG_HPMEVENT05] = "HPMEVENT05",
111  [MISCREG_HPMEVENT06] = "HPMEVENT06",
112  [MISCREG_HPMEVENT07] = "HPMEVENT07",
113  [MISCREG_HPMEVENT08] = "HPMEVENT08",
114  [MISCREG_HPMEVENT09] = "HPMEVENT09",
115  [MISCREG_HPMEVENT10] = "HPMEVENT10",
116  [MISCREG_HPMEVENT11] = "HPMEVENT11",
117  [MISCREG_HPMEVENT12] = "HPMEVENT12",
118  [MISCREG_HPMEVENT13] = "HPMEVENT13",
119  [MISCREG_HPMEVENT14] = "HPMEVENT14",
120  [MISCREG_HPMEVENT15] = "HPMEVENT15",
121  [MISCREG_HPMEVENT16] = "HPMEVENT16",
122  [MISCREG_HPMEVENT17] = "HPMEVENT17",
123  [MISCREG_HPMEVENT18] = "HPMEVENT18",
124  [MISCREG_HPMEVENT19] = "HPMEVENT19",
125  [MISCREG_HPMEVENT20] = "HPMEVENT20",
126  [MISCREG_HPMEVENT21] = "HPMEVENT21",
127  [MISCREG_HPMEVENT22] = "HPMEVENT22",
128  [MISCREG_HPMEVENT23] = "HPMEVENT23",
129  [MISCREG_HPMEVENT24] = "HPMEVENT24",
130  [MISCREG_HPMEVENT25] = "HPMEVENT25",
131  [MISCREG_HPMEVENT26] = "HPMEVENT26",
132  [MISCREG_HPMEVENT27] = "HPMEVENT27",
133  [MISCREG_HPMEVENT28] = "HPMEVENT28",
134  [MISCREG_HPMEVENT29] = "HPMEVENT29",
135  [MISCREG_HPMEVENT30] = "HPMEVENT30",
136  [MISCREG_HPMEVENT31] = "HPMEVENT31",
137  [MISCREG_TSELECT] = "TSELECT",
138  [MISCREG_TDATA1] = "TDATA1",
139  [MISCREG_TDATA2] = "TDATA2",
140  [MISCREG_TDATA3] = "TDATA3",
141  [MISCREG_DCSR] = "DCSR",
142  [MISCREG_DPC] = "DPC",
143  [MISCREG_DSCRATCH] = "DSCRATCH",
144 
145  [MISCREG_MEDELEG] = "MEDELEG",
146  [MISCREG_MIDELEG] = "MIDELEG",
147  [MISCREG_MTVEC] = "MTVEC",
148  [MISCREG_MCOUNTEREN] = "MCOUNTEREN",
149  [MISCREG_MSCRATCH] = "MSCRATCH",
150  [MISCREG_MEPC] = "MEPC",
151  [MISCREG_MCAUSE] = "MCAUSE",
152  [MISCREG_MTVAL] = "MTVAL",
153  [MISCREG_PMPCFG0] = "PMPCFG0",
154  // pmpcfg1 rv32 only
155  [MISCREG_PMPCFG2] = "PMPCFG2",
156  // pmpcfg3 rv32 only
157  [MISCREG_PMPADDR00] = "PMPADDR00",
158  [MISCREG_PMPADDR01] = "PMPADDR01",
159  [MISCREG_PMPADDR02] = "PMPADDR02",
160  [MISCREG_PMPADDR03] = "PMPADDR03",
161  [MISCREG_PMPADDR04] = "PMPADDR04",
162  [MISCREG_PMPADDR05] = "PMPADDR05",
163  [MISCREG_PMPADDR06] = "PMPADDR06",
164  [MISCREG_PMPADDR07] = "PMPADDR07",
165  [MISCREG_PMPADDR08] = "PMPADDR08",
166  [MISCREG_PMPADDR09] = "PMPADDR09",
167  [MISCREG_PMPADDR10] = "PMPADDR10",
168  [MISCREG_PMPADDR11] = "PMPADDR11",
169  [MISCREG_PMPADDR12] = "PMPADDR12",
170  [MISCREG_PMPADDR13] = "PMPADDR13",
171  [MISCREG_PMPADDR14] = "PMPADDR14",
172  [MISCREG_PMPADDR15] = "PMPADDR15",
173 
174  [MISCREG_SEDELEG] = "SEDELEG",
175  [MISCREG_SIDELEG] = "SIDELEG",
176  [MISCREG_STVEC] = "STVEC",
177  [MISCREG_SCOUNTEREN] = "SCOUNTEREN",
178  [MISCREG_SSCRATCH] = "SSCRATCH",
179  [MISCREG_SEPC] = "SEPC",
180  [MISCREG_SCAUSE] = "SCAUSE",
181  [MISCREG_STVAL] = "STVAL",
182  [MISCREG_SATP] = "SATP",
183 
184  [MISCREG_UTVEC] = "UTVEC",
185  [MISCREG_USCRATCH] = "USCRATCH",
186  [MISCREG_UEPC] = "UEPC",
187  [MISCREG_UCAUSE] = "UCAUSE",
188  [MISCREG_UTVAL] = "UTVAL",
189  [MISCREG_FFLAGS] = "FFLAGS",
190  [MISCREG_FRM] = "FRM",
191 
192  [MISCREG_NMIVEC] = "NMIVEC",
193  [MISCREG_NMIE] = "NMIE",
194  [MISCREG_NMIP] = "NMIP",
195 }};
196 
198 {
199  _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
200  _regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
201  _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
202  _regClasses.emplace_back(2, debug::IntRegs); // Not applicable to RISCV
203  _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
204  _regClasses.emplace_back(0, debug::IntRegs); // Not applicable to RISCV
205  _regClasses.emplace_back(NUM_MISCREGS, debug::MiscRegs);
206 
207  miscRegFile.resize(NUM_MISCREGS);
208  clear();
209 }
210 
211 bool ISA::inUserMode() const
212 {
213  return miscRegFile[MISCREG_PRV] == PRV_U;
214 }
215 
216 void
218 {
219  // First loop through the integer registers.
220  for (int i = 0; i < NumIntRegs; ++i)
221  tc->setIntReg(i, src->readIntReg(i));
222 
223  // Second loop through the float registers.
224  for (int i = 0; i < NumFloatRegs; ++i)
225  tc->setFloatReg(i, src->readFloatReg(i));
226 
227  // Lastly copy PC/NPC
228  tc->pcState(src->pcState());
229 }
230 
232 {
233  std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
234 
236  miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x14112D;
240  miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
241  (1ULL << FS_OFFSET);
244  // don't set it to zero; software may try to determine the supported
245  // triggers, starting at zero. simply set a different value here.
247  // NMI is always enabled.
249 }
250 
251 bool
252 ISA::hpmCounterEnabled(int misc_reg) const
253 {
254  int hpmcounter = misc_reg - MISCREG_CYCLE;
255  if (hpmcounter < 0 || hpmcounter > 31)
256  panic("Illegal HPM counter %d\n", hpmcounter);
257  int counteren;
258  switch (readMiscRegNoEffect(MISCREG_PRV)) {
259  case PRV_M:
260  return true;
261  case PRV_S:
262  counteren = MISCREG_MCOUNTEREN;
263  break;
264  case PRV_U:
265  counteren = MISCREG_SCOUNTEREN;
266  break;
267  default:
268  panic("Unknown privilege level %d\n", miscRegFile[MISCREG_PRV]);
269  return false;
270  }
271  return (miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
272 }
273 
274 RegVal
275 ISA::readMiscRegNoEffect(int misc_reg) const
276 {
277  if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
278  // Illegal CSR
279  panic("Illegal CSR index %#x\n", misc_reg);
280  return -1;
281  }
282  DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#x.\n",
283  MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]);
284  return miscRegFile[misc_reg];
285 }
286 
287 RegVal
288 ISA::readMiscReg(int misc_reg)
289 {
290  switch (misc_reg) {
291  case MISCREG_HARTID:
292  return tc->contextId();
293  case MISCREG_CYCLE:
295  DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
296  tc->getCpuPtr()->curCycle());
297  return tc->getCpuPtr()->curCycle();
298  } else {
299  warn("Cycle counter disabled.\n");
300  return 0;
301  }
302  case MISCREG_TIME:
304  DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
305  std::time(nullptr));
307  } else {
308  warn("Wall clock disabled.\n");
309  return 0;
310  }
311  case MISCREG_INSTRET:
313  DPRINTF(RiscvMisc, "Instruction counter at: %llu.\n",
314  tc->getCpuPtr()->totalInsts());
315  return tc->getCpuPtr()->totalInsts();
316  } else {
317  warn("Instruction counter disabled.\n");
318  return 0;
319  }
320  case MISCREG_IP:
321  {
322  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
323  tc->getCpuPtr()->getInterruptController(tc->threadId()));
324  return ic->readIP();
325  }
326  case MISCREG_IE:
327  {
328  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
329  tc->getCpuPtr()->getInterruptController(tc->threadId()));
330  return ic->readIE();
331  }
332  case MISCREG_SEPC:
333  case MISCREG_MEPC:
334  {
335  auto misa = readMiscRegNoEffect(MISCREG_ISA);
336  auto val = readMiscRegNoEffect(misc_reg);
337  // if compressed instructions are disabled, epc[1] is set to 0
338  if ((misa & ISA_EXT_C_MASK) == 0)
339  return mbits(val, 63, 2);
340  // epc[0] is always 0
341  else
342  return mbits(val, 63, 1);
343  }
344  default:
345  // Try reading HPM counters
346  // As a placeholder, all HPM counters are just cycle counters
347  if (misc_reg >= MISCREG_HPMCOUNTER03 &&
348  misc_reg <= MISCREG_HPMCOUNTER31) {
349  if (hpmCounterEnabled(misc_reg)) {
350  DPRINTF(RiscvMisc, "HPM counter %d: %llu.\n",
351  misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle());
352  return tc->getCpuPtr()->curCycle();
353  } else {
354  warn("HPM counter %d disabled.\n", misc_reg - MISCREG_CYCLE);
355  return 0;
356  }
357  }
358  return readMiscRegNoEffect(misc_reg);
359  }
360 }
361 
362 void
364 {
365  if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
366  // Illegal CSR
367  panic("Illegal CSR index %#x\n", misc_reg);
368  }
369  DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n",
370  MiscRegNames[misc_reg], misc_reg, val);
371  miscRegFile[misc_reg] = val;
372 }
373 
374 void
375 ISA::setMiscReg(int misc_reg, RegVal val)
376 {
377  if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
378  // Ignore writes to HPM counters for now
379  warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
380  } else {
381  switch (misc_reg) {
382 
383  // From section 3.7.1 of RISCV priv. specs
384  // V1.12, the odd-numbered configuration
385  // registers are illegal for RV64 and
386  // each 64 bit CFG register hold configurations
387  // for 8 PMP entries.
388 
389  case MISCREG_PMPCFG0:
390  case MISCREG_PMPCFG2:
391  {
392  // PMP registers should only be modified in M mode
394 
395  // Specs do not seem to mention what should be
396  // configured first, cfg or address regs!
397  // qemu seems to update the tables when
398  // pmp addr regs are written (with the assumption
399  // that cfg regs are already written)
400 
401  for (int i=0; i < sizeof(val); i++) {
402 
403  uint8_t cfg_val = (val >> (8*i)) & 0xff;
404  auto mmu = dynamic_cast<RiscvISA::MMU *>
405  (tc->getMMUPtr());
406 
407  // Form pmp_index using the index i and
408  // PMPCFG register number
409  // Note: MISCREG_PMPCFG2 - MISCREG_PMPCFG0 = 1
410  // 8*(misc_reg-MISCREG_PMPCFG0) will be useful
411  // if a system contains more than 16 PMP entries
412  uint32_t pmp_index = i+(8*(misc_reg-MISCREG_PMPCFG0));
413  mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
414  }
415 
416  setMiscRegNoEffect(misc_reg, val);
417  }
418  break;
420  {
421  // PMP registers should only be modified in M mode
423 
424  auto mmu = dynamic_cast<RiscvISA::MMU *>
425  (tc->getMMUPtr());
426  uint32_t pmp_index = misc_reg-MISCREG_PMPADDR00;
427  mmu->getPMP()->pmpUpdateAddr(pmp_index, val);
428 
429  setMiscRegNoEffect(misc_reg, val);
430  }
431  break;
432 
433  case MISCREG_IP:
434  {
435  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
436  tc->getCpuPtr()->getInterruptController(tc->threadId()));
437  ic->setIP(val);
438  }
439  break;
440  case MISCREG_IE:
441  {
442  auto ic = dynamic_cast<RiscvISA::Interrupts *>(
443  tc->getCpuPtr()->getInterruptController(tc->threadId()));
444  ic->setIE(val);
445  }
446  break;
447  case MISCREG_SATP:
448  {
449  // we only support bare and Sv39 mode; setting a different mode
450  // shall have no effect (see 4.1.12 in priv ISA manual)
451  SATP cur_val = readMiscRegNoEffect(misc_reg);
452  SATP new_val = val;
453  if (new_val.mode != AddrXlateMode::BARE &&
454  new_val.mode != AddrXlateMode::SV39)
455  new_val.mode = cur_val.mode;
456  setMiscRegNoEffect(misc_reg, new_val);
457  }
458  break;
459  case MISCREG_TSELECT:
460  {
461  // we don't support debugging, so always set a different value
462  // than written
463  setMiscRegNoEffect(misc_reg, val + 1);
464  }
465  break;
466  case MISCREG_ISA:
467  {
468  auto cur_val = readMiscRegNoEffect(misc_reg);
469  // only allow to disable compressed instructions
470  // if the following instruction is 4-byte aligned
471  if ((val & ISA_EXT_C_MASK) == 0 &&
473  2, 0) != 0) {
474  val |= cur_val & ISA_EXT_C_MASK;
475  }
476  setMiscRegNoEffect(misc_reg, val);
477  }
478  break;
479  case MISCREG_STATUS:
480  {
481  // SXL and UXL are hard-wired to 64 bit
482  auto cur = readMiscRegNoEffect(misc_reg);
484  val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
485  setMiscRegNoEffect(misc_reg, val);
486  }
487  break;
488  default:
489  setMiscRegNoEffect(misc_reg, val);
490  }
491  }
492 }
493 
494 void
496 {
497  DPRINTF(Checkpoint, "Serializing Riscv Misc Registers\n");
499 }
500 
501 void
503 {
504  DPRINTF(Checkpoint, "Unserializing Riscv Misc Registers\n");
506 }
507 
508 const int WARN_FAILURE = 10000;
509 
511 std::unordered_map<int, Addr> load_reservation_addrs;
512 
513 void
515 {
516  Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
517 
518  if (load_reservation_addr == INVALID_RESERVATION_ADDR)
519  return;
520  Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
521  DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
522  if ((load_reservation_addr & cacheBlockMask) == snoop_addr)
523  load_reservation_addr = INVALID_RESERVATION_ADDR;
524 }
525 
526 
527 void
529 {
530  Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
531 
532  load_reservation_addr = req->getPaddr() & ~0xF;
533  DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
534  req->contextId(), req->getPaddr() & ~0xF);
535 }
536 
537 bool
538 ISA::handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
539 {
540  Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
541  bool lr_addr_empty = (load_reservation_addr == INVALID_RESERVATION_ADDR);
542 
543  // Normally RISC-V uses zero to indicate success and nonzero to indicate
544  // failure (right now only 1 is reserved), but in gem5 zero indicates
545  // failure and one indicates success, so here we conform to that (it should
546  // be switched in the instruction's implementation)
547 
548  DPRINTF(LLSC, "[cid:%d]: load_reservation_addrs empty? %s.\n",
549  req->contextId(),
550  lr_addr_empty ? "yes" : "no");
551  if (!lr_addr_empty) {
552  DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
553  req->getPaddr() & ~0xF);
554  DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
555  load_reservation_addr);
556  }
557  if (lr_addr_empty
558  || load_reservation_addr != ((req->getPaddr() & ~0xF))) {
559  req->setExtraData(0);
560  int stCondFailures = tc->readStCondFailures();
561  tc->setStCondFailures(++stCondFailures);
562  if (stCondFailures % WARN_FAILURE == 0) {
563  warn("%i: context %d: %d consecutive SC failures.\n",
564  curTick(), tc->contextId(), stCondFailures);
565  }
566  return false;
567  }
568  if (req->isUncacheable()) {
569  req->setExtraData(2);
570  }
571 
572  return true;
573 }
574 
575 void
577 {
578  tc->getCpuPtr()->wakeup(tc->threadId());
579 }
580 
581 } // namespace RiscvISA
582 } // namespace gem5
583 
584 std::ostream &
586 {
587  switch (pm) {
589  return os << "PRV_U";
591  return os << "PRV_S";
593  return os << "PRV_M";
594  }
595  return os << "PRV_<invalid>";
596 }
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::RiscvISA::MISCREG_HPMCOUNTER31
@ MISCREG_HPMCOUNTER31
Definition: misc.hh:105
gem5::RiscvISA::MISCREG_HPMEVENT11
@ MISCREG_HPMEVENT11
Definition: misc.hh:114
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:56
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:71
gem5::RiscvISA::MISCREG_HPMCOUNTER09
@ MISCREG_HPMCOUNTER09
Definition: misc.hh:83
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:57
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const
Definition: thread_context.hh:210
warn
#define warn(...)
Definition: logging.hh:246
gem5::RiscvISA::MISCREG_PMPADDR11
@ MISCREG_PMPADDR11
Definition: misc.hh:166
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::MISCREG_HPMEVENT16
@ MISCREG_HPMEVENT16
Definition: misc.hh:119
gem5::RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: misc.hh:376
gem5::RiscvISA::MISCREG_HPMCOUNTER27
@ MISCREG_HPMCOUNTER27
Definition: misc.hh:101
gem5::RiscvISA::MISCREG_HPMCOUNTER08
@ MISCREG_HPMCOUNTER08
Definition: misc.hh:82
gem5::RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:108
gem5::RiscvISA::MISCREG_HPMCOUNTER12
@ MISCREG_HPMCOUNTER12
Definition: misc.hh:86
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:304
gem5::RiscvISA::MISCREG_SIDELEG
@ MISCREG_SIDELEG
Definition: misc.hh:173
gem5::RiscvISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.cc:211
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
pseudo_inst.hh
gem5::RiscvISA::MISCREG_SSCRATCH
@ MISCREG_SSCRATCH
Definition: misc.hh:176
gem5::RiscvISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:217
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RiscvISA::MISCREG_HPMEVENT19
@ MISCREG_HPMEVENT19
Definition: misc.hh:122
gem5::RiscvISA::MMU
Definition: mmu.hh:54
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::RiscvISA::MISCREG_PMPADDR09
@ MISCREG_PMPADDR09
Definition: misc.hh:164
gem5::RiscvISA::MISCREG_HPMCOUNTER26
@ MISCREG_HPMCOUNTER26
Definition: misc.hh:100
operator<<
std::ostream & operator<<(std::ostream &os, gem5::RiscvISA::PrivilegeMode pm)
Definition: isa.cc:585
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:53
gem5::RiscvISA::MISCREG_MTVAL
@ MISCREG_MTVAL
Definition: misc.hh:150
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::RiscvISA::MISCREG_HPMEVENT15
@ MISCREG_HPMEVENT15
Definition: misc.hh:118
gem5::RiscvISA::MISCREG_HPMEVENT05
@ MISCREG_HPMEVENT05
Definition: misc.hh:108
gem5::RiscvISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:60
interrupts.hh
gem5::RiscvISA::MISCREG_SEDELEG
@ MISCREG_SEDELEG
Definition: misc.hh:172
gem5::RiscvISA::MISCREG_HPMCOUNTER07
@ MISCREG_HPMCOUNTER07
Definition: misc.hh:81
gem5::RiscvISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:200
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::RiscvISA::MISCREG_DPC
@ MISCREG_DPC
Definition: misc.hh:140
gem5::RiscvISA::INVALID_RESERVATION_ADDR
const Addr INVALID_RESERVATION_ADDR
Definition: isa.cc:510
gem5::RiscvISA::MISCREG_ISA
@ MISCREG_ISA
Definition: misc.hh:66
gem5::RiscvISA::MISCREG_IE
@ MISCREG_IE
Definition: misc.hh:73
gem5::RiscvISA::MISCREG_HPMEVENT14
@ MISCREG_HPMEVENT14
Definition: misc.hh:117
float.hh
gem5::RiscvISA::MISCREG_CYCLE
@ MISCREG_CYCLE
Definition: misc.hh:74
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::RiscvISA::MISCREG_HPMCOUNTER14
@ MISCREG_HPMCOUNTER14
Definition: misc.hh:88
gem5::RiscvISA::ISA::Params
RiscvISAParams Params
Definition: isa.hh:76
isa.hh
request.hh
gem5::RiscvISA::MISCREG_HPMEVENT22
@ MISCREG_HPMEVENT22
Definition: misc.hh:125
gem5::RiscvISA::MISCREG_HPMCOUNTER13
@ MISCREG_HPMCOUNTER13
Definition: misc.hh:87
gem5::RiscvISA::MISCREG_HPMEVENT09
@ MISCREG_HPMEVENT09
Definition: misc.hh:112
misc.hh
gem5::RiscvISA::STATUS_UXL_MASK
const RegVal STATUS_UXL_MASK
Definition: misc.hh:600
gem5::RiscvISA::MISCREG_PMPADDR12
@ MISCREG_PMPADDR12
Definition: misc.hh:167
packet.hh
gem5::RiscvISA::MISCREG_SCAUSE
@ MISCREG_SCAUSE
Definition: misc.hh:178
gem5::RiscvISA::MISCREG_NMIE
@ MISCREG_NMIE
Definition: misc.hh:196
gem5::RiscvISA::MISCREG_HPMCOUNTER06
@ MISCREG_HPMCOUNTER06
Definition: misc.hh:80
gem5::RiscvISA::MISCREG_MEDELEG
@ MISCREG_MEDELEG
Definition: misc.hh:143
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
gem5::RiscvISA::MISCREG_DSCRATCH
@ MISCREG_DSCRATCH
Definition: misc.hh:141
gem5::RiscvISA::MISCREG_HPMEVENT29
@ MISCREG_HPMEVENT29
Definition: misc.hh:132
gem5::RiscvISA::FS_OFFSET
const off_t FS_OFFSET
Definition: misc.hh:590
gem5::RiscvISA::MISCREG_PMPADDR01
@ MISCREG_PMPADDR01
Definition: misc.hh:156
gem5::RiscvISA::MISCREG_INSTRET
@ MISCREG_INSTRET
Definition: misc.hh:76
pmp.hh
gem5::RiscvISA::MISCREG_HPMCOUNTER29
@ MISCREG_HPMCOUNTER29
Definition: misc.hh:103
gem5::RiscvISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:288
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
bitfield.hh
gem5::RiscvISA::MISCREG_PMPADDR05
@ MISCREG_PMPADDR05
Definition: misc.hh:160
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::RiscvISA::MISCREG_HPMEVENT24
@ MISCREG_HPMEVENT24
Definition: misc.hh:127
gem5::GenericISA::PCStateWithNext::npc
Addr npc() const
Definition: pcstate.hh:266
gem5::RiscvISA::MISCREG_HPMCOUNTER25
@ MISCREG_HPMCOUNTER25
Definition: misc.hh:99
gem5::RiscvISA::SXL_OFFSET
const off_t SXL_OFFSET
Definition: misc.hh:588
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
gem5::RiscvISA::MISCREG_HPMEVENT31
@ MISCREG_HPMEVENT31
Definition: misc.hh:134
gem5::RiscvISA::MISCREG_FRM
@ MISCREG_FRM
Definition: misc.hh:188
gem5::RiscvISA::MISCREG_SEPC
@ MISCREG_SEPC
Definition: misc.hh:177
gem5::RiscvISA::MISCREG_MSCRATCH
@ MISCREG_MSCRATCH
Definition: misc.hh:147
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::RiscvISA::MISCREG_HPMCOUNTER18
@ MISCREG_HPMCOUNTER18
Definition: misc.hh:92
gem5::RiscvISA::MISCREG_IMPID
@ MISCREG_IMPID
Definition: misc.hh:69
gem5::RiscvISA::MISCREG_HPMCOUNTER17
@ MISCREG_HPMCOUNTER17
Definition: misc.hh:91
gem5::RiscvISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:502
gem5::RiscvISA::MISCREG_PMPADDR00
@ MISCREG_PMPADDR00
Definition: misc.hh:155
gem5::RiscvISA::STATUS_SXL_MASK
const RegVal STATUS_SXL_MASK
Definition: misc.hh:599
gem5::RiscvISA::MISCREG_HPMCOUNTER23
@ MISCREG_HPMCOUNTER23
Definition: misc.hh:97
gem5::RiscvISA::MISCREG_VENDORID
@ MISCREG_VENDORID
Definition: misc.hh:67
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:180
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::RiscvISA::MISCREG_PMPADDR08
@ MISCREG_PMPADDR08
Definition: misc.hh:163
gem5::RiscvISA::MISCREG_HPMEVENT21
@ MISCREG_HPMEVENT21
Definition: misc.hh:124
gem5::RiscvISA::MISCREG_HPMEVENT08
@ MISCREG_HPMEVENT08
Definition: misc.hh:111
gem5::RiscvISA::ISA::clear
void clear()
Definition: isa.cc:231
gem5::RiscvISA::MISCREG_MCAUSE
@ MISCREG_MCAUSE
Definition: misc.hh:149
gem5::RiscvISA::MISCREG_HPMEVENT13
@ MISCREG_HPMEVENT13
Definition: misc.hh:116
gem5::RiscvISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:275
gem5::RiscvISA::MISCREG_HPMEVENT20
@ MISCREG_HPMEVENT20
Definition: misc.hh:123
gem5::RiscvISA::MISCREG_HPMEVENT07
@ MISCREG_HPMEVENT07
Definition: misc.hh:110
gem5::RiscvISA::MISCREG_TDATA1
@ MISCREG_TDATA1
Definition: misc.hh:136
gem5::RiscvISA::MISCREG_HPMEVENT30
@ MISCREG_HPMEVENT30
Definition: misc.hh:133
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::RiscvISA::ISA::miscRegFile
std::vector< RegVal > miscRegFile
Definition: isa.hh:71
gem5::RiscvISA::MISCREG_PMPCFG2
@ MISCREG_PMPCFG2
Definition: misc.hh:153
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::MISCREG_TDATA3
@ MISCREG_TDATA3
Definition: misc.hh:138
gem5::RiscvISA::MISCREG_TSELECT
@ MISCREG_TSELECT
Definition: misc.hh:135
gem5::RiscvISA::MISCREG_HPMEVENT17
@ MISCREG_HPMEVENT17
Definition: misc.hh:120
gem5::RiscvISA::MISCREG_USCRATCH
@ MISCREG_USCRATCH
Definition: misc.hh:183
gem5::ThreadContext::readStCondFailures
virtual unsigned readStCondFailures() const =0
gem5::RiscvISA::ISA::handleLockedRead
void handleLockedRead(const RequestPtr &req) override
Definition: isa.cc:528
gem5::RiscvISA::Interrupts
Definition: interrupts.hh:56
gem5::RiscvISA::MISCREG_NMIVEC
@ MISCREG_NMIVEC
Definition: misc.hh:194
gem5::RiscvISA::MISCREG_HPMCOUNTER04
@ MISCREG_HPMCOUNTER04
Definition: misc.hh:78
gem5::RiscvISA::MISCREG_PMPADDR15
@ MISCREG_PMPADDR15
Definition: misc.hh:170
gem5::RiscvISA::ISA::handleLockedSnoop
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
Definition: isa.cc:514
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::MISCREG_PMPADDR03
@ MISCREG_PMPADDR03
Definition: misc.hh:158
gem5::RiscvISA::MISCREG_PMPADDR10
@ MISCREG_PMPADDR10
Definition: misc.hh:165
gem5::RiscvISA::MISCREG_HPMEVENT27
@ MISCREG_HPMEVENT27
Definition: misc.hh:130
gem5::RiscvISA::MISCREG_HPMEVENT12
@ MISCREG_HPMEVENT12
Definition: misc.hh:115
gem5::RiscvISA::MISCREG_MEPC
@ MISCREG_MEPC
Definition: misc.hh:148
gem5::RiscvISA::MISCREG_HARTID
@ MISCREG_HARTID
Definition: misc.hh:70
gem5::RiscvISA::MISCREG_HPMCOUNTER22
@ MISCREG_HPMCOUNTER22
Definition: misc.hh:96
gem5::RiscvISA::MISCREG_HPMCOUNTER03
@ MISCREG_HPMCOUNTER03
Definition: misc.hh:77
gem5::RiscvISA::MISCREG_PMPADDR07
@ MISCREG_PMPADDR07
Definition: misc.hh:162
gem5::RiscvISA::MISCREG_HPMEVENT10
@ MISCREG_HPMEVENT10
Definition: misc.hh:113
gem5::RiscvISA::MISCREG_HPMEVENT26
@ MISCREG_HPMEVENT26
Definition: misc.hh:129
gem5::RiscvISA::MISCREG_ARCHID
@ MISCREG_ARCHID
Definition: misc.hh:68
mmu.hh
gem5::RiscvISA::MISCREG_UTVEC
@ MISCREG_UTVEC
Definition: misc.hh:182
base.hh
gem5::RiscvISA::MISCREG_HPMCOUNTER21
@ MISCREG_HPMCOUNTER21
Definition: misc.hh:95
gem5::RiscvISA::MISCREG_HPMEVENT23
@ MISCREG_HPMEVENT23
Definition: misc.hh:126
gem5::RiscvISA::MISCREG_PMPADDR06
@ MISCREG_PMPADDR06
Definition: misc.hh:161
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::RiscvISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:495
gem5::RiscvISA::MISCREG_PMPCFG0
@ MISCREG_PMPCFG0
Definition: misc.hh:151
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::RiscvISA::ISA::globalClearExclusive
void globalClearExclusive() override
Definition: isa.cc:576
gem5::RiscvISA::MISCREG_PMPADDR04
@ MISCREG_PMPADDR04
Definition: misc.hh:159
gem5::RiscvISA::MISCREG_PMPADDR14
@ MISCREG_PMPADDR14
Definition: misc.hh:169
logging.hh
gem5::RiscvISA::MISCREG_TIME
@ MISCREG_TIME
Definition: misc.hh:75
gem5::RiscvISA::MiscRegNames
const std::array< const char *, NUM_MISCREGS > MiscRegNames
Definition: isa.cc:66
gem5::RiscvISA::MISCREG_UEPC
@ MISCREG_UEPC
Definition: misc.hh:184
gem5::RiscvISA::UXL_OFFSET
const off_t UXL_OFFSET
Definition: misc.hh:589
gem5::RiscvISA::MISCREG_HPMEVENT25
@ MISCREG_HPMEVENT25
Definition: misc.hh:128
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RiscvISA::MISCREG_MIDELEG
@ MISCREG_MIDELEG
Definition: misc.hh:144
gem5::RiscvISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:375
gem5::RiscvISA::MISCREG_PMPADDR02
@ MISCREG_PMPADDR02
Definition: misc.hh:157
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:55
gem5::RiscvISA::MISCREG_STVAL
@ MISCREG_STVAL
Definition: misc.hh:179
gem5::RiscvISA::MISCREG_HPMCOUNTER10
@ MISCREG_HPMCOUNTER10
Definition: misc.hh:84
gem5::ThreadContext::threadId
virtual int threadId() const =0
trace.hh
gem5::RiscvISA::MISCREG_UCAUSE
@ MISCREG_UCAUSE
Definition: misc.hh:185
gem5::RiscvISA::MISCREG_HPMCOUNTER24
@ MISCREG_HPMCOUNTER24
Definition: misc.hh:98
gem5::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:247
gem5::RiscvISA::WARN_FAILURE
const int WARN_FAILURE
Definition: isa.cc:508
gem5::RiscvISA::ISA::handleLockedWrite
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
Definition: isa.cc:538
gem5::RiscvISA::MISCREG_HPMCOUNTER30
@ MISCREG_HPMCOUNTER30
Definition: misc.hh:104
gem5::BaseISA
Definition: isa.hh:57
gem5::RiscvISA::MISCREG_UTVAL
@ MISCREG_UTVAL
Definition: misc.hh:186
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5::RiscvISA::MISCREG_HPMCOUNTER16
@ MISCREG_HPMCOUNTER16
Definition: misc.hh:90
gem5::ThreadContext::setStCondFailures
virtual void setStCondFailures(unsigned sc_failures)=0
gem5::RiscvISA::MISCREG_MCOUNTEREN
@ MISCREG_MCOUNTEREN
Definition: misc.hh:146
gem5::RiscvISA::MISCREG_HPMEVENT28
@ MISCREG_HPMEVENT28
Definition: misc.hh:131
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::MISCREG_PRV
@ MISCREG_PRV
Definition: misc.hh:65
gem5::RiscvISA::ISA_EXT_C_MASK
const RegVal ISA_EXT_C_MASK
Definition: misc.hh:595
int.hh
gem5::RiscvISA::MISCREG_HPMEVENT18
@ MISCREG_HPMEVENT18
Definition: misc.hh:121
gem5::RiscvISA::MISCREG_HPMCOUNTER19
@ MISCREG_HPMCOUNTER19
Definition: misc.hh:93
gem5::RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::RiscvISA::ISA::hpmCounterEnabled
bool hpmCounterEnabled(int counter) const
Definition: isa.cc:252
gem5::RiscvISA::MISCREG_PMPADDR13
@ MISCREG_PMPADDR13
Definition: misc.hh:168
gem5::RiscvISA::MISCREG_TDATA2
@ MISCREG_TDATA2
Definition: misc.hh:137
gem5::RiscvISA::MISCREG_HPMEVENT04
@ MISCREG_HPMEVENT04
Definition: misc.hh:107
gem5::RiscvISA::MISCREG_FFLAGS
@ MISCREG_FFLAGS
Definition: misc.hh:187
pagetable.hh
gem5::RiscvISA::MISCREG_DCSR
@ MISCREG_DCSR
Definition: misc.hh:139
gem5::RiscvISA::MISCREG_IP
@ MISCREG_IP
Definition: misc.hh:72
gem5::RiscvISA::MISCREG_STVEC
@ MISCREG_STVEC
Definition: misc.hh:174
gem5::RiscvISA::MISCREG_HPMEVENT06
@ MISCREG_HPMEVENT06
Definition: misc.hh:109
gem5::RiscvISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:197
gem5::RiscvISA::MISCREG_HPMCOUNTER15
@ MISCREG_HPMCOUNTER15
Definition: misc.hh:89
gem5::RiscvISA::MISCREG_NMIP
@ MISCREG_NMIP
Definition: misc.hh:198
gem5::RiscvISA::MISCREG_MTVEC
@ MISCREG_MTVEC
Definition: misc.hh:145
gem5::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:241
gem5::RiscvISA::MISCREG_SCOUNTEREN
@ MISCREG_SCOUNTEREN
Definition: misc.hh:175
gem5::RiscvISA::MISCREG_HPMCOUNTER11
@ MISCREG_HPMCOUNTER11
Definition: misc.hh:85
gem5::RiscvISA::MISCREG_HPMCOUNTER05
@ MISCREG_HPMCOUNTER05
Definition: misc.hh:79
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::RiscvISA::MISCREG_HPMCOUNTER28
@ MISCREG_HPMCOUNTER28
Definition: misc.hh:102
gem5::RiscvISA::MISCREG_HPMCOUNTER20
@ MISCREG_HPMCOUNTER20
Definition: misc.hh:94
gem5::RiscvISA::MISCREG_HPMEVENT03
@ MISCREG_HPMEVENT03
Definition: misc.hh:106
gem5::RiscvISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:363
gem5::RiscvISA::load_reservation_addrs
std::unordered_map< int, Addr > load_reservation_addrs
Definition: isa.cc:511

Generated on Thu Jul 28 2022 13:32:21 for gem5 by doxygen 1.8.17