#include <isa.hh>

Inheritance diagram for gem5::RiscvISA::ISA:

Public Types
using	Params = RiscvISAParams

Public Types inherited from gem5::BaseISA
typedef std::vector< const RegClass * >	RegClasses

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
void	clear () override

PCStateBase *	newPCState (Addr new_inst_addr=0) const override

RegVal	readMiscRegNoEffect (RegIndex idx) const override

RegVal	readMiscReg (RegIndex idx) override

void	setMiscRegNoEffect (RegIndex idx, RegVal val) override

void	setMiscReg (RegIndex idx, RegVal val) override

virtual const std::unordered_map< int, CSRMetadata > &	getCSRDataMap () const

virtual const std::unordered_map< int, RegVal > &	getCSRMaskMap () const

bool	inUserMode () const override

void	copyRegsFrom (ThreadContext *src) override

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

	ISA (const Params &p)

void	handleLockedRead (const RequestPtr &req) override

bool	handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) override

void	handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) override

void	globalClearExclusive () override

void	resetThread () override

RiscvType	rvType () const

bool	getEnableRvv () const

void	clearLoadReservation (ContextID cid)

unsigned	getVecLenInBits ()
	Methods for getting VLEN, VLENB and ELEN values.

unsigned	getVecLenInBytes ()

unsigned	getVecElemLenInBits ()

int64_t	getVectorLengthInBytes () const override
	This function returns the vector length of the Vector Length Agnostic extension of the ISA.

PrivilegeModeSet	getPrivilegeModeSet ()

bool	resumeOnPending ()

bool	enableZcd ()

virtual Addr	getFaultHandlerAddr (RegIndex idx, uint64_t cause, bool intr) const

Addr	rvSext (Addr addr) const

Public Member Functions inherited from gem5::BaseISA
virtual void	takeOverFrom (ThreadContext new_tc, ThreadContext old_tc)

virtual void	setThreadContext (ThreadContext *_tc)

virtual uint64_t	getExecutingAsid () const

const RegClasses &	regClasses () const

const std::string	getIsaName () const

virtual void	handleLockedRead (ExecContext *xc, const RequestPtr &req)

virtual bool	handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask)

virtual void	handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)

virtual void	handleLockedSnoopHit ()

virtual void	handleLockedSnoopHit (ExecContext *xc)

virtual void	globalClearExclusive (ExecContext *xc)

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected.

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbePoints ()
	Register probe points for this object.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index.

virtual void	startup ()
	startup() is the final initialization call before simulation.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters.

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Protected Member Functions
bool	hpmCounterEnabled (int counter) const

Protected Member Functions inherited from gem5::BaseISA
	BaseISA (const SimObjectParams &p, const std::string &name)

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain.

void	signalDrainDone () const
	Signal that an object is drained.

Protected Attributes
RiscvType	_rvType

std::vector< RegVal >	miscRegFile

bool	enableRvv

const int	WARN_FAILURE = 10000

const Addr	INVALID_RESERVATION_ADDR = (Addr)-1

std::unordered_map< int, Addr >	load_reservation_addrs

unsigned	vlen
	Length of each vector register in bits.

unsigned	elen
	Length of each vector element in bits.

PrivilegeModeSet	_privilegeModeSet
	The combination of privilege modes in Privilege Levels section of RISC-V privileged spec.

const bool	_wfiResumeOnPending
	The WFI instruction can halt the execution of a hart.

bool	_enableZcd
	Enable Zcd extensions.

Protected Attributes inherited from gem5::BaseISA
ThreadContext *	tc = nullptr

RegClasses	_regClasses

std::string	isaName

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Detailed Description

Definition at line 73 of file isa.hh.

Member Typedef Documentation

◆ Params

using gem5::RiscvISA::ISA::Params = RiscvISAParams

Definition at line 120 of file isa.hh.

Constructor & Destructor Documentation

◆ ISA()

gem5::RiscvISA::ISA::ISA ( const Params & p )

Definition at line 261 of file isa.cc.

References gem5::BaseISA::_regClasses, gem5::ArmISA::ccRegClass, clear(), fatal_if, gem5::X86ISA::floatRegClass, inform, gem5::ArmISA::intRegClass, gem5::ArmISA::matRegClass, gem5::ArmISA::miscRegClass, miscRegFile, gem5::RiscvISA::NUM_PHYS_MISCREGS, gem5::RiscvISA::p, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, and gem5::RiscvISA::vecRegClass.

Member Function Documentation

◆ clear()

void gem5::RiscvISA::ISA::clear ( )

overridevirtual

◆ clearLoadReservation()

void gem5::RiscvISA::ISA::clearLoadReservation ( ContextID cid )

inline

Definition at line 175 of file isa.hh.

References INVALID_RESERVATION_ADDR, and load_reservation_addrs.

Referenced by gem5::RiscvISA::RiscvFault::invoke().

◆ copyRegsFrom()

void gem5::RiscvISA::ISA::copyRegsFrom ( ThreadContext * src )

overridevirtual

Implements gem5::BaseISA.

Definition at line 293 of file isa.cc.

References gem5::X86ISA::floatRegClass, gem5::ThreadContext::getReg(), gem5::RiscvISA::i, gem5::ArmISA::intRegClass, gem5::RiscvISA::NUM_PHYS_MISCREGS, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::ThreadContext::setMiscRegNoEffect(), gem5::ThreadContext::setReg(), gem5::BaseISA::tc, and gem5::RiscvISA::vecRegClass.

◆ enableZcd()

bool gem5::RiscvISA::ISA::enableZcd ( )

inline

Definition at line 192 of file isa.hh.

References _enableZcd.

Referenced by gem5::RiscvISA::Decoder::Decoder().

◆ getCSRDataMap()

virtual const std::unordered_map< int, CSRMetadata > & gem5::RiscvISA::ISA::getCSRDataMap ( ) const

inlinevirtual

Definition at line 141 of file isa.hh.

References gem5::RiscvISA::CSRData.

◆ getCSRMaskMap()

virtual const std::unordered_map< int, RegVal > & gem5::RiscvISA::ISA::getCSRMaskMap ( ) const

inlinevirtual

Definition at line 146 of file isa.hh.

References _privilegeModeSet, _rvType, and gem5::RiscvISA::CSRMasks.

◆ getEnableRvv()

bool gem5::RiscvISA::ISA::getEnableRvv ( ) const

inline

Definition at line 172 of file isa.hh.

References enableRvv.

Referenced by clear(), and setMiscReg().

◆ getFaultHandlerAddr()

Addr gem5::RiscvISA::ISA::getFaultHandlerAddr	(	RegIndex	idx,
		uint64_t	cause,
		bool	intr
	)		const

virtual

Definition at line 1010 of file isa.cc.

References gem5::X86ISA::addr, gem5::bits(), gem5::mbits(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::BaseISA::tc, and gem5::PowerISA::vec.

◆ getPrivilegeModeSet()

PrivilegeModeSet gem5::RiscvISA::ISA::getPrivilegeModeSet ( )

inline

Definition at line 188 of file isa.hh.

References _privilegeModeSet.

Referenced by clear(), readMiscReg(), and setMiscReg().

◆ getVecElemLenInBits()

unsigned gem5::RiscvISA::ISA::getVecElemLenInBits ( )

inline

Definition at line 184 of file isa.hh.

References elen.

Referenced by gem5::RiscvISA::Decoder::Decoder().

◆ getVecLenInBits()

unsigned gem5::RiscvISA::ISA::getVecLenInBits ( )

inline

Methods for getting VLEN, VLENB and ELEN values.

Definition at line 182 of file isa.hh.

References vlen.

Referenced by gem5::RiscvISA::Decoder::Decoder().

◆ getVecLenInBytes()

unsigned gem5::RiscvISA::ISA::getVecLenInBytes ( )

inline

Definition at line 183 of file isa.hh.

References vlen.

Referenced by readMiscReg().

◆ getVectorLengthInBytes()

int64_t gem5::RiscvISA::ISA::getVectorLengthInBytes ( ) const

inlineoverridevirtual

This function returns the vector length of the Vector Length Agnostic extension of the ISA.

For ARM ISA, this function returns the SVE/SVE2 vector length. For RISC-V ISA, this function returns the RVV vector length. For other ISAs, this function returns -1.

Reimplemented from gem5::BaseISA.

Definition at line 186 of file isa.hh.

References vlen.

◆ globalClearExclusive()

void gem5::RiscvISA::ISA::globalClearExclusive ( )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 996 of file isa.cc.

References gem5::ThreadContext::contextId(), gem5::ThreadContext::getCpuPtr(), INVALID_RESERVATION_ADDR, load_reservation_addrs, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), and gem5::BaseCPU::wakeup().

◆ handleLockedRead()

void gem5::RiscvISA::ISA::handleLockedRead ( const RequestPtr & req )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 938 of file isa.cc.

References gem5::ThreadContext::contextId(), DPRINTF, load_reservation_addrs, and gem5::BaseISA::tc.

◆ handleLockedSnoop()

void gem5::RiscvISA::ISA::handleLockedSnoop	(	PacketPtr	pkt,
		Addr	cacheBlockMask
	)

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 924 of file isa.cc.

References gem5::ThreadContext::contextId(), DPRINTF, gem5::Packet::getAddr(), INVALID_RESERVATION_ADDR, load_reservation_addrs, and gem5::BaseISA::tc.

◆ handleLockedWrite()

bool gem5::RiscvISA::ISA::handleLockedWrite	(	const RequestPtr &	req,
		Addr	cacheBlockMask
	)

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 948 of file isa.cc.

References gem5::ThreadContext::contextId(), gem5::curTick(), DPRINTF, INVALID_RESERVATION_ADDR, load_reservation_addrs, gem5::ThreadContext::readStCondFailures(), gem5::ThreadContext::setStCondFailures(), gem5::BaseISA::tc, warn, and WARN_FAILURE.

◆ hpmCounterEnabled()

bool gem5::RiscvISA::ISA::hpmCounterEnabled ( int counter ) const

protected

Definition at line 384 of file isa.cc.

References gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_CYCLEH, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, miscRegFile, panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, gem5::RiscvISA::PRV_U, and readMiscRegNoEffect().

Referenced by readMiscReg().

◆ inUserMode()

bool gem5::RiscvISA::ISA::inUserMode ( ) const

overridevirtual

Implements gem5::BaseISA.

Definition at line 287 of file isa.cc.

References gem5::RiscvISA::MISCREG_PRV, miscRegFile, and gem5::RiscvISA::PRV_U.

◆ newPCState()

PCStateBase * gem5::RiscvISA::ISA::newPCState ( Addr new_inst_addr = 0 ) const

inlineoverridevirtual

Implements gem5::BaseISA.

Definition at line 125 of file isa.hh.

References _rvType, and rvSext().

◆ readMiscReg()

RegVal gem5::RiscvISA::ISA::readMiscReg ( RegIndex idx )

overridevirtual

Implements gem5::BaseISA.

Definition at line 423 of file isa.cc.

Referenced by readMiscReg(), and setMiscReg().

◆ readMiscRegNoEffect()

RegVal gem5::RiscvISA::ISA::readMiscRegNoEffect ( RegIndex idx ) const

overridevirtual

Implements gem5::BaseISA.

Definition at line 413 of file isa.cc.

References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_PHYS_MISCREGS, and panic_if.

Referenced by hpmCounterEnabled(), readMiscReg(), and setMiscReg().

◆ resetThread()

void gem5::RiscvISA::ISA::resetThread ( )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 1004 of file isa.cc.

References gem5::RiscvISA::Reset::invoke(), and gem5::BaseISA::tc.

◆ resumeOnPending()

bool gem5::RiscvISA::ISA::resumeOnPending ( )

inline

Definition at line 190 of file isa.hh.

References _wfiResumeOnPending.

◆ rvSext()

Addr gem5::RiscvISA::ISA::rvSext ( Addr addr ) const

inline

Definition at line 197 of file isa.hh.

References _rvType, gem5::X86ISA::addr, and gem5::RiscvISA::RV32.

Referenced by newPCState().

◆ rvType()

RiscvType gem5::RiscvISA::ISA::rvType ( ) const

inline

Definition at line 170 of file isa.hh.

References _rvType.

Referenced by gem5::RiscvISA::TLB::getValidAddr(), readMiscReg(), and setMiscReg().

◆ serialize()

void gem5::RiscvISA::ISA::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Reimplemented from gem5::BaseISA.

Definition at line 908 of file isa.cc.

References DPRINTF, miscRegFile, gem5::BaseISA::serialize(), and SERIALIZE_CONTAINER.

◆ setMiscReg()

void gem5::RiscvISA::ISA::setMiscReg	(	RegIndex	idx,
		RegVal	val
	)

overridevirtual

Implements gem5::BaseISA.

Definition at line 651 of file isa.cc.

Referenced by setMiscReg().

◆ setMiscRegNoEffect()

void gem5::RiscvISA::ISA::setMiscRegNoEffect	(	RegIndex	idx,
		RegVal	val
	)

overridevirtual

Implements gem5::BaseISA.

Definition at line 641 of file isa.cc.

References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_PHYS_MISCREGS, panic_if, and gem5::X86ISA::val.

Referenced by readMiscReg(), and setMiscReg().

◆ unserialize()

void gem5::RiscvISA::ISA::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 917 of file isa.cc.

References DPRINTF, miscRegFile, and UNSERIALIZE_CONTAINER.

Member Data Documentation

◆ _enableZcd

bool gem5::RiscvISA::ISA::_enableZcd

protected

Enable Zcd extensions.

Set the option to false implies the Zcmp and Zcmt is enable as c.fsdsp is overlap with them. Refs: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc

Definition at line 117 of file isa.hh.

Referenced by enableZcd().

◆ _privilegeModeSet

PrivilegeModeSet gem5::RiscvISA::ISA::_privilegeModeSet

protected

The combination of privilege modes in Privilege Levels section of RISC-V privileged spec.

Definition at line 100 of file isa.hh.

Referenced by getCSRMaskMap(), and getPrivilegeModeSet().

◆ _rvType

RiscvType gem5::RiscvISA::ISA::_rvType

protected

Definition at line 76 of file isa.hh.

Referenced by clear(), getCSRMaskMap(), newPCState(), readMiscReg(), rvSext(), rvType(), and setMiscReg().

◆ _wfiResumeOnPending

const bool gem5::RiscvISA::ISA::_wfiResumeOnPending

protected

The WFI instruction can halt the execution of a hart.

If this variable is set true, the execution resumes if an interrupt becomes pending. If this variable is set to false, the execution only resumes if an locally enabled interrupt becomes pending.

Definition at line 109 of file isa.hh.

Referenced by resumeOnPending().

◆ elen

unsigned gem5::RiscvISA::ISA::elen

protected

Length of each vector element in bits.

ELEN in Ch. 2 of RISC-V vector spec

Definition at line 95 of file isa.hh.

Referenced by getVecElemLenInBits().

◆ enableRvv

bool gem5::RiscvISA::ISA::enableRvv

protected

Definition at line 78 of file isa.hh.

Referenced by getEnableRvv().

◆ INVALID_RESERVATION_ADDR

const Addr gem5::RiscvISA::ISA::INVALID_RESERVATION_ADDR = (Addr)-1

protected

Definition at line 84 of file isa.hh.

Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedSnoop(), and handleLockedWrite().

◆ load_reservation_addrs

std::unordered_map<int, Addr> gem5::RiscvISA::ISA::load_reservation_addrs

protected

Definition at line 85 of file isa.hh.

Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedRead(), handleLockedSnoop(), and handleLockedWrite().

◆ miscRegFile

std::vector<RegVal> gem5::RiscvISA::ISA::miscRegFile

protected

Definition at line 77 of file isa.hh.

Referenced by clear(), hpmCounterEnabled(), inUserMode(), ISA(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().

◆ vlen

unsigned gem5::RiscvISA::ISA::vlen

protected

Length of each vector register in bits.

VLEN in Ch. 2 of RISC-V vector spec

Definition at line 90 of file isa.hh.

Referenced by getVecLenInBits(), getVecLenInBytes(), and getVectorLengthInBytes().

◆ WARN_FAILURE

const int gem5::RiscvISA::ISA::WARN_FAILURE = 10000

protected

Definition at line 83 of file isa.hh.

Referenced by handleLockedWrite().

The documentation for this class was generated from the following files:

arch/riscv/isa.hh
arch/riscv/isa.cc

Public Types

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Params

Constructor & Destructor Documentation

◆ ISA()

Member Function Documentation

◆ clear()

◆ clearLoadReservation()

◆ copyRegsFrom()

◆ enableZcd()

◆ getCSRDataMap()

◆ getCSRMaskMap()

◆ getEnableRvv()

◆ getFaultHandlerAddr()

◆ getPrivilegeModeSet()

◆ getVecElemLenInBits()

◆ getVecLenInBits()

◆ getVecLenInBytes()

◆ getVectorLengthInBytes()

◆ globalClearExclusive()

◆ handleLockedRead()

◆ handleLockedSnoop()

◆ handleLockedWrite()

◆ hpmCounterEnabled()

◆ inUserMode()

◆ newPCState()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ resetThread()

◆ resumeOnPending()

◆ rvSext()

◆ rvType()

◆ serialize()

◆ setMiscReg()

◆ setMiscRegNoEffect()

◆ unserialize()

Member Data Documentation

◆ _enableZcd

◆ _privilegeModeSet

◆ _rvType

◆ _wfiResumeOnPending

◆ elen

◆ enableRvv

◆ INVALID_RESERVATION_ADDR

◆ load_reservation_addrs

◆ miscRegFile

◆ vlen

◆ WARN_FAILURE