gem5 v24.1.0.1
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#include <isa.hh>
Public Types | |
using | Params = RiscvISAParams |
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typedef std::vector< const RegClass * > | RegClasses |
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typedef SimObjectParams | Params |
Public Member Functions | |
void | clear () override |
PCStateBase * | newPCState (Addr new_inst_addr=0) const override |
RegVal | readMiscRegNoEffect (RegIndex idx) const override |
RegVal | readMiscReg (RegIndex idx) override |
void | setMiscRegNoEffect (RegIndex idx, RegVal val) override |
void | setMiscReg (RegIndex idx, RegVal val) override |
virtual const std::unordered_map< int, CSRMetadata > & | getCSRDataMap () const |
virtual const std::unordered_map< int, RegVal > & | getCSRMaskMap () const |
bool | inUserMode () const override |
void | copyRegsFrom (ThreadContext *src) override |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
ISA (const Params &p) | |
void | handleLockedRead (const RequestPtr &req) override |
bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) override |
void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) override |
void | globalClearExclusive () override |
void | resetThread () override |
RiscvType | rvType () const |
bool | getEnableRvv () const |
void | clearLoadReservation (ContextID cid) |
unsigned | getVecLenInBits () |
Methods for getting VLEN, VLENB and ELEN values. | |
unsigned | getVecLenInBytes () |
unsigned | getVecElemLenInBits () |
int64_t | getVectorLengthInBytes () const override |
This function returns the vector length of the Vector Length Agnostic extension of the ISA. | |
PrivilegeModeSet | getPrivilegeModeSet () |
bool | resumeOnPending () |
bool | enableZcd () |
virtual Addr | getFaultHandlerAddr (RegIndex idx, uint64_t cause, bool intr) const |
Addr | rvSext (Addr addr) const |
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virtual void | takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) |
virtual void | setThreadContext (ThreadContext *_tc) |
virtual uint64_t | getExecutingAsid () const |
const RegClasses & | regClasses () const |
const std::string | getIsaName () const |
virtual void | handleLockedRead (ExecContext *xc, const RequestPtr &req) |
virtual bool | handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoopHit () |
virtual void | handleLockedSnoopHit (ExecContext *xc) |
virtual void | globalClearExclusive (ExecContext *xc) |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. | |
virtual void | regProbePoints () |
Register probe points for this object. | |
virtual void | regProbeListeners () |
Register probe listeners for this object. | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. | |
virtual void | startup () |
startup() is the final initialization call before simulation. | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. | |
virtual void | notifyFork () |
Notify a child process of a fork. | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. | |
virtual void | resetStats () |
Callback to reset stats. | |
virtual void | preDumpStats () |
Callback before stats are dumped. | |
void | addStat (statistics::Info *info) |
Register a stat with this group. | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
Protected Member Functions | |
bool | hpmCounterEnabled (int counter) const |
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BaseISA (const SimObjectParams &p, const std::string &name) | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. | |
void | signalDrainDone () const |
Signal that an object is drained. | |
Protected Attributes | |
RiscvType | _rvType |
std::vector< RegVal > | miscRegFile |
bool | enableRvv |
const int | WARN_FAILURE = 10000 |
const Addr | INVALID_RESERVATION_ADDR = (Addr)-1 |
std::unordered_map< int, Addr > | load_reservation_addrs |
unsigned | vlen |
Length of each vector register in bits. | |
unsigned | elen |
Length of each vector element in bits. | |
PrivilegeModeSet | _privilegeModeSet |
The combination of privilege modes in Privilege Levels section of RISC-V privileged spec. | |
const bool | _wfiResumeOnPending |
The WFI instruction can halt the execution of a hart. | |
bool | _enableZcd |
Enable Zcd extensions. | |
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ThreadContext * | tc = nullptr |
RegClasses | _regClasses |
std::string | isaName |
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const SimObjectParams & | _params |
Cached copy of the object parameters. | |
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EventQueue * | eventq |
A pointer to this object's event queue. | |
Additional Inherited Members | |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
using gem5::RiscvISA::ISA::Params = RiscvISAParams |
gem5::RiscvISA::ISA::ISA | ( | const Params & | p | ) |
Definition at line 261 of file isa.cc.
References gem5::BaseISA::_regClasses, gem5::ArmISA::ccRegClass, clear(), fatal_if, gem5::X86ISA::floatRegClass, inform, gem5::ArmISA::intRegClass, gem5::ArmISA::matRegClass, gem5::ArmISA::miscRegClass, miscRegFile, gem5::RiscvISA::NUM_PHYS_MISCREGS, gem5::RiscvISA::p, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, and gem5::RiscvISA::vecRegClass.
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Reimplemented from gem5::BaseISA.
Definition at line 318 of file isa.cc.
References _rvType, getEnableRvv(), getPrivilegeModeSet(), gem5::RiscvISA::INITIAL, gem5::RiscvISA::MISCREG_ARCHID, gem5::RiscvISA::MISCREG_IMPID, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_NMIE, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::RiscvISA::MISCREG_VENDORID, miscRegFile, gem5::Named::name(), panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, and gem5::ArmISA::status.
Referenced by ISA().
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Definition at line 175 of file isa.hh.
References INVALID_RESERVATION_ADDR, and load_reservation_addrs.
Referenced by gem5::RiscvISA::RiscvFault::invoke().
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Implements gem5::BaseISA.
Definition at line 293 of file isa.cc.
References gem5::X86ISA::floatRegClass, gem5::ThreadContext::getReg(), gem5::RiscvISA::i, gem5::ArmISA::intRegClass, gem5::RiscvISA::NUM_PHYS_MISCREGS, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::ThreadContext::setMiscRegNoEffect(), gem5::ThreadContext::setReg(), gem5::BaseISA::tc, and gem5::RiscvISA::vecRegClass.
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Definition at line 192 of file isa.hh.
References _enableZcd.
Referenced by gem5::RiscvISA::Decoder::Decoder().
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Definition at line 141 of file isa.hh.
References gem5::RiscvISA::CSRData.
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Definition at line 146 of file isa.hh.
References _privilegeModeSet, _rvType, and gem5::RiscvISA::CSRMasks.
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Definition at line 172 of file isa.hh.
References enableRvv.
Referenced by clear(), and setMiscReg().
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Definition at line 1010 of file isa.cc.
References gem5::X86ISA::addr, gem5::bits(), gem5::mbits(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::BaseISA::tc, and gem5::PowerISA::vec.
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Definition at line 188 of file isa.hh.
References _privilegeModeSet.
Referenced by clear(), readMiscReg(), and setMiscReg().
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Definition at line 184 of file isa.hh.
References elen.
Referenced by gem5::RiscvISA::Decoder::Decoder().
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Methods for getting VLEN, VLENB and ELEN values.
Definition at line 182 of file isa.hh.
References vlen.
Referenced by gem5::RiscvISA::Decoder::Decoder().
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This function returns the vector length of the Vector Length Agnostic extension of the ISA.
For ARM ISA, this function returns the SVE/SVE2 vector length. For RISC-V ISA, this function returns the RVV vector length. For other ISAs, this function returns -1.
Reimplemented from gem5::BaseISA.
Definition at line 186 of file isa.hh.
References vlen.
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 996 of file isa.cc.
References gem5::ThreadContext::contextId(), gem5::ThreadContext::getCpuPtr(), INVALID_RESERVATION_ADDR, load_reservation_addrs, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), and gem5::BaseCPU::wakeup().
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Reimplemented from gem5::BaseISA.
Definition at line 938 of file isa.cc.
References gem5::ThreadContext::contextId(), DPRINTF, load_reservation_addrs, and gem5::BaseISA::tc.
Reimplemented from gem5::BaseISA.
Definition at line 924 of file isa.cc.
References gem5::ThreadContext::contextId(), DPRINTF, gem5::Packet::getAddr(), INVALID_RESERVATION_ADDR, load_reservation_addrs, and gem5::BaseISA::tc.
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Reimplemented from gem5::BaseISA.
Definition at line 948 of file isa.cc.
References gem5::ThreadContext::contextId(), gem5::curTick(), DPRINTF, INVALID_RESERVATION_ADDR, load_reservation_addrs, gem5::ThreadContext::readStCondFailures(), gem5::ThreadContext::setStCondFailures(), gem5::BaseISA::tc, warn, and WARN_FAILURE.
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Definition at line 384 of file isa.cc.
References gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_CYCLEH, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, miscRegFile, panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, gem5::RiscvISA::PRV_U, and readMiscRegNoEffect().
Referenced by readMiscReg().
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Implements gem5::BaseISA.
Definition at line 287 of file isa.cc.
References gem5::RiscvISA::MISCREG_PRV, miscRegFile, and gem5::RiscvISA::PRV_U.
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Implements gem5::BaseISA.
Definition at line 423 of file isa.cc.
References _rvType, gem5::PCStateBase::as(), gem5::ThreadContext::contextId(), gem5::Clocked::curCycle(), DPRINTF, gem5::RiscvISA::FFLAGS_MASK, gem5::RiscvISA::FRM_OFFSET, gem5::ThreadContext::getCpuPtr(), gem5::BaseCPU::getInterruptController(), getPrivilegeModeSet(), getVecLenInBytes(), hpmCounterEnabled(), gem5::mbits(), gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_CYCLEH, gem5::RiscvISA::MISCREG_FCSR, gem5::RiscvISA::MISCREG_FFLAGS, gem5::RiscvISA::MISCREG_FFLAGS_EXE, gem5::RiscvISA::MISCREG_FRM, gem5::RiscvISA::MISCREG_HARTID, gem5::RiscvISA::MISCREG_HPMCOUNTER03, gem5::RiscvISA::MISCREG_HPMCOUNTER03H, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_HPMCOUNTER31H, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_INSTRET, gem5::RiscvISA::MISCREG_INSTRETH, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MEPC, gem5::RiscvISA::MISCREG_SEPC, gem5::RiscvISA::MISCREG_SIE, gem5::RiscvISA::MISCREG_SIP, gem5::RiscvISA::MISCREG_SSTATUS, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TIME, gem5::RiscvISA::MISCREG_TIMEH, gem5::RiscvISA::MISCREG_UIE, gem5::RiscvISA::MISCREG_UIP, gem5::RiscvISA::MISCREG_USTATUS, gem5::RiscvISA::MISCREG_VCSR, gem5::RiscvISA::MISCREG_VL, gem5::RiscvISA::MISCREG_VLENB, gem5::RiscvISA::MISCREG_VTYPE, gem5::RiscvISA::MISCREG_VXRM, gem5::RiscvISA::MISCREG_VXSAT, gem5::Named::name(), panic, gem5::ThreadContext::pcState(), gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, gem5::RiscvISA::PRV_U, readMiscReg(), readMiscRegNoEffect(), gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, rvType(), setMiscRegNoEffect(), gem5::RiscvISA::SI_MASK, gem5::RiscvISA::SSTATUS_MASKS, gem5::ArmISA::status, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), gem5::BaseCPU::totalInsts(), gem5::RiscvISA::UI_MASK, gem5::RiscvISA::USTATUS_MASKS, gem5::X86ISA::val, gem5::RiscvISA::PCState::vl(), gem5::RiscvISA::PCState::vtype(), and warn.
Referenced by readMiscReg(), and setMiscReg().
Implements gem5::BaseISA.
Definition at line 413 of file isa.cc.
References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_PHYS_MISCREGS, and panic_if.
Referenced by hpmCounterEnabled(), readMiscReg(), and setMiscReg().
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Reimplemented from gem5::BaseISA.
Definition at line 1004 of file isa.cc.
References gem5::RiscvISA::Reset::invoke(), and gem5::BaseISA::tc.
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Definition at line 190 of file isa.hh.
References _wfiResumeOnPending.
Definition at line 197 of file isa.hh.
References _rvType, gem5::X86ISA::addr, and gem5::RiscvISA::RV32.
Referenced by newPCState().
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Definition at line 170 of file isa.hh.
References _rvType.
Referenced by gem5::RiscvISA::TLB::getValidAddr(), readMiscReg(), and setMiscReg().
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Serialize an object.
Output an object's state into the current checkpoint section.
cp | Checkpoint state |
Reimplemented from gem5::BaseISA.
Definition at line 908 of file isa.cc.
References DPRINTF, miscRegFile, gem5::BaseISA::serialize(), and SERIALIZE_CONTAINER.
Implements gem5::BaseISA.
Definition at line 651 of file isa.cc.
References _rvType, gem5::PCStateBase::as(), gem5::bits(), gem5::RiscvISA::FFLAGS_MASK, gem5::RiscvISA::FRM_MASK, gem5::ThreadContext::getCpuPtr(), getEnableRvv(), gem5::BaseCPU::getInterruptController(), gem5::ThreadContext::getMMUPtr(), getPrivilegeModeSet(), gem5::RiscvISA::i, gem5::RiscvISA::mask, gem5::RiscvISA::MI_MASK, gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_FCSR, gem5::RiscvISA::MISCREG_FFLAGS, gem5::RiscvISA::MISCREG_FFLAGS_EXE, gem5::RiscvISA::MISCREG_FRM, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_PMPADDR00, gem5::RiscvISA::MISCREG_PMPADDR15, gem5::RiscvISA::MISCREG_PMPCFG0, gem5::RiscvISA::MISCREG_PMPCFG1, gem5::RiscvISA::MISCREG_PMPCFG2, gem5::RiscvISA::MISCREG_PMPCFG3, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SATP, gem5::RiscvISA::MISCREG_SENVCFG, gem5::RiscvISA::MISCREG_SIE, gem5::RiscvISA::MISCREG_SIP, gem5::RiscvISA::MISCREG_SSTATUS, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::RiscvISA::MISCREG_UIE, gem5::RiscvISA::MISCREG_UIP, gem5::RiscvISA::MISCREG_USTATUS, gem5::RiscvISA::MISCREG_VCSR, gem5::RiscvISA::MISCREG_VXRM, gem5::RiscvISA::MISCREG_VXSAT, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::MSTATUS_MASKS, gem5::Named::name(), panic, gem5::ThreadContext::pcState(), gem5::RiscvISA::PRV_M, readMiscReg(), readMiscRegNoEffect(), gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, rvType(), setMiscReg(), setMiscRegNoEffect(), gem5::RiscvISA::SI_MASK, gem5::RiscvISA::SSTATUS_MASKS, gem5::RiscvISA::STATUS_SXL_MASK, gem5::RiscvISA::STATUS_UXL_MASK, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), gem5::RiscvISA::UI_MASK, gem5::RiscvISA::USTATUS_MASKS, gem5::X86ISA::val, and warn.
Referenced by setMiscReg().
Implements gem5::BaseISA.
Definition at line 641 of file isa.cc.
References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_PHYS_MISCREGS, panic_if, and gem5::X86ISA::val.
Referenced by readMiscReg(), and setMiscReg().
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Unserialize an object.
Read an object's state from the current checkpoint section.
cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 917 of file isa.cc.
References DPRINTF, miscRegFile, and UNSERIALIZE_CONTAINER.
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Enable Zcd extensions.
Set the option to false implies the Zcmp and Zcmt is enable as c.fsdsp is overlap with them. Refs: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc
Definition at line 117 of file isa.hh.
Referenced by enableZcd().
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The combination of privilege modes in Privilege Levels section of RISC-V privileged spec.
Definition at line 100 of file isa.hh.
Referenced by getCSRMaskMap(), and getPrivilegeModeSet().
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Definition at line 76 of file isa.hh.
Referenced by clear(), getCSRMaskMap(), newPCState(), readMiscReg(), rvSext(), rvType(), and setMiscReg().
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The WFI instruction can halt the execution of a hart.
If this variable is set true, the execution resumes if an interrupt becomes pending. If this variable is set to false, the execution only resumes if an locally enabled interrupt becomes pending.
Definition at line 109 of file isa.hh.
Referenced by resumeOnPending().
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Length of each vector element in bits.
ELEN in Ch. 2 of RISC-V vector spec
Definition at line 95 of file isa.hh.
Referenced by getVecElemLenInBits().
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Definition at line 78 of file isa.hh.
Referenced by getEnableRvv().
Definition at line 84 of file isa.hh.
Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedSnoop(), and handleLockedWrite().
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Definition at line 85 of file isa.hh.
Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedRead(), handleLockedSnoop(), and handleLockedWrite().
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Definition at line 77 of file isa.hh.
Referenced by clear(), hpmCounterEnabled(), inUserMode(), ISA(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Length of each vector register in bits.
VLEN in Ch. 2 of RISC-V vector spec
Definition at line 90 of file isa.hh.
Referenced by getVecLenInBits(), getVecLenInBytes(), and getVectorLengthInBytes().
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Definition at line 83 of file isa.hh.
Referenced by handleLockedWrite().