gem5 v24.0.0.0
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remote_gdb.cc
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1/*
2 * Copyright 2015 LabWare
3 * Copyright 2014 Google, Inc.
4 * Copyright (c) 2010 ARM Limited
5 * Copyright (c) 2021 IBM Corporation
6 * All rights reserved
7 *
8 * The license below extends only to copyright in the software and shall
9 * not be construed as granting a license to any other intellectual
10 * property including but not limited to intellectual property relating
11 * to a hardware implementation of the functionality of the software
12 * licensed hereunder. You may use the software subject to the license
13 * terms below provided that you ensure that this notice is replicated
14 * unmodified and in its entirety in all distributions of the software,
15 * modified or unmodified, in source code or in binary form.
16 *
17 * Copyright (c) 2002-2005 The Regents of The University of Michigan
18 * All rights reserved.
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are
22 * met: redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer;
24 * redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution;
27 * neither the name of the copyright holders nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 */
43
44/*
45 * Copyright (c) 1990, 1993 The Regents of the University of California
46 * All rights reserved
47 *
48 * This software was developed by the Computer Systems Engineering group
49 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
50 * contributed to Berkeley.
51 *
52 * All advertising materials mentioning features or use of this software
53 * must display the following acknowledgement:
54 * This product includes software developed by the University of
55 * California, Lawrence Berkeley Laboratories.
56 *
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
59 * are met:
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
65 * 3. All advertising materials mentioning features or use of this software
66 * must display the following acknowledgement:
67 * This product includes software developed by the University of
68 * California, Berkeley and its contributors.
69 * 4. Neither the name of the University nor the names of its contributors
70 * may be used to endorse or promote products derived from this software
71 * without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
83 * SUCH DAMAGE.
84 *
85 * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
86 */
87
88/*-
89 * Copyright (c) 2001 The NetBSD Foundation, Inc.
90 * All rights reserved.
91 *
92 * This code is derived from software contributed to The NetBSD Foundation
93 * by Jason R. Thorpe.
94 *
95 * Redistribution and use in source and binary forms, with or without
96 * modification, are permitted provided that the following conditions
97 * are met:
98 * 1. Redistributions of source code must retain the above copyright
99 * notice, this list of conditions and the following disclaimer.
100 * 2. Redistributions in binary form must reproduce the above copyright
101 * notice, this list of conditions and the following disclaimer in the
102 * documentation and/or other materials provided with the distribution.
103 * 3. All advertising materials mentioning features or use of this software
104 * must display the following acknowledgement:
105 * This product includes software developed by the NetBSD
106 * Foundation, Inc. and its contributors.
107 * 4. Neither the name of The NetBSD Foundation nor the names of its
108 * contributors may be used to endorse or promote products derived
109 * from this software without specific prior written permission.
110 *
111 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
112 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
113 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
114 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
115 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
116 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
117 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
118 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
119 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
120 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
121 * POSSIBILITY OF SUCH DAMAGE.
122 */
123
124/*
125 * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
126 *
127 * Taken from NetBSD
128 *
129 * "Stub" to allow remote cpu to debug over a serial line using gdb.
130 */
131
132
134
135#include <sys/signal.h>
136#include <unistd.h>
137
138#include <string>
139
140#include "arch/power/gdb-xml/gdb_xml_power64_core.hh"
141#include "arch/power/gdb-xml/gdb_xml_power_core.hh"
142#include "arch/power/gdb-xml/gdb_xml_power_fpu.hh"
143#include "arch/power/gdb-xml/gdb_xml_powerpc_32.hh"
144#include "arch/power/gdb-xml/gdb_xml_powerpc_64.hh"
145#include "arch/power/pcstate.hh"
147#include "cpu/thread_state.hh"
148#include "debug/GDBAcc.hh"
149#include "debug/GDBMisc.hh"
150#include "mem/page_table.hh"
151#include "sim/byteswap.hh"
152
153namespace gem5
154{
155
156using namespace PowerISA;
157
158RemoteGDB::RemoteGDB(System *_system, ListenSocketConfig _listen_config)
159 : BaseRemoteGDB(_system, _listen_config),
160 regCache32(this), regCache64(this)
161{
162}
163
164/*
165 * Determine if the mapping at va..(va+len) is valid.
166 */
167bool
168RemoteGDB::acc(Addr va, size_t len)
169{
170 // Check to make sure the first byte is mapped into the processes address
171 // space. At the time of this writing, the acc() check is used when
172 // processing the MemR/MemW packets before actually asking the translating
173 // port proxy to read/writeBlob. I (bgs) am not convinced the first byte
174 // check is enough.
175 panic_if(FullSystem, "acc not implemented for POWER FS!");
176 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
177}
178
179void
180RemoteGDB::PowerGdbRegCache::getRegs(ThreadContext *context)
181{
182 DPRINTF(GDBAcc, "getRegs in remotegdb \n");
183
184 Msr msr = context->getReg(int_reg::Msr);
185 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
186
187 // Default order on 32-bit PowerPC:
188 // R0-R31 (32-bit each), F0-F31 (64-bit IEEE754 double),
189 // PC, MSR, CR, LR, CTR, XER, FPSCR (32-bit each)
190
191 for (int i = 0; i < int_reg::NumArchRegs; i++) {
193 r.gpr[i] = htog((uint32_t)context->getReg(reg), order);
194 }
195
196 for (int i = 0; i < float_reg::NumArchRegs; i++)
197 r.fpr[i] = context->getReg(floatRegClass[i]);
198
199 r.pc = htog((uint32_t)context->pcState().instAddr(), order);
200 r.msr = 0; // MSR is privileged, hence not exposed here
201 r.cr = htog((uint32_t)context->getReg(int_reg::Cr), order);
202 r.lr = htog((uint32_t)context->getReg(int_reg::Lr), order);
203 r.ctr = htog((uint32_t)context->getReg(int_reg::Ctr), order);
204 r.xer = htog((uint32_t)context->getReg(int_reg::Xer), order);
205 r.fpscr = htog((uint32_t)context->getReg(int_reg::Fpscr), order);
206}
207
208void
209RemoteGDB::PowerGdbRegCache::setRegs(ThreadContext *context) const
210{
211 DPRINTF(GDBAcc, "setRegs in remotegdb \n");
212
213 Msr msr = context->getReg(int_reg::Msr);
214 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
215
216 for (int i = 0; i < int_reg::NumArchRegs; i++)
217 context->setReg(intRegClass[i], gtoh(r.gpr[i], order));
218
219 for (int i = 0; i < float_reg::NumArchRegs; i++)
220 context->setReg(floatRegClass[i], r.fpr[i]);
221
222 auto pc = context->pcState().as<PowerISA::PCState>();
223 pc.byteOrder(order);
224 pc.set(gtoh(r.pc, order));
225 context->pcState(pc);
226 // MSR is privileged, hence not modified here
227 context->setReg(int_reg::Cr, gtoh(r.cr, order));
228 context->setReg(int_reg::Lr, gtoh(r.lr, order));
229 context->setReg(int_reg::Ctr, gtoh(r.ctr, order));
230 context->setReg(int_reg::Xer, gtoh(r.xer, order));
231 context->setReg(int_reg::Fpscr, gtoh(r.fpscr, order));
232}
233
234void
235RemoteGDB::Power64GdbRegCache::getRegs(ThreadContext *context)
236{
237 DPRINTF(GDBAcc, "getRegs in remotegdb \n");
238
239 Msr msr = context->getReg(int_reg::Msr);
240 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
241
242 // Default order on 64-bit PowerPC:
243 // GPRR0-GPRR31 (64-bit each), FPR0-FPR31 (64-bit IEEE754 double),
244 // CIA, MSR, CR, LR, CTR, XER, FPSCR (only CR, XER, FPSCR are 32-bit
245 // each and the rest are 64-bit)
246
247 for (int i = 0; i < int_reg::NumArchRegs; i++)
248 r.gpr[i] = htog(context->getReg(intRegClass[i]), order);
249
250 for (int i = 0; i < float_reg::NumArchRegs; i++)
251 r.fpr[i] = context->getReg(floatRegClass[i]);
252
253 r.pc = htog(context->pcState().instAddr(), order);
254 r.msr = 0; // MSR is privileged, hence not exposed here
255 r.cr = htog((uint32_t)context->getReg(int_reg::Cr), order);
256 r.lr = htog(context->getReg(int_reg::Lr), order);
257 r.ctr = htog(context->getReg(int_reg::Ctr), order);
258 r.xer = htog((uint32_t)context->getReg(int_reg::Xer), order);
259 r.fpscr = htog((uint32_t)context->getReg(int_reg::Fpscr), order);
260}
261
262void
263RemoteGDB::Power64GdbRegCache::setRegs(ThreadContext *context) const
264{
265 DPRINTF(GDBAcc, "setRegs in remotegdb \n");
266
267 Msr msr = context->getReg(int_reg::Msr);
268 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
269
270 for (int i = 0; i < int_reg::NumArchRegs; i++)
271 context->setReg(intRegClass[i], gtoh(r.gpr[i], order));
272
273 for (int i = 0; i < float_reg::NumArchRegs; i++)
274 context->setReg(floatRegClass[i], r.fpr[i]);
275
276 auto pc = context->pcState().as<PowerISA::PCState>();
277 pc.byteOrder(order);
278 pc.set(gtoh(r.pc, order));
279 context->pcState(pc);
280 // MSR is privileged, hence not modified here
281 context->setReg(int_reg::Cr, gtoh(r.cr, order));
282 context->setReg(int_reg::Lr, gtoh(r.lr, order));
283 context->setReg(int_reg::Ctr, gtoh(r.ctr, order));
284 context->setReg(int_reg::Xer, gtoh(r.xer, order));
285 context->setReg(int_reg::Fpscr, gtoh(r.fpscr, order));
286}
287
289RemoteGDB::gdbRegs()
290{
291 Msr msr = context()->getReg(int_reg::Msr);
292 if (msr.sf)
293 return &regCache64;
294 else
295 return &regCache32;
296}
297
298bool
299RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
300{
301#define GDB_XML(x, s) \
302 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
303 Blobs::s ## _len) }
304 static const std::map<std::string, std::string> annexMap32{
305 GDB_XML("target.xml", gdb_xml_powerpc_32),
306 GDB_XML("power-core.xml", gdb_xml_power_core),
307 GDB_XML("power-fpu.xml", gdb_xml_power_fpu)
308 };
309 static const std::map<std::string, std::string> annexMap64{
310 GDB_XML("target.xml", gdb_xml_powerpc_64),
311 GDB_XML("power64-core.xml", gdb_xml_power64_core),
312 GDB_XML("power-fpu.xml", gdb_xml_power_fpu)
313 };
314#undef GDB_XML
315
316 Msr msr = context()->getReg(int_reg::Msr);
317 auto& annexMap = msr.sf ? annexMap64 : annexMap32;
318 auto it = annexMap.find(annex);
319 if (it == annexMap.end())
320 return false;
321 output = it->second;
322 return true;
323}
324
325} // namespace gem5
#define GDB_XML(x, s)
#define DPRINTF(x,...)
Definition trace.hh:210
RemoteGDB(System *_system, ListenSocketConfig _listen_config)
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition remote_gdb.hh:86
Target & as()
Definition pcstate.hh:73
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId &reg) const
virtual void setReg(const RegId &reg, RegVal val)
virtual const PCStateBase & pcState() const =0
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
uint16_t len
Definition helpers.cc:83
Bitfield< 7 > i
Definition misc_types.hh:67
constexpr RegClass intRegClass
Definition int.hh:173
Bitfield< 4 > pc
Bitfield< 5, 3 > reg
Definition types.hh:92
constexpr RegClass floatRegClass
Definition float.hh:143
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
T gtoh(T value, ByteOrder guest_byte_order)
Definition byteswap.hh:194
T htog(T value, ByteOrder guest_byte_order)
Definition byteswap.hh:187
Declarations of a non-full system Page Table.

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