135#include <sys/signal.h>
140#include "arch/power/gdb-xml/gdb_xml_power64_core.hh"
141#include "arch/power/gdb-xml/gdb_xml_power_core.hh"
142#include "arch/power/gdb-xml/gdb_xml_power_fpu.hh"
143#include "arch/power/gdb-xml/gdb_xml_powerpc_32.hh"
144#include "arch/power/gdb-xml/gdb_xml_powerpc_64.hh"
148#include "debug/GDBAcc.hh"
149#include "debug/GDBMisc.hh"
156using namespace PowerISA;
159 : BaseRemoteGDB(_system, _listen_config),
160 regCache32(this), regCache64(this)
168RemoteGDB::acc(Addr va,
size_t len)
175 panic_if(FullSystem,
"acc not implemented for POWER FS!");
176 return context()->getProcessPtr()->pTable->lookup(va) !=
nullptr;
182 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
184 Msr msr = context->
getReg(int_reg::Msr);
185 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
191 for (
int i = 0;
i < int_reg::NumArchRegs;
i++) {
196 for (
int i = 0;
i < float_reg::NumArchRegs;
i++)
201 r.cr =
htog((uint32_t)context->
getReg(int_reg::Cr), order);
202 r.lr =
htog((uint32_t)context->
getReg(int_reg::Lr), order);
203 r.ctr =
htog((uint32_t)context->
getReg(int_reg::Ctr), order);
204 r.xer =
htog((uint32_t)context->
getReg(int_reg::Xer), order);
205 r.fpscr =
htog((uint32_t)context->
getReg(int_reg::Fpscr), order);
211 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
213 Msr msr = context->
getReg(int_reg::Msr);
214 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
216 for (
int i = 0;
i < int_reg::NumArchRegs;
i++)
219 for (
int i = 0;
i < float_reg::NumArchRegs;
i++)
224 pc.set(
gtoh(r.pc, order));
227 context->
setReg(int_reg::Cr,
gtoh(r.cr, order));
228 context->
setReg(int_reg::Lr,
gtoh(r.lr, order));
229 context->
setReg(int_reg::Ctr,
gtoh(r.ctr, order));
230 context->
setReg(int_reg::Xer,
gtoh(r.xer, order));
231 context->
setReg(int_reg::Fpscr,
gtoh(r.fpscr, order));
237 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
239 Msr msr = context->
getReg(int_reg::Msr);
240 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
247 for (
int i = 0;
i < int_reg::NumArchRegs;
i++)
250 for (
int i = 0;
i < float_reg::NumArchRegs;
i++)
255 r.cr =
htog((uint32_t)context->
getReg(int_reg::Cr), order);
256 r.lr =
htog(context->
getReg(int_reg::Lr), order);
257 r.ctr =
htog(context->
getReg(int_reg::Ctr), order);
258 r.xer =
htog((uint32_t)context->
getReg(int_reg::Xer), order);
259 r.fpscr =
htog((uint32_t)context->
getReg(int_reg::Fpscr), order);
265 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
267 Msr msr = context->
getReg(int_reg::Msr);
268 ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
270 for (
int i = 0;
i < int_reg::NumArchRegs;
i++)
273 for (
int i = 0;
i < float_reg::NumArchRegs;
i++)
278 pc.set(
gtoh(r.pc, order));
281 context->
setReg(int_reg::Cr,
gtoh(r.cr, order));
282 context->
setReg(int_reg::Lr,
gtoh(r.lr, order));
283 context->
setReg(int_reg::Ctr,
gtoh(r.ctr, order));
284 context->
setReg(int_reg::Xer,
gtoh(r.xer, order));
285 context->
setReg(int_reg::Fpscr,
gtoh(r.fpscr, order));
291 Msr msr = context()->getReg(int_reg::Msr);
299RemoteGDB::getXferFeaturesRead(
const std::string &annex, std::string &output)
301#define GDB_XML(x, s) \
302 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
304 static const std::map<std::string, std::string> annexMap32{
305 GDB_XML(
"target.xml", gdb_xml_powerpc_32),
306 GDB_XML(
"power-core.xml", gdb_xml_power_core),
307 GDB_XML(
"power-fpu.xml", gdb_xml_power_fpu)
309 static const std::map<std::string, std::string> annexMap64{
310 GDB_XML(
"target.xml", gdb_xml_powerpc_64),
311 GDB_XML(
"power64-core.xml", gdb_xml_power64_core),
312 GDB_XML(
"power-fpu.xml", gdb_xml_power_fpu)
316 Msr msr = context()->getReg(int_reg::Msr);
317 auto& annexMap = msr.sf ? annexMap64 : annexMap32;
318 auto it = annexMap.find(annex);
319 if (it == annexMap.end())
RemoteGDB(System *_system, ListenSocketConfig _listen_config)
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Register ID: describe an architectural register with its class and index.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId ®) const
virtual void setReg(const RegId ®, RegVal val)
virtual const PCStateBase & pcState() const =0
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
constexpr RegClass intRegClass
constexpr RegClass floatRegClass
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
T gtoh(T value, ByteOrder guest_byte_order)
T htog(T value, ByteOrder guest_byte_order)
Declarations of a non-full system Page Table.