gem5  v22.0.0.2
remote_gdb.cc
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1 /*
2  * Copyright 2015 LabWare
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5  * Copyright (c) 2021 IBM Corporation
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43 
44 /*
45  * Copyright (c) 1990, 1993 The Regents of the University of California
46  * All rights reserved
47  *
48  * This software was developed by the Computer Systems Engineering group
49  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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54  * This product includes software developed by the University of
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57  * Redistribution and use in source and binary forms, with or without
58  * modification, are permitted provided that the following conditions
59  * are met:
60  * 1. Redistributions of source code must retain the above copyright
61  * notice, this list of conditions and the following disclaimer.
62  * 2. Redistributions in binary form must reproduce the above copyright
63  * notice, this list of conditions and the following disclaimer in the
64  * documentation and/or other materials provided with the distribution.
65  * 3. All advertising materials mentioning features or use of this software
66  * must display the following acknowledgement:
67  * This product includes software developed by the University of
68  * California, Berkeley and its contributors.
69  * 4. Neither the name of the University nor the names of its contributors
70  * may be used to endorse or promote products derived from this software
71  * without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
74  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
77  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
83  * SUCH DAMAGE.
84  *
85  * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
86  */
87 
88 /*-
89  * Copyright (c) 2001 The NetBSD Foundation, Inc.
90  * All rights reserved.
91  *
92  * This code is derived from software contributed to The NetBSD Foundation
93  * by Jason R. Thorpe.
94  *
95  * Redistribution and use in source and binary forms, with or without
96  * modification, are permitted provided that the following conditions
97  * are met:
98  * 1. Redistributions of source code must retain the above copyright
99  * notice, this list of conditions and the following disclaimer.
100  * 2. Redistributions in binary form must reproduce the above copyright
101  * notice, this list of conditions and the following disclaimer in the
102  * documentation and/or other materials provided with the distribution.
103  * 3. All advertising materials mentioning features or use of this software
104  * must display the following acknowledgement:
105  * This product includes software developed by the NetBSD
106  * Foundation, Inc. and its contributors.
107  * 4. Neither the name of The NetBSD Foundation nor the names of its
108  * contributors may be used to endorse or promote products derived
109  * from this software without specific prior written permission.
110  *
111  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
112  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
113  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
114  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
115  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
116  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
117  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
118  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
119  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
120  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
121  * POSSIBILITY OF SUCH DAMAGE.
122  */
123 
124 /*
125  * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
126  *
127  * Taken from NetBSD
128  *
129  * "Stub" to allow remote cpu to debug over a serial line using gdb.
130  */
131 
132 
133 #include "arch/power/remote_gdb.hh"
134 
135 #include <sys/signal.h>
136 #include <unistd.h>
137 
138 #include <string>
139 
140 #include "arch/power/gdb-xml/gdb_xml_power64_core.hh"
141 #include "arch/power/gdb-xml/gdb_xml_power_core.hh"
142 #include "arch/power/gdb-xml/gdb_xml_power_fpu.hh"
143 #include "arch/power/gdb-xml/gdb_xml_powerpc_32.hh"
144 #include "arch/power/gdb-xml/gdb_xml_powerpc_64.hh"
145 #include "arch/power/pcstate.hh"
146 #include "arch/power/regs/misc.hh"
147 #include "cpu/thread_state.hh"
148 #include "debug/GDBAcc.hh"
149 #include "debug/GDBMisc.hh"
150 #include "mem/page_table.hh"
151 #include "sim/byteswap.hh"
152 
153 namespace gem5
154 {
155 
156 using namespace PowerISA;
157 
158 RemoteGDB::RemoteGDB(System *_system, int _port)
159  : BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
160 {
161 }
162 
163 /*
164  * Determine if the mapping at va..(va+len) is valid.
165  */
166 bool
167 RemoteGDB::acc(Addr va, size_t len)
168 {
169  // Check to make sure the first byte is mapped into the processes address
170  // space. At the time of this writing, the acc() check is used when
171  // processing the MemR/MemW packets before actually asking the translating
172  // port proxy to read/writeBlob. I (bgs) am not convinced the first byte
173  // check is enough.
174  panic_if(FullSystem, "acc not implemented for POWER FS!");
175  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
176 }
177 
178 void
179 RemoteGDB::PowerGdbRegCache::getRegs(ThreadContext *context)
180 {
181  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
182 
183  Msr msr = context->getReg(int_reg::Msr);
184  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
185 
186  // Default order on 32-bit PowerPC:
187  // R0-R31 (32-bit each), F0-F31 (64-bit IEEE754 double),
188  // PC, MSR, CR, LR, CTR, XER, FPSCR (32-bit each)
189 
190  for (int i = 0; i < int_reg::NumArchRegs; i++) {
192  r.gpr[i] = htog((uint32_t)context->getReg(reg), order);
193  }
194 
195  for (int i = 0; i < float_reg::NumArchRegs; i++)
196  r.fpr[i] = context->getReg(RegId(FloatRegClass, i));
197 
198  r.pc = htog((uint32_t)context->pcState().instAddr(), order);
199  r.msr = 0; // MSR is privileged, hence not exposed here
200  r.cr = htog((uint32_t)context->getReg(int_reg::Cr), order);
201  r.lr = htog((uint32_t)context->getReg(int_reg::Lr), order);
202  r.ctr = htog((uint32_t)context->getReg(int_reg::Ctr), order);
203  r.xer = htog((uint32_t)context->getReg(int_reg::Xer), order);
204  r.fpscr = htog((uint32_t)context->getReg(int_reg::Fpscr), order);
205 }
206 
207 void
208 RemoteGDB::PowerGdbRegCache::setRegs(ThreadContext *context) const
209 {
210  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
211 
212  Msr msr = context->getReg(int_reg::Msr);
213  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
214 
215  for (int i = 0; i < int_reg::NumArchRegs; i++)
216  context->setReg(RegId(IntRegClass, i), gtoh(r.gpr[i], order));
217 
218  for (int i = 0; i < float_reg::NumArchRegs; i++)
219  context->setReg(RegId(FloatRegClass, i), r.fpr[i]);
220 
221  auto pc = context->pcState().as<PowerISA::PCState>();
222  pc.byteOrder(order);
223  pc.set(gtoh(r.pc, order));
224  context->pcState(pc);
225  // MSR is privileged, hence not modified here
226  context->setReg(int_reg::Cr, gtoh(r.cr, order));
227  context->setReg(int_reg::Lr, gtoh(r.lr, order));
228  context->setReg(int_reg::Ctr, gtoh(r.ctr, order));
229  context->setReg(int_reg::Xer, gtoh(r.xer, order));
230  context->setReg(int_reg::Fpscr, gtoh(r.fpscr, order));
231 }
232 
233 void
234 RemoteGDB::Power64GdbRegCache::getRegs(ThreadContext *context)
235 {
236  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
237 
238  Msr msr = context->getReg(int_reg::Msr);
239  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
240 
241  // Default order on 64-bit PowerPC:
242  // GPRR0-GPRR31 (64-bit each), FPR0-FPR31 (64-bit IEEE754 double),
243  // CIA, MSR, CR, LR, CTR, XER, FPSCR (only CR, XER, FPSCR are 32-bit
244  // each and the rest are 64-bit)
245 
246  for (int i = 0; i < int_reg::NumArchRegs; i++)
247  r.gpr[i] = htog(context->getReg(RegId(IntRegClass, i)), order);
248 
249  for (int i = 0; i < float_reg::NumArchRegs; i++)
250  r.fpr[i] = context->getReg(RegId(FloatRegClass, i));
251 
252  r.pc = htog(context->pcState().instAddr(), order);
253  r.msr = 0; // MSR is privileged, hence not exposed here
254  r.cr = htog((uint32_t)context->getReg(int_reg::Cr), order);
255  r.lr = htog(context->getReg(int_reg::Lr), order);
256  r.ctr = htog(context->getReg(int_reg::Ctr), order);
257  r.xer = htog((uint32_t)context->getReg(int_reg::Xer), order);
258  r.fpscr = htog((uint32_t)context->getReg(int_reg::Fpscr), order);
259 }
260 
261 void
262 RemoteGDB::Power64GdbRegCache::setRegs(ThreadContext *context) const
263 {
264  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
265 
266  Msr msr = context->getReg(int_reg::Msr);
267  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
268 
269  for (int i = 0; i < int_reg::NumArchRegs; i++)
270  context->setReg(RegId(IntRegClass, i), gtoh(r.gpr[i], order));
271 
272  for (int i = 0; i < float_reg::NumArchRegs; i++)
273  context->setReg(RegId(FloatRegClass, i), r.fpr[i]);
274 
275  auto pc = context->pcState().as<PowerISA::PCState>();
276  pc.byteOrder(order);
277  pc.set(gtoh(r.pc, order));
278  context->pcState(pc);
279  // MSR is privileged, hence not modified here
280  context->setReg(int_reg::Cr, gtoh(r.cr, order));
281  context->setReg(int_reg::Lr, gtoh(r.lr, order));
282  context->setReg(int_reg::Ctr, gtoh(r.ctr, order));
283  context->setReg(int_reg::Xer, gtoh(r.xer, order));
284  context->setReg(int_reg::Fpscr, gtoh(r.fpscr, order));
285 }
286 
289 {
290  Msr msr = context()->getReg(int_reg::Msr);
291  if (msr.sf)
292  return &regCache64;
293  else
294  return &regCache32;
295 }
296 
297 bool
298 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
299 {
300 #define GDB_XML(x, s) \
301  { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
302  Blobs::s ## _len) }
303  static const std::map<std::string, std::string> annexMap32{
304  GDB_XML("target.xml", gdb_xml_powerpc_32),
305  GDB_XML("power-core.xml", gdb_xml_power_core),
306  GDB_XML("power-fpu.xml", gdb_xml_power_fpu)
307  };
308  static const std::map<std::string, std::string> annexMap64{
309  GDB_XML("target.xml", gdb_xml_powerpc_64),
310  GDB_XML("power64-core.xml", gdb_xml_power64_core),
311  GDB_XML("power-fpu.xml", gdb_xml_power_fpu)
312  };
313 #undef GDB_XML
314 
315  Msr msr = context()->getReg(int_reg::Msr);
316  auto& annexMap = msr.sf ? annexMap64 : annexMap32;
317  auto it = annexMap.find(annex);
318  if (it == annexMap.end())
319  return false;
320  output = it->second;
321  return true;
322 }
323 
324 } // namespace gem5
gem5::PowerISA::int_reg::Cr
constexpr RegId Cr(IntRegClass, _CrIdx)
remote_gdb.hh
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
thread_state.hh
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::output
static void output(const char *filename)
Definition: debug.cc:60
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::PowerISA::int_reg::Xer
constexpr RegId Xer(IntRegClass, _XerIdx)
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
GDB_XML
#define GDB_XML(x, s)
gem5::EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:133
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition: remote_gdb.hh:85
gem5::MipsISA::RemoteGDB::getXferFeaturesRead
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
gem5::PowerISA::int_reg::Ctr
constexpr RegId Ctr(IntRegClass, _CtrIdx)
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::MipsISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
pcstate.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:185
gem5::gtoh
T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194
gem5::PowerISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, int _port)
len
uint16_t len
Definition: helpers.cc:62
gem5::htog
T htog(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:187
misc.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::MipsISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs()
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::PowerISA::float_reg::NumArchRegs
const int NumArchRegs
Definition: float.hh:41
gem5::PowerISA::int_reg::Lr
constexpr RegId Lr(IntRegClass, _LrIdx)
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:395
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::PowerISA::int_reg::Fpscr
constexpr RegId Fpscr(IntRegClass, _FpscrIdx)
gem5::MipsISA::RemoteGDB::acc
bool acc(Addr addr, size_t len)
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PowerISA::int_reg::Msr
constexpr RegId Msr(IntRegClass, _MsrIdx)
byteswap.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183

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