gem5  v22.0.0.2
faults.cc
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1 /*
2  * Copyright (c) 2016 RISC-V Foundation
3  * Copyright (c) 2016 The University of Virginia
4  * Copyright (c) 2018 TU Dresden
5  * Copyright (c) 2020 Barkhausen Institut
6  * All rights reserved.
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31 
32 #include "arch/riscv/faults.hh"
33 
35 #include "arch/riscv/isa.hh"
36 #include "arch/riscv/regs/misc.hh"
37 #include "arch/riscv/utility.hh"
38 #include "cpu/base.hh"
39 #include "cpu/thread_context.hh"
40 #include "debug/Faults.hh"
41 #include "sim/debug.hh"
42 #include "sim/full_system.hh"
43 #include "sim/workload.hh"
44 
45 namespace gem5
46 {
47 
48 namespace RiscvISA
49 {
50 
51 void
53 {
54  panic("Fault %s encountered at pc %s.", name(), tc->pcState());
55 }
56 
57 void
59 {
60  auto pc_state = tc->pcState().as<PCState>();
61 
62  DPRINTFS(Faults, tc->getCpuPtr(), "Fault (%s) at PC: %s\n",
63  name(), pc_state);
64 
65  if (FullSystem) {
67  PrivilegeMode prv = PRV_M;
68  STATUS status = tc->readMiscReg(MISCREG_STATUS);
69 
70  // According to riscv-privileged-v1.11, if a NMI occurs at the middle
71  // of a M-mode trap handler, the state (epc/cause) will be overwritten
72  // and is not necessary recoverable. There's nothing we can do here so
73  // we'll just warn our user that the CPU state might be broken.
74  warn_if(isNonMaskableInterrupt() && pp == PRV_M && status.mie == 0,
75  "NMI overwriting M-mode trap handler state");
76 
77  // Set fault handler privilege mode
78  if (isNonMaskableInterrupt()) {
79  prv = PRV_M;
80  } else if (isInterrupt()) {
81  if (pp != PRV_M &&
82  bits(tc->readMiscReg(MISCREG_MIDELEG), _code) != 0) {
83  prv = PRV_S;
84  }
85  if (pp == PRV_U &&
86  bits(tc->readMiscReg(MISCREG_SIDELEG), _code) != 0) {
87  prv = PRV_U;
88  }
89  } else {
90  if (pp != PRV_M &&
91  bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) {
92  prv = PRV_S;
93  }
94  if (pp == PRV_U &&
95  bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
96  prv = PRV_U;
97  }
98  }
99 
100  // Set fault registers and status
101  MiscRegIndex cause, epc, tvec, tval;
102  switch (prv) {
103  case PRV_U:
104  cause = MISCREG_UCAUSE;
105  epc = MISCREG_UEPC;
106  tvec = MISCREG_UTVEC;
107  tval = MISCREG_UTVAL;
108 
109  status.upie = status.uie;
110  status.uie = 0;
111  break;
112  case PRV_S:
113  cause = MISCREG_SCAUSE;
114  epc = MISCREG_SEPC;
115  tvec = MISCREG_STVEC;
116  tval = MISCREG_STVAL;
117 
118  status.spp = pp;
119  status.spie = status.sie;
120  status.sie = 0;
121  break;
122  case PRV_M:
123  cause = MISCREG_MCAUSE;
124  epc = MISCREG_MEPC;
126  tval = MISCREG_MTVAL;
127 
128  status.mpp = pp;
129  status.mpie = status.mie;
130  status.mie = 0;
131  break;
132  default:
133  panic("Unknown privilege mode %d.", prv);
134  break;
135  }
136 
137  // Set fault cause, privilege, and return PC
138  // Interrupt is indicated on the MSB of cause (bit 63 in RV64)
139  uint64_t _cause = _code;
140  if (isInterrupt()) {
141  _cause |= (1L << 63);
142  }
143  tc->setMiscReg(cause, _cause);
144  tc->setMiscReg(epc, tc->pcState().instAddr());
145  tc->setMiscReg(tval, trap_value());
146  tc->setMiscReg(MISCREG_PRV, prv);
148  // Temporarily mask NMI while we're in NMI handler. Otherweise, the
149  // checkNonMaskableInterrupt will always return true and we'll be
150  // stucked in an infinite loop.
151  if (isNonMaskableInterrupt()) {
152  tc->setMiscReg(MISCREG_NMIE, 0);
153  }
154 
155  // Set PC to fault handler address
156  Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
157  if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
158  addr += 4 * _code;
159  pc_state.set(addr);
160  tc->pcState(pc_state);
161  } else {
162  inst->advancePC(pc_state);
163  tc->pcState(pc_state);
164  invokeSE(tc, inst);
165  }
166 }
167 
168 void
170 {
172  STATUS status = tc->readMiscReg(MISCREG_STATUS);
173  status.mie = 0;
174  status.mprv = 0;
176  tc->setMiscReg(MISCREG_MCAUSE, 0);
177 
178  // Advance the PC to the implementation-defined reset vector
179  auto workload = dynamic_cast<Workload *>(tc->getSystemPtr()->workload);
180  PCState pc(workload->getEntry());
181  tc->pcState(pc);
182 }
183 
184 void
186 {
187  auto *rsi = static_cast<RiscvStaticInst *>(inst.get());
188  panic("Unknown instruction 0x%08x at pc %s", rsi->machInst,
189  tc->pcState());
190 }
191 
192 void
194 {
195  auto *rsi = static_cast<RiscvStaticInst *>(inst.get());
196  panic("Illegal instruction 0x%08x at pc %s: %s", rsi->machInst,
197  tc->pcState(), reason.c_str());
198 }
199 
200 void
202 {
203  panic("Unimplemented instruction %s at pc %s", instName, tc->pcState());
204 }
205 
206 void
208 {
209  panic("Illegal floating-point rounding mode 0x%x at pc %s.",
210  frm, tc->pcState());
211 }
212 
213 void
215 {
216  schedRelBreak(0);
217 }
218 
219 void
221 {
222  tc->getSystemPtr()->workload->syscall(tc);
223 }
224 
225 } // namespace RiscvISA
226 } // namespace gem5
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:56
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:71
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::RiscvISA::UnimplementedFault::instName
const std::string instName
Definition: faults.hh:202
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:57
faults.hh
gem5::X86ISA::L
Bitfield< 7, 0 > L
Definition: int.hh:61
gem5::RiscvISA::MISCREG_SIDELEG
@ MISCREG_SIDELEG
Definition: misc.hh:173
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:51
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::RiscvISA::RiscvFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:58
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:53
gem5::RiscvISA::MISCREG_MTVAL
@ MISCREG_MTVAL
Definition: misc.hh:150
gem5::RiscvISA::IllegalFrmFault::frm
const uint8_t frm
Definition: faults.hh:216
gem5::RiscvISA::MISCREG_SEDELEG
@ MISCREG_SEDELEG
Definition: misc.hh:172
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::RiscvISA::RiscvFault::isInterrupt
bool isInterrupt() const
Definition: faults.hh:118
isa.hh
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
misc.hh
gem5::RefCountingPtr< StaticInst >
gem5::RiscvISA::MISCREG_SCAUSE
@ MISCREG_SCAUSE
Definition: misc.hh:178
gem5::RiscvISA::MISCREG_NMIE
@ MISCREG_NMIE
Definition: misc.hh:196
gem5::RiscvISA::MISCREG_MEDELEG
@ MISCREG_MEDELEG
Definition: misc.hh:143
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
gem5::schedRelBreak
void schedRelBreak(Tick delta)
Cause the simulator to execute a breakpoint relative to the current tick.
Definition: debug.cc:93
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
workload.hh
gem5::RiscvISA::MISCREG_SEPC
@ MISCREG_SEPC
Definition: misc.hh:177
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
debug.hh
gem5::RiscvISA::RiscvFault::name
FaultName name() const override
Definition: faults.hh:117
gem5::RiscvISA::IllegalInstFault::reason
const std::string reason
Definition: faults.hh:188
gem5::Workload
Definition: workload.hh:49
gem5::RiscvISA::MISCREG_MCAUSE
@ MISCREG_MCAUSE
Definition: misc.hh:149
gem5::RiscvISA::RiscvFault::_code
ExceptionCode _code
Definition: faults.hh:111
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::RiscvISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:169
gem5::RiscvISA::MISCREG_NMIVEC
@ MISCREG_NMIVEC
Definition: misc.hh:194
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
DPRINTFS
#define DPRINTFS(x, s,...)
Definition: trace.hh:193
gem5::RiscvISA::MISCREG_MEPC
@ MISCREG_MEPC
Definition: misc.hh:148
full_system.hh
gem5::RiscvISA::UnknownInstFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:185
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:273
gem5::RiscvISA::IllegalFrmFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:207
gem5::RiscvISA::MISCREG_UTVEC
@ MISCREG_UTVEC
Definition: misc.hh:182
base.hh
gem5::RiscvISA::SyscallFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:220
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::RiscvISA::BreakpointFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:214
gem5::RiscvISA::IllegalInstFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:193
gem5::RiscvISA::MISCREG_UEPC
@ MISCREG_UEPC
Definition: misc.hh:184
gem5::RiscvISA::MISCREG_MIDELEG
@ MISCREG_MIDELEG
Definition: misc.hh:144
utility.hh
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::RiscvISA::MISCREG_STVAL
@ MISCREG_STVAL
Definition: misc.hh:179
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:55
gem5::RiscvISA::RiscvFault::trap_value
virtual RegVal trap_value() const
Definition: faults.hh:124
gem5::RiscvISA::MISCREG_UCAUSE
@ MISCREG_UCAUSE
Definition: misc.hh:185
gem5::RiscvISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:63
gem5::RiscvISA::MISCREG_UTVAL
@ MISCREG_UTVAL
Definition: misc.hh:186
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::MISCREG_PRV
@ MISCREG_PRV
Definition: misc.hh:65
gem5::RiscvISA::UnimplementedFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:201
gem5::RiscvISA::MISCREG_STVEC
@ MISCREG_STVEC
Definition: misc.hh:174
thread_context.hh
gem5::RiscvISA::RiscvFault::invokeSE
virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:52
gem5::RiscvISA::MISCREG_MTVEC
@ MISCREG_MTVEC
Definition: misc.hh:145
gem5::RiscvISA::RiscvFault::isNonMaskableInterrupt
bool isNonMaskableInterrupt() const
Definition: faults.hh:119
gem5::Workload::syscall
virtual void syscall(ThreadContext *tc)
Definition: workload.hh:109
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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