gem5 v24.0.0.0
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gem5::RiscvISA::VsIndexMicroInst Class Reference

#include <vector.hh>

Inheritance diagram for gem5::RiscvISA::VsIndexMicroInst:
gem5::RiscvISA::VectorMemMicroInst gem5::RiscvISA::VectorMicroInst gem5::RiscvISA::RiscvMicroInst gem5::RiscvISA::RiscvStaticInst gem5::StaticInst gem5::RefCounted

Protected Member Functions

 VsIndexMicroInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _vs3RegIdx, uint32_t _vs3ElemIdx, uint32_t _vs2RegIdx, uint32_t _vs2ElemIdx)
 
std::string generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override
 Internal function to generate disassembly string.
 
- Protected Member Functions inherited from gem5::RiscvISA::VectorMemMicroInst
 VectorMemMicroInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _microVl, uint32_t _microIdx, uint32_t _offset)
 
- Protected Member Functions inherited from gem5::RiscvISA::VectorMicroInst
 VectorMicroInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _microVl, uint32_t _microIdx, uint32_t _vlen=256)
 
- Protected Member Functions inherited from gem5::RiscvISA::RiscvMicroInst
 RiscvMicroInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 
void advancePC (PCStateBase &pcState) const override
 
void advancePC (ThreadContext *tc) const override
 
- Protected Member Functions inherited from gem5::RiscvISA::RiscvStaticInst
 RiscvStaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 
template<typename T >
rvSelect (T v32, T v64) const
 
template<typename T32 , typename T64 >
T64 rvExt (T64 x) const
 
uint64_t rvZext (uint64_t x) const
 
int64_t rvSext (int64_t x) const
 
- Protected Member Functions inherited from gem5::StaticInst
void setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest)
 Set the pointers which point to the arrays of source and destination register indices.
 
 StaticInst (const char *_mnemonic, OpClass op_class)
 Constructor.
 
template<typename T >
size_t simpleAsBytes (void *buf, size_t max_size, const T &t)
 

Protected Attributes

uint32_t vs3RegIdx
 
uint32_t vs3ElemIdx
 
uint32_t vs2RegIdx
 
uint32_t vs2ElemIdx
 
- Protected Attributes inherited from gem5::RiscvISA::VectorMemMicroInst
uint32_t offset
 
Request::Flags memAccessFlags
 
- Protected Attributes inherited from gem5::RiscvISA::VectorMicroInst
uint32_t vlen
 
uint32_t microVl
 
uint32_t microIdx
 
uint8_t vtype
 
- Protected Attributes inherited from gem5::StaticInst
std::bitset< Num_Flags > flags
 Flag values for this instruction.
 
OpClass _opClass
 See opClass().
 
uint8_t _numSrcRegs = 0
 See numSrcRegs().
 
uint8_t _numDestRegs = 0
 See numDestRegs().
 
std::array< uint8_t, MiscRegClass+1 > _numTypedDestRegs = {}
 
size_t _size = 0
 Instruction size in bytes.
 
const char * mnemonic
 Base mnemonic (e.g., "add").
 
std::unique_ptr< std::string > cachedDisassembly
 String representation of disassembly (lazily evaluated via disassemble()).
 

Additional Inherited Members

- Public Types inherited from gem5::StaticInst
using RegIdArrayPtr = RegId (StaticInst:: *)[]
 
- Public Member Functions inherited from gem5::RiscvISA::RiscvStaticInst
void advancePC (PCStateBase &pc) const override
 
void advancePC (ThreadContext *tc) const override
 
std::unique_ptr< PCStateBasebuildRetPC (const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
 
size_t asBytes (void *buf, size_t size) override
 Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.
 
- Public Member Functions inherited from gem5::StaticInst
uint8_t numSrcRegs () const
 Number of source registers.
 
uint8_t numDestRegs () const
 Number of destination registers.
 
uint8_t numDestRegs (RegClassType type) const
 Number of destination registers of a particular type.
 
bool isNop () const
 
bool isMemRef () const
 
bool isLoad () const
 
bool isStore () const
 
bool isAtomic () const
 
bool isStoreConditional () const
 
bool isInstPrefetch () const
 
bool isDataPrefetch () const
 
bool isPrefetch () const
 
bool isInteger () const
 
bool isFloating () const
 
bool isVector () const
 
bool isMatrix () const
 
bool isControl () const
 
bool isCall () const
 
bool isReturn () const
 
bool isDirectCtrl () const
 
bool isIndirectCtrl () const
 
bool isCondCtrl () const
 
bool isUncondCtrl () const
 
bool isSerializing () const
 
bool isSerializeBefore () const
 
bool isSerializeAfter () const
 
bool isSquashAfter () const
 
bool isFullMemBarrier () const
 
bool isReadBarrier () const
 
bool isWriteBarrier () const
 
bool isNonSpeculative () const
 
bool isQuiesce () const
 
bool isUnverifiable () const
 
bool isPseudo () const
 
bool isSyscall () const
 
bool isMacroop () const
 
bool isMicroop () const
 
bool isDelayedCommit () const
 
bool isLastMicroop () const
 
bool isFirstMicroop () const
 
bool isHtmStart () const
 
bool isHtmStop () const
 
bool isHtmCancel () const
 
bool isInvalid () const
 
bool isHtmCmd () const
 
void setFirstMicroop ()
 
void setLastMicroop ()
 
void setDelayedCommit ()
 
void setFlag (Flags f)
 
OpClass opClass () const
 Operation class. Used to select appropriate function unit in issue.
 
const RegIddestRegIdx (int i) const
 Return logical index (architectural reg num) of i'th destination reg.
 
void setDestRegIdx (int i, const RegId &val)
 
const RegIdsrcRegIdx (int i) const
 Return logical index (architectural reg num) of i'th source reg.
 
void setSrcRegIdx (int i, const RegId &val)
 
virtual uint64_t getEMI () const
 
virtual ~StaticInst ()
 
virtual Fault execute (ExecContext *xc, trace::InstRecord *traceData) const =0
 
virtual Fault initiateAcc (ExecContext *xc, trace::InstRecord *traceData) const
 
virtual Fault completeAcc (Packet *pkt, ExecContext *xc, trace::InstRecord *trace_data) const
 
size_t size () const
 
virtual void size (size_t newSize)
 
virtual StaticInstPtr fetchMicroop (MicroPC upc) const
 Return the microop that goes with a particular micropc.
 
virtual std::unique_ptr< PCStateBasebranchTarget (const PCStateBase &pc) const
 Return the target address for a PC-relative branch.
 
virtual std::unique_ptr< PCStateBasebranchTarget (ThreadContext *tc) const
 Return the target address for an indirect branch (jump).
 
virtual const std::string & disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const
 Return string representation of disassembled instruction.
 
void printFlags (std::ostream &outs, const std::string &separator) const
 Print a separator separated list of this instruction's set flag names on the given stream.
 
std::string getName ()
 Return name of machine instruction.
 
- Public Member Functions inherited from gem5::RefCounted
 RefCounted ()
 We initialize the reference count to zero and the first object to take ownership of it must increment it to one.
 
virtual ~RefCounted ()
 We make the destructor virtual because we're likely to have virtual functions on reference counted objects.
 
void incref () const
 Increment the reference count.
 
void decref () const
 Decrement the reference count and destroy the object if all references are gone.
 
- Public Attributes inherited from gem5::RiscvISA::RiscvStaticInst
ExtMachInst machInst
 
- Static Public Attributes inherited from gem5::StaticInst
static StaticInstPtr nullStaticInstPtr
 Pointer to a statically allocated "null" instruction object.
 

Detailed Description

Definition at line 503 of file vector.hh.

Constructor & Destructor Documentation

◆ VsIndexMicroInst()

gem5::RiscvISA::VsIndexMicroInst::VsIndexMicroInst ( const char * mnem,
ExtMachInst _machInst,
OpClass __opClass,
uint32_t _vs3RegIdx,
uint32_t _vs3ElemIdx,
uint32_t _vs2RegIdx,
uint32_t _vs2ElemIdx )
inlineprotected

Definition at line 510 of file vector.hh.

Member Function Documentation

◆ generateDisassembly()

std::string gem5::RiscvISA::VsIndexMicroInst::generateDisassembly ( Addr pc,
const loader::SymbolTable * symtab ) const
overrideprotectedvirtual

Member Data Documentation

◆ vs2ElemIdx

uint32_t gem5::RiscvISA::VsIndexMicroInst::vs2ElemIdx
protected

Definition at line 509 of file vector.hh.

Referenced by generateDisassembly().

◆ vs2RegIdx

uint32_t gem5::RiscvISA::VsIndexMicroInst::vs2RegIdx
protected

Definition at line 508 of file vector.hh.

◆ vs3ElemIdx

uint32_t gem5::RiscvISA::VsIndexMicroInst::vs3ElemIdx
protected

Definition at line 507 of file vector.hh.

Referenced by generateDisassembly().

◆ vs3RegIdx

uint32_t gem5::RiscvISA::VsIndexMicroInst::vs3RegIdx
protected

Definition at line 506 of file vector.hh.


The documentation for this class was generated from the following files:

Generated on Tue Jun 18 2024 16:24:22 for gem5 by doxygen 1.11.0