gem5  v21.1.0.2
gic_v3_distributor.hh
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40 
41 #ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
42 #define __DEV_ARM_GICV3_DISTRIBUTOR_H__
43 
44 #include "base/addr_range.hh"
45 #include "dev/arm/gic_v3.hh"
46 #include "sim/serialize.hh"
47 
48 namespace gem5
49 {
50 
52 {
53  private:
54 
55  friend class Gicv3Redistributor;
56  friend class Gicv3CPUInterface;
57  friend class Gicv3Its;
58 
59  protected:
60 
62  const uint32_t itLines;
63 
64  enum
65  {
66  // Control Register
67  GICD_CTLR = 0x0000,
68  // Interrupt Controller Type Register
69  GICD_TYPER = 0x0004,
70  // Implementer Identification Register
71  GICD_IIDR = 0x0008,
72  // Interrupt Controller Type Register 2
73  GICD_TYPER2 = 0x000C,
74  // Error Reporting Status Register
75  GICD_STATUSR = 0x0010,
76  // Set Non-secure SPI Pending Register
77  GICD_SETSPI_NSR = 0x0040,
78  // Clear Non-secure SPI Pending Register
79  GICD_CLRSPI_NSR = 0x0048,
80  // Set Secure SPI Pending Register
81  GICD_SETSPI_SR = 0x0050,
82  // Clear Secure SPI Pending Register
83  GICD_CLRSPI_SR = 0x0058,
84  // Software Generated Interrupt Register
85  GICD_SGIR = 0x0f00,
86  // Peripheral ID0 Register
87  GICD_PIDR0 = 0xffe0,
88  // Peripheral ID1 Register
89  GICD_PIDR1 = 0xffe4,
90  // Peripheral ID2 Register
91  GICD_PIDR2 = 0xffe8,
92  // Peripheral ID3 Register
93  GICD_PIDR3 = 0xffec,
94  // Peripheral ID4 Register
95  GICD_PIDR4 = 0xffd0,
96  // Peripheral ID5 Register
97  GICD_PIDR5 = 0xffd4,
98  // Peripheral ID6 Register
99  GICD_PIDR6 = 0xffd8,
100  // Peripheral ID7 Register
101  GICD_PIDR7 = 0xffdc,
102  };
103 
104  // Interrupt Group Registers
105  static const AddrRange GICD_IGROUPR;
106  // Interrupt Set-Enable Registers
107  static const AddrRange GICD_ISENABLER;
108  // Interrupt Clear-Enable Registers
109  static const AddrRange GICD_ICENABLER;
110  // Interrupt Set-Pending Registers
111  static const AddrRange GICD_ISPENDR;
112  // Interrupt Clear-Pending Registers
113  static const AddrRange GICD_ICPENDR;
114  // Interrupt Set-Active Registers
115  static const AddrRange GICD_ISACTIVER;
116  // Interrupt Clear-Active Registers
117  static const AddrRange GICD_ICACTIVER;
118  // Interrupt Priority Registers
120  // Interrupt Processor Targets Registers
121  static const AddrRange GICD_ITARGETSR; // GICv2 legacy
122  // Interrupt Configuration Registers
123  static const AddrRange GICD_ICFGR;
124  // Interrupt Group Modifier Registers
125  static const AddrRange GICD_IGRPMODR;
126  // Non-secure Access Control Registers
127  static const AddrRange GICD_NSACR;
128  // SGI Clear-Pending Registers
129  static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
130  // SGI Set-Pending Registers
131  static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
132  // Interrupt Routing Registers
133  static const AddrRange GICD_IROUTER;
134 
135  BitUnion64(IROUTER)
136  Bitfield<63, 40> res0_1;
137  Bitfield<39, 32> Aff3;
138  Bitfield<31> IRM;
139  Bitfield<30, 24> res0_2;
140  Bitfield<23, 16> Aff2;
141  Bitfield<15, 8> Aff1;
142  Bitfield<7, 0> Aff0;
143  EndBitUnion(IROUTER)
144 
145  static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0;
146  static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0;
147  static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
148  static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1;
149  static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2;
150  static const uint32_t GICD_CTLR_DS = 1 << 6;
151 
152  bool ARE;
153  bool DS;
157  std::vector <uint8_t> irqGroup;
162  std::vector <uint8_t> irqPriority;
163  std::vector <Gicv3::IntTriggerType> irqConfig;
164  std::vector <uint8_t> irqGrpmod;
165  std::vector <uint8_t> irqNsacr;
167 
168  uint32_t gicdTyper;
169  uint32_t gicdPidr0;
170  uint32_t gicdPidr1;
171  uint32_t gicdPidr2;
172  uint32_t gicdPidr3;
173  uint32_t gicdPidr4;
174 
175  public:
176 
177  static const uint32_t ADDR_RANGE_SIZE = 0x10000;
178  static const uint32_t IDBITS = 0xf;
179 
180  protected:
181 
182  void activateIRQ(uint32_t int_id);
183  void deactivateIRQ(uint32_t int_id);
184  void fullUpdate();
185  Gicv3::GroupId getIntGroup(int int_id) const;
186 
187  inline bool
188  groupEnabled(Gicv3::GroupId group) const
189  {
190  if (DS == 0) {
191  switch (group) {
192  case Gicv3::G0S:
193  return EnableGrp0;
194 
195  case Gicv3::G1S:
196  return EnableGrp1S;
197 
198  case Gicv3::G1NS:
199  return EnableGrp1NS;
200 
201  default:
202  panic("Gicv3Distributor::groupEnabled(): "
203  "invalid group!\n");
204  }
205  } else {
206  switch (group) {
207  case Gicv3::G0S:
208  return EnableGrp0;
209 
210  case Gicv3::G1S:
211  case Gicv3::G1NS:
212  return EnableGrp1NS;
213 
214  default:
215  panic("Gicv3Distributor::groupEnabled(): "
216  "invalid group!\n");
217  }
218  }
219  }
220 
221  Gicv3::IntStatus intStatus(uint32_t int_id) const;
222 
223  inline bool isNotSPI(uint32_t int_id) const
224  {
225  if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) {
226  return true;
227  } else {
228  return false;
229  }
230  }
231 
232  bool isLevelSensitive(uint32_t int_id) const
233  {
234  return irqConfig[int_id] == Gicv3::INT_LEVEL_SENSITIVE;
235  }
236 
248  bool treatAsEdgeTriggered(uint32_t int_id) const
249  {
250  return !isLevelSensitive(int_id) || irqPendingIspendr[int_id];
251  }
252 
253  inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const
254  {
255  return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
256  }
257 
258  void serialize(CheckpointOut & cp) const override;
259  void unserialize(CheckpointIn & cp) override;
260  void update();
261  Gicv3CPUInterface* route(uint32_t int_id);
262 
263  public:
264 
265  Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
266 
267  void sendInt(uint32_t int_id);
268  void clearInt(uint32_t int_id);
269  void deassertSPI(uint32_t int_id);
270  void clearIrqCpuInterface(uint32_t int_id);
271  void init();
272  uint64_t read(Addr addr, size_t size, bool is_secure_access);
273  void write(Addr addr, uint64_t data, size_t size,
274  bool is_secure_access);
275 };
276 
277 } // namespace gem5
278 
279 #endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
gem5::Gicv3Distributor::isLevelSensitive
bool isLevelSensitive(uint32_t int_id) const
Definition: gic_v3_distributor.hh:232
gem5::Gicv3Distributor::GICD_CTLR_DS
static const uint32_t GICD_CTLR_DS
Definition: gic_v3_distributor.hh:150
gem5::Gicv3::G1NS
@ G1NS
Definition: gic_v3.hh:97
gem5::Gicv3Distributor::gicdTyper
uint32_t gicdTyper
Definition: gic_v3_distributor.hh:168
gem5::Gicv3Distributor::route
Gicv3CPUInterface * route(uint32_t int_id)
Definition: gic_v3_distributor.cc:1040
data
const char data[]
Definition: circlebuf.test.cc:48
serialize.hh
gem5::Gicv3Distributor::treatAsEdgeTriggered
bool treatAsEdgeTriggered(uint32_t int_id) const
This helper is used to check if an interrupt should be treated as edge triggered in the following sce...
Definition: gic_v3_distributor.hh:248
gem5::X86ISA::vector
Bitfield< 15, 8 > vector
Definition: intmessage.hh:48
gem5::Gicv3Distributor::res0_1
res0_1
Definition: gic_v3_distributor.hh:136
gem5::Gicv3Redistributor
Definition: gic_v3_redistributor.hh:55
gem5::Gicv3Distributor::init
void init()
Definition: gic_v3_distributor.cc:136
gem5::Gicv3Distributor::GICD_IPRIORITYR
static const AddrRange GICD_IPRIORITYR
Definition: gic_v3_distributor.hh:119
gem5::Gicv3Distributor::irqGrpmod
std::vector< uint8_t > irqGrpmod
Definition: gic_v3_distributor.hh:164
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Gicv3Distributor::GICD_STATUSR
@ GICD_STATUSR
Definition: gic_v3_distributor.hh:75
gem5::Gicv3Distributor::GICD_SETSPI_SR
@ GICD_SETSPI_SR
Definition: gic_v3_distributor.hh:81
gem5::Gicv3Distributor::intStatus
Gicv3::IntStatus intStatus(uint32_t int_id) const
Definition: gic_v3_distributor.cc:1120
gem5::Gicv3Distributor::GICD_PIDR7
@ GICD_PIDR7
Definition: gic_v3_distributor.hh:101
gem5::Gicv3Distributor::GICD_PIDR4
@ GICD_PIDR4
Definition: gic_v3_distributor.hh:95
gem5::Gicv3Distributor::irqPendingIspendr
std::vector< bool > irqPendingIspendr
Definition: gic_v3_distributor.hh:160
gem5::Gicv3Distributor::GICD_NSACR
static const AddrRange GICD_NSACR
Definition: gic_v3_distributor.hh:127
gem5::Gicv3Distributor::irqNsacr
std::vector< uint8_t > irqNsacr
Definition: gic_v3_distributor.hh:165
gem5::Gicv3::PPI_MAX
static const int PPI_MAX
Definition: gic_v3.hh:81
gem5::Gicv3Distributor::EndBitUnion
EndBitUnion(IROUTER) static const uint32_t GICD_CTLR_ENABLEGRP0
gem5::Gicv3Distributor::GICD_PIDR6
@ GICD_PIDR6
Definition: gic_v3_distributor.hh:99
gem5::Gicv3Distributor::update
void update()
Definition: gic_v3_distributor.cc:1085
gem5::Gicv3Distributor::deassertSPI
void deassertSPI(uint32_t int_id)
Definition: gic_v3_distributor.cc:1029
gem5::Gicv3Distributor::GICD_SGIR
@ GICD_SGIR
Definition: gic_v3_distributor.hh:85
gem5::Gicv3Distributor::GICD_CPENDSGIR
static const AddrRange GICD_CPENDSGIR
Definition: gic_v3_distributor.hh:129
gem5::Gicv3Distributor::GICD_IGROUPR
static const AddrRange GICD_IGROUPR
Definition: gic_v3_distributor.hh:105
gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1
static const uint32_t GICD_CTLR_ENABLEGRP1
Definition: gic_v3_distributor.hh:146
gem5::Gicv3Distributor::GICD_SETSPI_NSR
@ GICD_SETSPI_NSR
Definition: gic_v3_distributor.hh:77
gem5::Gicv3Distributor::GICD_IIDR
@ GICD_IIDR
Definition: gic_v3_distributor.hh:71
gem5::Gicv3Distributor::irqPending
std::vector< bool > irqPending
Definition: gic_v3_distributor.hh:159
gem5::Gicv3Distributor::isNotSPI
bool isNotSPI(uint32_t int_id) const
Definition: gic_v3_distributor.hh:223
gem5::Gicv3Distributor::GICD_ICENABLER
static const AddrRange GICD_ICENABLER
Definition: gic_v3_distributor.hh:109
gem5::Gicv3Distributor::GICD_CLRSPI_SR
@ GICD_CLRSPI_SR
Definition: gic_v3_distributor.hh:83
gem5::Gicv3Distributor::EnableGrp1NS
bool EnableGrp1NS
Definition: gic_v3_distributor.hh:155
gem5::Gicv3Distributor::activateIRQ
void activateIRQ(uint32_t int_id)
Definition: gic_v3_distributor.cc:1166
gem5::Gicv3Distributor::ARE
bool ARE
Definition: gic_v3_distributor.hh:152
gem5::Gicv3Distributor::GICD_ICFGR
static const AddrRange GICD_ICFGR
Definition: gic_v3_distributor.hh:123
gem5::Gicv3Distributor::GICD_IGRPMODR
static const AddrRange GICD_IGRPMODR
Definition: gic_v3_distributor.hh:125
gem5::Gicv3Distributor::write
void write(Addr addr, uint64_t data, size_t size, bool is_secure_access)
Definition: gic_v3_distributor.cc:513
gem5::Gicv3Distributor::DS
bool DS
Definition: gic_v3_distributor.hh:153
gem5::Gicv3Distributor::gicdPidr4
uint32_t gicdPidr4
Definition: gic_v3_distributor.hh:173
gem5::Gicv3Distributor::GICD_IROUTER
static const AddrRange GICD_IROUTER
Definition: gic_v3_distributor.hh:133
gem5::Gicv3Distributor::GICD_TYPER2
@ GICD_TYPER2
Definition: gic_v3_distributor.hh:73
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::Gicv3Distributor::GICD_ICPENDR
static const AddrRange GICD_ICPENDR
Definition: gic_v3_distributor.hh:113
gem5::Gicv3Distributor::sendInt
void sendInt(uint32_t int_id)
Definition: gic_v3_distributor.cc:1007
gem5::Gicv3Distributor::GICD_PIDR0
@ GICD_PIDR0
Definition: gic_v3_distributor.hh:87
gem5::Gicv3::INT_LEVEL_SENSITIVE
@ INT_LEVEL_SENSITIVE
Definition: gic_v3.hh:102
gem5::Gicv3Distributor::getIntGroup
Gicv3::GroupId getIntGroup(int int_id) const
Definition: gic_v3_distributor.cc:1139
gem5::Gicv3Distributor::res0_2
Bitfield< 30, 24 > res0_2
Definition: gic_v3_distributor.hh:139
gem5::Gicv3Distributor::Aff0
Bitfield< 7, 0 > Aff0
Definition: gic_v3_distributor.hh:142
gem5::Gicv3Distributor::groupEnabled
bool groupEnabled(Gicv3::GroupId group) const
Definition: gic_v3_distributor.hh:188
gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1S
static const uint32_t GICD_CTLR_ENABLEGRP1S
Definition: gic_v3_distributor.hh:149
gem5::Gicv3Distributor::GICD_ITARGETSR
static const AddrRange GICD_ITARGETSR
Definition: gic_v3_distributor.hh:121
gem5::Gicv3Distributor::GICD_CLRSPI_NSR
@ GICD_CLRSPI_NSR
Definition: gic_v3_distributor.hh:79
gem5::Gicv3Distributor::BitUnion64
BitUnion64(IROUTER) Bitfield< 63
gem5::Gicv3Distributor::Aff3
Bitfield< 39, 32 > Aff3
Definition: gic_v3_distributor.hh:137
gem5::Gicv3Distributor::gicdPidr2
uint32_t gicdPidr2
Definition: gic_v3_distributor.hh:171
gem5::Gicv3Distributor::GICD_PIDR1
@ GICD_PIDR1
Definition: gic_v3_distributor.hh:89
gem5::Gicv3Distributor::IDBITS
static const uint32_t IDBITS
Definition: gic_v3_distributor.hh:178
gem5::Gicv3Distributor::clearIrqCpuInterface
void clearIrqCpuInterface(uint32_t int_id)
Definition: gic_v3_distributor.cc:1077
gem5::Gicv3Distributor::GICD_CTLR
@ GICD_CTLR
Definition: gic_v3_distributor.hh:67
gem5::Gicv3Distributor::irqEnabled
std::vector< bool > irqEnabled
Definition: gic_v3_distributor.hh:158
gem5::Gicv3Distributor::fullUpdate
void fullUpdate()
gem5::Gicv3Distributor::read
uint64_t read(Addr addr, size_t size, bool is_secure_access)
Definition: gic_v3_distributor.cc:141
gem5::Gicv3Distributor::Aff2
Bitfield< 23, 16 > Aff2
Definition: gic_v3_distributor.hh:140
gem5::Gicv3Distributor::EnableGrp0
bool EnableGrp0
Definition: gic_v3_distributor.hh:156
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Gicv3Distributor::gic
Gicv3 * gic
Definition: gic_v3_distributor.hh:61
gem5::Gicv3Distributor::GICD_ICACTIVER
static const AddrRange GICD_ICACTIVER
Definition: gic_v3_distributor.hh:117
gem5::Gicv3Distributor::irqActive
std::vector< bool > irqActive
Definition: gic_v3_distributor.hh:161
gem5::Gicv3Distributor::clearInt
void clearInt(uint32_t int_id)
Definition: gic_v3_distributor.cc:1019
addr_range.hh
gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1NS
static const uint32_t GICD_CTLR_ENABLEGRP1NS
Definition: gic_v3_distributor.hh:147
gem5::Gicv3::G0S
@ G0S
Definition: gic_v3.hh:95
gem5::Gicv3Distributor::GICD_ISACTIVER
static const AddrRange GICD_ISACTIVER
Definition: gic_v3_distributor.hh:115
gem5::Gicv3Distributor::GICD_ISPENDR
static const AddrRange GICD_ISPENDR
Definition: gic_v3_distributor.hh:111
gem5::Gicv3Distributor::GICD_PIDR2
@ GICD_PIDR2
Definition: gic_v3_distributor.hh:91
gem5::Gicv3Distributor::itLines
const uint32_t itLines
Definition: gic_v3_distributor.hh:62
gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1A
static const uint32_t GICD_CTLR_ENABLEGRP1A
Definition: gic_v3_distributor.hh:148
gem5::Gicv3Distributor::gicdPidr0
uint32_t gicdPidr0
Definition: gic_v3_distributor.hh:169
gem5::Gicv3Distributor::EnableGrp1S
bool EnableGrp1S
Definition: gic_v3_distributor.hh:154
gem5::Gicv3
Definition: gic_v3.hh:56
gem5::Gicv3Distributor
Definition: gic_v3_distributor.hh:51
gem5::Gicv3Distributor::GICD_TYPER
@ GICD_TYPER
Definition: gic_v3_distributor.hh:69
gem5::Gicv3Distributor::GICD_ISENABLER
static const AddrRange GICD_ISENABLER
Definition: gic_v3_distributor.hh:107
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:53
gem5::Gicv3Its
GICv3 ITS module.
Definition: gic_v3_its.hh:83
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
gem5::Gicv3::IntStatus
IntStatus
Definition: gic_v3.hh:84
gem5::Gicv3::SGI_MAX
static const int SGI_MAX
Definition: gic_v3.hh:79
gem5::Gicv3Distributor::irqAffinityRouting
std::vector< IROUTER > irqAffinityRouting
Definition: gic_v3_distributor.hh:166
gem5::Gicv3Distributor::gicdPidr3
uint32_t gicdPidr3
Definition: gic_v3_distributor.hh:172
gem5::Gicv3Distributor::nsAccessToSecInt
bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const
Definition: gic_v3_distributor.hh:253
gem5::Gicv3Distributor::irqConfig
std::vector< Gicv3::IntTriggerType > irqConfig
Definition: gic_v3_distributor.hh:163
gem5::Gicv3Distributor::Gicv3Distributor
Gicv3Distributor(Gicv3 *gic, uint32_t it_lines)
Definition: gic_v3_distributor.cc:71
gem5::Gicv3Distributor::gicdPidr1
uint32_t gicdPidr1
Definition: gic_v3_distributor.hh:170
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3Distributor::GICD_PIDR5
@ GICD_PIDR5
Definition: gic_v3_distributor.hh:97
gem5::Gicv3::G1S
@ G1S
Definition: gic_v3.hh:96
gem5::Gicv3Distributor::Aff1
Bitfield< 15, 8 > Aff1
Definition: gic_v3_distributor.hh:141
gem5::Gicv3Distributor::irqGroup
std::vector< uint8_t > irqGroup
Definition: gic_v3_distributor.hh:157
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Gicv3Distributor::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3_distributor.cc:1181
gem5::Gicv3Distributor::ADDR_RANGE_SIZE
static const uint32_t ADDR_RANGE_SIZE
Definition: gic_v3_distributor.hh:177
gem5::Gicv3Distributor::deactivateIRQ
void deactivateIRQ(uint32_t int_id)
Definition: gic_v3_distributor.cc:1175
gem5::Gicv3Distributor::GICD_SPENDSGIR
static const AddrRange GICD_SPENDSGIR
Definition: gic_v3_distributor.hh:131
gem5::Gicv3Distributor::GICD_PIDR3
@ GICD_PIDR3
Definition: gic_v3_distributor.hh:93
gic_v3.hh
gem5::Gicv3Distributor::irqPriority
std::vector< uint8_t > irqPriority
Definition: gic_v3_distributor.hh:162
gem5::Gicv3Distributor::IRM
Bitfield< 31 > IRM
Definition: gic_v3_distributor.hh:138
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Gicv3Distributor::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3_distributor.cc:1201

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