gem5  v21.1.0.2
Classes | Public Member Functions | Protected Types | Protected Member Functions | Protected Attributes | Static Protected Attributes | Friends | List of all members
gem5::Gicv3CPUInterface Class Referenceabstract

#include <gic_v3_cpu_interface.hh>

Inheritance diagram for gem5::Gicv3CPUInterface:
gem5::ArmISA::BaseISADevice gem5::Serializable

Classes

struct  hppi_t
 

Public Member Functions

 Gicv3CPUInterface (Gicv3 *gic, uint32_t cpu_id)
 
void init ()
 
RegVal readMiscReg (int misc_reg) override
 Read a system register belonging to this device. More...
 
void setMiscReg (int misc_reg, RegVal val) override
 Write to a system register belonging to this device. More...
 
void setThreadContext (ThreadContext *tc) override
 
- Public Member Functions inherited from gem5::ArmISA::BaseISADevice
 BaseISADevice ()
 
virtual ~BaseISADevice ()
 
virtual void setISA (ISA *isa)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 

Protected Types

enum  {
  GICC_CTLR = 0x0000, GICC_PMR = 0x0004, GICC_BPR = 0x0008, GICC_IAR = 0x000C,
  GICC_EOIR = 0x0010, GICC_RPR = 0x0014, GICC_HPPI = 0x0018, GICC_ABPR = 0x001C,
  GICC_AIAR = 0x0020, GICC_AEOIR = 0x0024, GICC_AHPPIR = 0x0028, GICC_STATUSR = 0x002C,
  GICC_IIDR = 0x00FC
}
 
enum  {
  GICH_HCR = 0x0000, GICH_VTR = 0x0004, GICH_VMCR = 0x0008, GICH_MISR = 0x0010,
  GICH_EISR = 0x0020, GICH_ELRSR = 0x0030
}
 

Protected Member Functions

 BitUnion64 (ICC_CTLR_EL1) Bitfield< 63
 
 EndBitUnion (ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63
 
 EndBitUnion (ICC_CTLR_EL3) BitUnion64(ICC_IGRPEN0_EL1) Bitfield< 63
 
 EndBitUnion (ICC_IGRPEN0_EL1) BitUnion64(ICC_IGRPEN1_EL1) Bitfield< 63
 
 EndBitUnion (ICC_IGRPEN1_EL1) BitUnion64(ICC_IGRPEN1_EL3) Bitfield< 63
 
 EndBitUnion (ICC_IGRPEN1_EL3) BitUnion64(ICC_SRE_EL1) Bitfield< 63
 
 EndBitUnion (ICC_SRE_EL1) BitUnion64(ICC_SRE_EL2) Bitfield< 63
 
 EndBitUnion (ICC_SRE_EL2) BitUnion64(ICC_SRE_EL3) Bitfield< 63
 
 EndBitUnion (ICC_SRE_EL3) static const uint8_t PRIORITY_BITS
 
 BitUnion64 (ICH_HCR_EL2) Bitfield< 63
 
 EndBitUnion (ICH_HCR_EL2) BitUnion64(ICH_LR_EL2) Bitfield< 63
 
 EndBitUnion (ICH_LR_EL2) static const uint64_t ICH_LR_EL2_STATE_INVALID=0
 
 BitUnion32 (ICH_LRC) Bitfield< 31
 
 EndBitUnion (ICH_LRC) BitUnion64(ICH_MISR_EL2) Bitfield< 63
 
 EndBitUnion (ICH_MISR_EL2) BitUnion64(ICH_VMCR_EL2) Bitfield< 63
 
 EndBitUnion (ICH_VMCR_EL2) BitUnion64(ICH_VTR_EL2) Bitfield< 63
 
 EndBitUnion (ICH_VTR_EL2) BitUnion64(ICV_CTLR_EL1) Bitfield< 63
 
EndBitUnion(ICV_CTLR_EL1) protected void generateSGI (RegVal val, Gicv3::GroupId group)
 
int currEL () const
 
void deactivateIRQ (uint32_t intid, Gicv3::GroupId group)
 
void dropPriority (Gicv3::GroupId group)
 
uint64_t eoiMaintenanceInterruptStatus () const
 
bool getHCREL2FMO () const
 
bool getHCREL2IMO () const
 
uint32_t getHPPIR0 () const
 
uint32_t getHPPIR1 () const
 
int getHPPVILR () const
 
bool groupEnabled (Gicv3::GroupId group) const
 
uint32_t groupPriorityMask (Gicv3::GroupId group)
 
bool haveEL (ArmISA::ExceptionLevel el) const
 
int highestActiveGroup () const
 
uint8_t highestActivePriority () const
 
bool hppiCanPreempt ()
 
bool hppviCanPreempt (int lrIdx) const
 
bool inSecureState () const
 
ArmISA::InterruptTypes intSignalType (Gicv3::GroupId group) const
 
bool isAA64 () const
 
bool isEL3OrMon () const
 
bool isEOISplitMode () const
 
bool isSecureBelowEL3 () const
 
ICH_MISR_EL2 maintenanceInterruptStatus () const
 
void resetHppi (uint32_t intid)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
void update ()
 
void updateDistributor ()
 
void virtualActivateIRQ (uint32_t lrIdx)
 
void virtualDeactivateIRQ (int lrIdx)
 
uint8_t virtualDropPriority ()
 
int virtualFindActive (uint32_t intid) const
 
uint32_t virtualGroupPriorityMask (Gicv3::GroupId group) const
 
uint8_t virtualHighestActivePriority () const
 
void virtualIncrementEOICount ()
 
bool virtualIsEOISplitMode () const
 
void virtualUpdate ()
 
RegVal bpr1 (Gicv3::GroupId group)
 
bool havePendingInterrupts (void) const
 
void clearPendingInterrupts (void)
 
void assertWakeRequest (void)
 
void deassertWakeRequest (void)
 
RegVal readBankedMiscReg (ArmISA::MiscRegIndex misc_reg) const
 
void setBankedMiscReg (ArmISA::MiscRegIndex misc_reg, RegVal val) const
 

Protected Attributes

Gicv3gic
 
Gicv3Redistributorredistributor
 
Gicv3Distributordistributor
 
uint32_t cpuId
 
ArmInterruptPinmaintenanceInterrupt
 
 res0_3
 
Bitfield< 19 > ExtRange
 
Bitfield< 18 > RSS
 
Bitfield< 17, 16 > res0_2
 
Bitfield< 15 > A3V
 
Bitfield< 14 > SEIS
 
Bitfield< 13, 11 > IDbits
 
Bitfield< 10, 8 > PRIbits
 
Bitfield< 7 > res0_1
 
Bitfield< 6 > PMHE
 
Bitfield< 5, 2 > res0_0
 
Bitfield< 1 > EOImode
 
Bitfield< 0 > CBPR
 
 res0_2
 
Bitfield< 17 > nDS
 
Bitfield< 16 > res0_1
 
Bitfield< 7 > res0_0
 
Bitfield< 5 > RM
 
Bitfield< 4 > EOImode_EL1NS
 
Bitfield< 3 > EOImode_EL1S
 
Bitfield< 2 > EOImode_EL3
 
Bitfield< 1 > CBPR_EL1NS
 
Bitfield< 0 > CBPR_EL1S
 
 res0
 
Bitfield< 0 > Enable
 
Bitfield< 1 > EnableGrp1S
 
Bitfield< 0 > EnableGrp1NS
 
Bitfield< 2 > DIB
 
Bitfield< 1 > DFB
 
Bitfield< 0 > SRE
 
Bitfield< 3 > Enable
 
hppi_t hppi
 
Bitfield< 31, 27 > EOIcount
 
Bitfield< 26, 15 > res0_1
 
Bitfield< 14 > TDIR
 
Bitfield< 13 > TSEI
 
Bitfield< 12 > TALL1
 
Bitfield< 11 > TALL0
 
Bitfield< 10 > TC
 
Bitfield< 9, 8 > res0_0
 
Bitfield< 7 > VGrp1DIE
 
Bitfield< 6 > VGrp1EIE
 
Bitfield< 5 > VGrp0DIE
 
Bitfield< 4 > VGrp0EIE
 
Bitfield< 3 > NPIE
 
Bitfield< 2 > LRENPIE
 
Bitfield< 1 > UIE
 
Bitfield< 0 > En
 
 State
 
Bitfield< 61 > HW
 
Bitfield< 60 > Group
 
Bitfield< 59, 56 > res0_1
 
Bitfield< 55, 48 > Priority
 
Bitfield< 47, 45 > res0_0
 
Bitfield< 44, 32 > pINTID
 
Bitfield< 41 > EOI
 
Bitfield< 31, 0 > vINTID
 
Bitfield< 29 > HW
 
Bitfield< 28 > Group
 
Bitfield< 27, 24 > res0_1
 
Bitfield< 23, 16 > Priority
 
Bitfield< 15, 13 > res0_0
 
Bitfield< 12, 0 > pINTID
 
Bitfield< 9 > EOI
 
Bitfield< 7 > VGrp1D
 
Bitfield< 6 > VGrp1E
 
Bitfield< 5 > VGrp0D
 
Bitfield< 4 > VGrp0E
 
Bitfield< 3 > NP
 
Bitfield< 2 > LRENP
 
Bitfield< 1 > U
 
Bitfield< 0 > EOI
 
Bitfield< 31, 24 > VPMR
 
Bitfield< 23, 21 > VBPR0
 
Bitfield< 20, 18 > VBPR1
 
Bitfield< 17, 10 > res0_1
 
Bitfield< 9 > VEOIM
 
Bitfield< 8, 5 > res0_0
 
Bitfield< 4 > VCBPR
 
Bitfield< 3 > VFIQEn
 
Bitfield< 2 > VAckCtl
 
Bitfield< 1 > VENG1
 
Bitfield< 0 > VENG0
 
 res0_1
 
Bitfield< 31, 29 > PRIbits
 
Bitfield< 28, 26 > PREbits
 
Bitfield< 25, 23 > IDbits
 
Bitfield< 22 > SEIS
 
Bitfield< 21 > A3V
 
Bitfield< 20 > res1
 
Bitfield< 19 > TDS
 
Bitfield< 18, 5 > res0_0
 
Bitfield< 4, 0 > ListRegs
 
Bitfield< 17, 16 > res0_1
 
Bitfield< 7, 2 > res0_0
 
- Protected Attributes inherited from gem5::ArmISA::BaseISADevice
ISAisa
 

Static Protected Attributes

static const uint8_t GIC_MIN_BPR = 2
 
static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1
 
static const uint8_t VIRTUAL_PRIORITY_BITS = 5
 
static const uint8_t VIRTUAL_PREEMPTION_BITS = 5
 
static const uint8_t VIRTUAL_NUM_LIST_REGS = 16
 
static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS
 
static const AddrRange GICC_APR
 
static const AddrRange GICC_NSAPR
 
static const AddrRange GICH_APR
 
static const AddrRange GICH_LR
 
static const uint64_t ICH_LR_EL2_STATE_PENDING = 1
 
static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2
 
static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3
 

Friends

class Gicv3Distributor
 
class Gicv3Redistributor
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 

Detailed Description

Definition at line 53 of file gic_v3_cpu_interface.hh.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum
protected
Enumerator
GICC_CTLR 
GICC_PMR 
GICC_BPR 
GICC_IAR 
GICC_EOIR 
GICC_RPR 
GICC_HPPI 
GICC_ABPR 
GICC_AIAR 
GICC_AEOIR 
GICC_AHPPIR 
GICC_STATUSR 
GICC_IIDR 

Definition at line 167 of file gic_v3_cpu_interface.hh.

◆ anonymous enum

anonymous enum
protected
Enumerator
GICH_HCR 
GICH_VTR 
GICH_VMCR 
GICH_MISR 
GICH_EISR 
GICH_ELRSR 

Definition at line 188 of file gic_v3_cpu_interface.hh.

Constructor & Destructor Documentation

◆ Gicv3CPUInterface()

gem5::Gicv3CPUInterface::Gicv3CPUInterface ( Gicv3 gic,
uint32_t  cpu_id 
)

Member Function Documentation

◆ assertWakeRequest()

void gem5::Gicv3CPUInterface::assertWakeRequest ( void  )
protected

◆ BitUnion32()

gem5::Gicv3CPUInterface::BitUnion32 ( ICH_LRC  )
protected

◆ BitUnion64() [1/2]

gem5::Gicv3CPUInterface::BitUnion64 ( ICC_CTLR_EL1  )
protected

◆ BitUnion64() [2/2]

gem5::Gicv3CPUInterface::BitUnion64 ( ICH_HCR_EL2  )
protected

◆ bpr1()

RegVal gem5::Gicv3CPUInterface::bpr1 ( Gicv3::GroupId  group)
protected

◆ clearPendingInterrupts()

void gem5::Gicv3CPUInterface::clearPendingInterrupts ( void  )
protected

◆ currEL()

int gem5::Gicv3CPUInterface::currEL ( ) const
protected

◆ deactivateIRQ()

void gem5::Gicv3CPUInterface::deactivateIRQ ( uint32_t  intid,
Gicv3::GroupId  group 
)
protected

◆ deassertWakeRequest()

void gem5::Gicv3CPUInterface::deassertWakeRequest ( void  )
protected

◆ dropPriority()

void gem5::Gicv3CPUInterface::dropPriority ( Gicv3::GroupId  group)
protected

◆ EndBitUnion() [1/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_CTLR_EL1  )
protected

◆ EndBitUnion() [2/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_CTLR_EL3  )
protected

◆ EndBitUnion() [3/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_IGRPEN0_EL1  )
protected

◆ EndBitUnion() [4/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_IGRPEN1_EL1  )
protected

◆ EndBitUnion() [5/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_IGRPEN1_EL3  )
protected

◆ EndBitUnion() [6/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_SRE_EL1  )
protected

◆ EndBitUnion() [7/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_SRE_EL2  )
protected

◆ EndBitUnion() [8/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_SRE_EL3  ) const
protected

◆ EndBitUnion() [9/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICH_HCR_EL2  )
protected

◆ EndBitUnion() [10/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICH_LR_EL2  ) const
protectedpure virtual

◆ EndBitUnion() [11/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICH_LRC  )
protected

◆ EndBitUnion() [12/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICH_MISR_EL2  )
protected

◆ EndBitUnion() [13/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICH_VMCR_EL2  )
protected

◆ EndBitUnion() [14/14]

gem5::Gicv3CPUInterface::EndBitUnion ( ICH_VTR_EL2  )
protected

◆ eoiMaintenanceInterruptStatus()

uint64_t gem5::Gicv3CPUInterface::eoiMaintenanceInterruptStatus ( ) const
protected

◆ generateSGI()

void gem5::Gicv3CPUInterface::generateSGI ( RegVal  val,
Gicv3::GroupId  group 
)
protected

◆ getHCREL2FMO()

bool gem5::Gicv3CPUInterface::getHCREL2FMO ( ) const
protected

◆ getHCREL2IMO()

bool gem5::Gicv3CPUInterface::getHCREL2IMO ( ) const
protected

◆ getHPPIR0()

uint32_t gem5::Gicv3CPUInterface::getHPPIR0 ( ) const
protected

◆ getHPPIR1()

uint32_t gem5::Gicv3CPUInterface::getHPPIR1 ( ) const
protected

◆ getHPPVILR()

int gem5::Gicv3CPUInterface::getHPPVILR ( ) const
protected

◆ groupEnabled()

bool gem5::Gicv3CPUInterface::groupEnabled ( Gicv3::GroupId  group) const
protected

◆ groupPriorityMask()

uint32_t gem5::Gicv3CPUInterface::groupPriorityMask ( Gicv3::GroupId  group)
protected

◆ haveEL()

bool gem5::Gicv3CPUInterface::haveEL ( ArmISA::ExceptionLevel  el) const
protected

◆ havePendingInterrupts()

bool gem5::Gicv3CPUInterface::havePendingInterrupts ( void  ) const
protected

◆ highestActiveGroup()

int gem5::Gicv3CPUInterface::highestActiveGroup ( ) const
protected

◆ highestActivePriority()

uint8_t gem5::Gicv3CPUInterface::highestActivePriority ( ) const
protected

◆ hppiCanPreempt()

bool gem5::Gicv3CPUInterface::hppiCanPreempt ( )
protected

◆ hppviCanPreempt()

bool gem5::Gicv3CPUInterface::hppviCanPreempt ( int  lrIdx) const
protected

◆ init()

void gem5::Gicv3CPUInterface::init ( )

◆ inSecureState()

bool gem5::Gicv3CPUInterface::inSecureState ( ) const
protected

◆ intSignalType()

InterruptTypes gem5::Gicv3CPUInterface::intSignalType ( Gicv3::GroupId  group) const
protected

◆ isAA64()

bool gem5::Gicv3CPUInterface::isAA64 ( ) const
protected

◆ isEL3OrMon()

bool gem5::Gicv3CPUInterface::isEL3OrMon ( ) const
protected

◆ isEOISplitMode()

bool gem5::Gicv3CPUInterface::isEOISplitMode ( ) const
protected

◆ isSecureBelowEL3()

bool gem5::Gicv3CPUInterface::isSecureBelowEL3 ( ) const
protected

◆ maintenanceInterruptStatus()

Gicv3CPUInterface::ICH_MISR_EL2 gem5::Gicv3CPUInterface::maintenanceInterruptStatus ( ) const
protected

◆ readBankedMiscReg()

RegVal gem5::Gicv3CPUInterface::readBankedMiscReg ( ArmISA::MiscRegIndex  misc_reg) const
protected

◆ readMiscReg()

RegVal gem5::Gicv3CPUInterface::readMiscReg ( int  misc_reg)
overridevirtual

Read a system register belonging to this device.

Parameters
misc_regRegister number (see regs/misc.hh)
Returns
Register value.

Implements gem5::ArmISA::BaseISADevice.

Definition at line 120 of file gic_v3_cpu_interface.cc.

References bpr1(), currEL(), DPRINTF, gem5::ArmISA::EL1, gem5::ArmISA::EL3, Enable, eoiMaintenanceInterruptStatus(), gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, getHCREL2FMO(), getHCREL2IMO(), getHPPIR0(), getHPPIR1(), getHPPVILR(), gem5::Gicv3CPUInterface::hppi_t::group, haveEL(), highestActivePriority(), hppi, hppiCanPreempt(), hppviCanPreempt(), inSecureState(), gem5::Gicv3::INTID_SECURE, gem5::Gicv3::INTID_SPURIOUS, gem5::ArmISA::BaseISADevice::isa, isSecureBelowEL3(), maintenanceInterruptStatus(), gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP0R1, gem5::ArmISA::MISCREG_ICC_AP0R1_EL1, gem5::ArmISA::MISCREG_ICC_AP0R2, gem5::ArmISA::MISCREG_ICC_AP0R2_EL1, gem5::ArmISA::MISCREG_ICC_AP0R3, gem5::ArmISA::MISCREG_ICC_AP0R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1, gem5::ArmISA::MISCREG_ICC_AP1R2, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1, gem5::ArmISA::MISCREG_ICC_AP1R3, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1, gem5::ArmISA::MISCREG_ICC_BPR0, gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_BPR1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1, gem5::ArmISA::MISCREG_ICC_CTLR, gem5::ArmISA::MISCREG_ICC_CTLR_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL3, gem5::ArmISA::MISCREG_ICC_HPPIR0, gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1, gem5::ArmISA::MISCREG_ICC_HPPIR1, gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1, gem5::ArmISA::MISCREG_ICC_HSRE, gem5::ArmISA::MISCREG_ICC_IAR0, gem5::ArmISA::MISCREG_ICC_IAR0_EL1, gem5::ArmISA::MISCREG_ICC_IAR1, gem5::ArmISA::MISCREG_ICC_IAR1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN0, gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3, gem5::ArmISA::MISCREG_ICC_MCTLR, gem5::ArmISA::MISCREG_ICC_MGRPEN1, gem5::ArmISA::MISCREG_ICC_MSRE, gem5::ArmISA::MISCREG_ICC_PMR, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICC_RPR, gem5::ArmISA::MISCREG_ICC_RPR_EL1, gem5::ArmISA::MISCREG_ICC_SRE, gem5::ArmISA::MISCREG_ICC_SRE_EL1, gem5::ArmISA::MISCREG_ICC_SRE_EL2, gem5::ArmISA::MISCREG_ICC_SRE_EL3, gem5::ArmISA::MISCREG_ICH_AP0R0, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP0R1, gem5::ArmISA::MISCREG_ICH_AP0R1_EL2, gem5::ArmISA::MISCREG_ICH_AP0R2, gem5::ArmISA::MISCREG_ICH_AP0R2_EL2, gem5::ArmISA::MISCREG_ICH_AP0R3, gem5::ArmISA::MISCREG_ICH_AP0R3_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R1, gem5::ArmISA::MISCREG_ICH_AP1R1_EL2, gem5::ArmISA::MISCREG_ICH_AP1R2, gem5::ArmISA::MISCREG_ICH_AP1R2_EL2, gem5::ArmISA::MISCREG_ICH_AP1R3, gem5::ArmISA::MISCREG_ICH_AP1R3_EL2, gem5::ArmISA::MISCREG_ICH_EISR, gem5::ArmISA::MISCREG_ICH_EISR_EL2, gem5::ArmISA::MISCREG_ICH_ELRSR, gem5::ArmISA::MISCREG_ICH_ELRSR_EL2, gem5::ArmISA::MISCREG_ICH_HCR, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_LR15, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICH_LRC0, gem5::ArmISA::MISCREG_ICH_LRC15, gem5::ArmISA::MISCREG_ICH_MISR, gem5::ArmISA::MISCREG_ICH_MISR_EL2, gem5::ArmISA::MISCREG_ICH_VMCR, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::MISCREG_ICH_VTR, gem5::ArmISA::MISCREG_ICH_VTR_EL2, gem5::ArmISA::MISCREG_ICV_AP0R0_EL1, gem5::ArmISA::MISCREG_ICV_AP1R0_EL1, gem5::ArmISA::MISCREG_ICV_BPR0_EL1, gem5::ArmISA::MISCREG_ICV_BPR1_EL1, gem5::ArmISA::MISCREG_ICV_CTLR_EL1, gem5::ArmISA::MISCREG_ICV_HPPIR0_EL1, gem5::ArmISA::MISCREG_ICV_HPPIR1_EL1, gem5::ArmISA::MISCREG_ICV_IAR0_EL1, gem5::ArmISA::MISCREG_ICV_IAR1_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICV_PMR_EL1, gem5::ArmISA::MISCREG_ICV_RPR_EL1, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::miscRegName, panic, readBankedMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::Gicv3Redistributor::SMALLEST_LPI_ID, U, VIRTUAL_NUM_LIST_REGS, VIRTUAL_PREEMPTION_BITS, VIRTUAL_PRIORITY_BITS, virtualActivateIRQ(), virtualHighestActivePriority(), and virtualUpdate().

Referenced by bpr1(), and groupPriorityMask().

◆ resetHppi()

void gem5::Gicv3CPUInterface::resetHppi ( uint32_t  intid)
protected

◆ serialize()

void gem5::Gicv3CPUInterface::serialize ( CheckpointOut cp) const
overrideprotectedvirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 2615 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3CPUInterface::hppi_t::group, hppi, gem5::Gicv3CPUInterface::hppi_t::intid, gem5::Gicv3CPUInterface::hppi_t::prio, SERIALIZE_ENUM, and SERIALIZE_SCALAR.

◆ setBankedMiscReg()

void gem5::Gicv3CPUInterface::setBankedMiscReg ( ArmISA::MiscRegIndex  misc_reg,
RegVal  val 
) const
protected

◆ setMiscReg()

void gem5::Gicv3CPUInterface::setMiscReg ( int  misc_reg,
RegVal  val 
)
overridevirtual

Write to a system register belonging to this device.

Parameters
misc_regRegister number (see regs/misc.hh)
valValue to store

Implements gem5::ArmISA::BaseISADevice.

Definition at line 740 of file gic_v3_cpu_interface.cc.

References currEL(), deactivateIRQ(), distributor, DPRINTF, dropPriority(), gem5::Gicv3Distributor::DS, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::X86ISA::enable, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, generateSGI(), getHCREL2FMO(), getHCREL2IMO(), gem5::Gicv3Distributor::getIntGroup(), gem5::Gicv3Redistributor::getIntGroup(), GIC_MIN_BPR, GIC_MIN_BPR_NS, haveEL(), highestActiveGroup(), inSecureState(), gem5::Gicv3::INTID_SECURE, gem5::Gicv3::INTID_SPURIOUS, gem5::ArmISA::BaseISADevice::isa, isEL3OrMon(), isEOISplitMode(), isSecureBelowEL3(), gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP0R1, gem5::ArmISA::MISCREG_ICC_AP0R1_EL1, gem5::ArmISA::MISCREG_ICC_AP0R2, gem5::ArmISA::MISCREG_ICC_AP0R2_EL1, gem5::ArmISA::MISCREG_ICC_AP0R3, gem5::ArmISA::MISCREG_ICC_AP0R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1, gem5::ArmISA::MISCREG_ICC_AP1R2, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1, gem5::ArmISA::MISCREG_ICC_AP1R3, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1, gem5::ArmISA::MISCREG_ICC_ASGI1R, gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1, gem5::ArmISA::MISCREG_ICC_BPR0, gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_BPR1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR, gem5::ArmISA::MISCREG_ICC_CTLR_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR_EL3, gem5::ArmISA::MISCREG_ICC_DIR, gem5::ArmISA::MISCREG_ICC_DIR_EL1, gem5::ArmISA::MISCREG_ICC_EOIR0, gem5::ArmISA::MISCREG_ICC_EOIR0_EL1, gem5::ArmISA::MISCREG_ICC_EOIR1, gem5::ArmISA::MISCREG_ICC_EOIR1_EL1, gem5::ArmISA::MISCREG_ICC_HSRE, gem5::ArmISA::MISCREG_ICC_IGRPEN0, gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3, gem5::ArmISA::MISCREG_ICC_MCTLR, gem5::ArmISA::MISCREG_ICC_MGRPEN1, gem5::ArmISA::MISCREG_ICC_MSRE, gem5::ArmISA::MISCREG_ICC_PMR, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICC_SGI0R, gem5::ArmISA::MISCREG_ICC_SGI0R_EL1, gem5::ArmISA::MISCREG_ICC_SGI1R, gem5::ArmISA::MISCREG_ICC_SGI1R_EL1, gem5::ArmISA::MISCREG_ICC_SRE, gem5::ArmISA::MISCREG_ICC_SRE_EL1, gem5::ArmISA::MISCREG_ICC_SRE_EL2, gem5::ArmISA::MISCREG_ICC_SRE_EL3, gem5::ArmISA::MISCREG_ICH_AP0R0, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP0R1, gem5::ArmISA::MISCREG_ICH_AP0R1_EL2, gem5::ArmISA::MISCREG_ICH_AP0R2, gem5::ArmISA::MISCREG_ICH_AP0R2_EL2, gem5::ArmISA::MISCREG_ICH_AP0R3, gem5::ArmISA::MISCREG_ICH_AP0R3_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R1, gem5::ArmISA::MISCREG_ICH_AP1R1_EL2, gem5::ArmISA::MISCREG_ICH_AP1R2, gem5::ArmISA::MISCREG_ICH_AP1R2_EL2, gem5::ArmISA::MISCREG_ICH_AP1R3, gem5::ArmISA::MISCREG_ICH_AP1R3_EL2, gem5::ArmISA::MISCREG_ICH_HCR, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_LR15, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICH_LRC0, gem5::ArmISA::MISCREG_ICH_LRC15, gem5::ArmISA::MISCREG_ICH_VMCR, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::MISCREG_ICV_AP0R0_EL1, gem5::ArmISA::MISCREG_ICV_AP1R0_EL1, gem5::ArmISA::MISCREG_ICV_BPR0_EL1, gem5::ArmISA::MISCREG_ICV_BPR1_EL1, gem5::ArmISA::MISCREG_ICV_CTLR_EL1, gem5::ArmISA::MISCREG_ICV_DIR_EL1, gem5::ArmISA::MISCREG_ICV_EOIR0_EL1, gem5::ArmISA::MISCREG_ICV_EOIR1_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICV_PMR_EL1, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::miscRegName, panic, readBankedMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), redistributor, setBankedMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), U, updateDistributor(), gem5::X86ISA::val, VIRTUAL_PREEMPTION_BITS, virtualDeactivateIRQ(), virtualDropPriority(), virtualFindActive(), virtualIncrementEOICount(), virtualIsEOISplitMode(), and virtualUpdate().

◆ setThreadContext()

void gem5::Gicv3CPUInterface::setThreadContext ( ThreadContext tc)
overridevirtual

◆ unserialize()

void gem5::Gicv3CPUInterface::unserialize ( CheckpointIn cp)
overrideprotectedvirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 2623 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3CPUInterface::hppi_t::group, hppi, gem5::Gicv3CPUInterface::hppi_t::intid, gem5::Gicv3CPUInterface::hppi_t::prio, UNSERIALIZE_ENUM, and UNSERIALIZE_SCALAR.

◆ update()

void gem5::Gicv3CPUInterface::update ( )
protected

◆ updateDistributor()

void gem5::Gicv3CPUInterface::updateDistributor ( )
protected

Definition at line 2027 of file gic_v3_cpu_interface.cc.

References distributor, and gem5::Gicv3Distributor::update().

Referenced by deactivateIRQ(), and setMiscReg().

◆ virtualActivateIRQ()

void gem5::Gicv3CPUInterface::virtualActivateIRQ ( uint32_t  lrIdx)
protected

◆ virtualDeactivateIRQ()

void gem5::Gicv3CPUInterface::virtualDeactivateIRQ ( int  lrIdx)
protected

◆ virtualDropPriority()

uint8_t gem5::Gicv3CPUInterface::virtualDropPriority ( )
protected

◆ virtualFindActive()

int gem5::Gicv3CPUInterface::virtualFindActive ( uint32_t  intid) const
protected

◆ virtualGroupPriorityMask()

uint32_t gem5::Gicv3CPUInterface::virtualGroupPriorityMask ( Gicv3::GroupId  group) const
protected

◆ virtualHighestActivePriority()

uint8_t gem5::Gicv3CPUInterface::virtualHighestActivePriority ( ) const
protected

◆ virtualIncrementEOICount()

void gem5::Gicv3CPUInterface::virtualIncrementEOICount ( )
protected

◆ virtualIsEOISplitMode()

bool gem5::Gicv3CPUInterface::virtualIsEOISplitMode ( ) const
protected

◆ virtualUpdate()

void gem5::Gicv3CPUInterface::virtualUpdate ( )
protected

Friends And Related Function Documentation

◆ Gicv3Distributor

friend class Gicv3Distributor
friend

Definition at line 57 of file gic_v3_cpu_interface.hh.

◆ Gicv3Redistributor

friend class Gicv3Redistributor
friend

Definition at line 58 of file gic_v3_cpu_interface.hh.

Member Data Documentation

◆ A3V [1/2]

Bitfield< 15 > gem5::Gicv3CPUInterface::A3V
protected

Definition at line 74 of file gic_v3_cpu_interface.hh.

◆ A3V [2/2]

Bitfield<21> gem5::Gicv3CPUInterface::A3V
protected

Definition at line 282 of file gic_v3_cpu_interface.hh.

◆ CBPR

Bitfield< 0 > gem5::Gicv3CPUInterface::CBPR
protected

Definition at line 82 of file gic_v3_cpu_interface.hh.

◆ CBPR_EL1NS

Bitfield<1> gem5::Gicv3CPUInterface::CBPR_EL1NS
protected

Definition at line 101 of file gic_v3_cpu_interface.hh.

◆ CBPR_EL1S

Bitfield<0> gem5::Gicv3CPUInterface::CBPR_EL1S
protected

Definition at line 102 of file gic_v3_cpu_interface.hh.

◆ cpuId

uint32_t gem5::Gicv3CPUInterface::cpuId
protected

◆ DFB

Bitfield< 1 > gem5::Gicv3CPUInterface::DFB
protected

Definition at line 124 of file gic_v3_cpu_interface.hh.

◆ DIB

Bitfield< 2 > gem5::Gicv3CPUInterface::DIB
protected

Definition at line 123 of file gic_v3_cpu_interface.hh.

◆ distributor

Gicv3Distributor* gem5::Gicv3CPUInterface::distributor
protected

◆ En

Bitfield<0> gem5::Gicv3CPUInterface::En
protected

Definition at line 218 of file gic_v3_cpu_interface.hh.

◆ Enable [1/2]

Bitfield< 3 > gem5::Gicv3CPUInterface::Enable
protected

Definition at line 107 of file gic_v3_cpu_interface.hh.

Referenced by readMiscReg().

◆ Enable [2/2]

Bitfield<3> gem5::Gicv3CPUInterface::Enable
protected

Definition at line 130 of file gic_v3_cpu_interface.hh.

◆ EnableGrp1NS

Bitfield<0> gem5::Gicv3CPUInterface::EnableGrp1NS
protected

Definition at line 118 of file gic_v3_cpu_interface.hh.

◆ EnableGrp1S

Bitfield<1> gem5::Gicv3CPUInterface::EnableGrp1S
protected

Definition at line 117 of file gic_v3_cpu_interface.hh.

◆ EOI [1/3]

Bitfield<41> gem5::Gicv3CPUInterface::EOI
protected

Definition at line 229 of file gic_v3_cpu_interface.hh.

◆ EOI [2/3]

Bitfield<9> gem5::Gicv3CPUInterface::EOI
protected

Definition at line 246 of file gic_v3_cpu_interface.hh.

◆ EOI [3/3]

Bitfield<0> gem5::Gicv3CPUInterface::EOI
protected

Definition at line 258 of file gic_v3_cpu_interface.hh.

◆ EOIcount

Bitfield<31, 27> gem5::Gicv3CPUInterface::EOIcount
protected

Definition at line 203 of file gic_v3_cpu_interface.hh.

◆ EOImode

Bitfield< 1 > gem5::Gicv3CPUInterface::EOImode
protected

Definition at line 81 of file gic_v3_cpu_interface.hh.

◆ EOImode_EL1NS

Bitfield<4> gem5::Gicv3CPUInterface::EOImode_EL1NS
protected

Definition at line 98 of file gic_v3_cpu_interface.hh.

◆ EOImode_EL1S

Bitfield<3> gem5::Gicv3CPUInterface::EOImode_EL1S
protected

Definition at line 99 of file gic_v3_cpu_interface.hh.

◆ EOImode_EL3

Bitfield<2> gem5::Gicv3CPUInterface::EOImode_EL3
protected

Definition at line 100 of file gic_v3_cpu_interface.hh.

◆ ExtRange

Bitfield< 19 > gem5::Gicv3CPUInterface::ExtRange
protected

Definition at line 71 of file gic_v3_cpu_interface.hh.

◆ gic

Gicv3* gem5::Gicv3CPUInterface::gic
protected

◆ GIC_MIN_BPR

const uint8_t gem5::Gicv3CPUInterface::GIC_MIN_BPR = 2
staticprotected

Definition at line 147 of file gic_v3_cpu_interface.hh.

Referenced by bpr1(), highestActivePriority(), and setMiscReg().

◆ GIC_MIN_BPR_NS

const uint8_t gem5::Gicv3CPUInterface::GIC_MIN_BPR_NS = GIC_MIN_BPR + 1
staticprotected

Definition at line 149 of file gic_v3_cpu_interface.hh.

Referenced by bpr1(), and setMiscReg().

◆ GIC_MIN_VBPR

const uint8_t gem5::Gicv3CPUInterface::GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS
staticprotected

Definition at line 155 of file gic_v3_cpu_interface.hh.

Referenced by virtualDropPriority(), and virtualHighestActivePriority().

◆ GICC_APR

const AddrRange gem5::Gicv3CPUInterface::GICC_APR
staticprotected

Definition at line 184 of file gic_v3_cpu_interface.hh.

◆ GICC_NSAPR

const AddrRange gem5::Gicv3CPUInterface::GICC_NSAPR
staticprotected

Definition at line 185 of file gic_v3_cpu_interface.hh.

◆ GICH_APR

const AddrRange gem5::Gicv3CPUInterface::GICH_APR
staticprotected

Definition at line 198 of file gic_v3_cpu_interface.hh.

◆ GICH_LR

const AddrRange gem5::Gicv3CPUInterface::GICH_LR
staticprotected

Definition at line 199 of file gic_v3_cpu_interface.hh.

◆ Group [1/2]

Bitfield<60> gem5::Gicv3CPUInterface::Group
protected

Definition at line 224 of file gic_v3_cpu_interface.hh.

◆ Group [2/2]

Bitfield<28> gem5::Gicv3CPUInterface::Group
protected

Definition at line 241 of file gic_v3_cpu_interface.hh.

◆ hppi

hppi_t gem5::Gicv3CPUInterface::hppi
protected

◆ HW [1/2]

Bitfield<61> gem5::Gicv3CPUInterface::HW
protected

Definition at line 223 of file gic_v3_cpu_interface.hh.

◆ HW [2/2]

Bitfield<29> gem5::Gicv3CPUInterface::HW
protected

Definition at line 240 of file gic_v3_cpu_interface.hh.

◆ ICH_LR_EL2_STATE_ACTIVE

const uint64_t gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE = 2
staticprotected

◆ ICH_LR_EL2_STATE_ACTIVE_PENDING

const uint64_t gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE_PENDING = 3
staticprotected

Definition at line 236 of file gic_v3_cpu_interface.hh.

Referenced by virtualFindActive().

◆ ICH_LR_EL2_STATE_PENDING

const uint64_t gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_PENDING = 1
staticprotected

Definition at line 234 of file gic_v3_cpu_interface.hh.

Referenced by maintenanceInterruptStatus().

◆ IDbits [1/2]

Bitfield< 13, 11 > gem5::Gicv3CPUInterface::IDbits
protected

Definition at line 76 of file gic_v3_cpu_interface.hh.

◆ IDbits [2/2]

Bitfield<25, 23> gem5::Gicv3CPUInterface::IDbits
protected

Definition at line 280 of file gic_v3_cpu_interface.hh.

◆ ListRegs

Bitfield<4, 0> gem5::Gicv3CPUInterface::ListRegs
protected

Definition at line 286 of file gic_v3_cpu_interface.hh.

◆ LRENP

Bitfield<2> gem5::Gicv3CPUInterface::LRENP
protected

Definition at line 256 of file gic_v3_cpu_interface.hh.

◆ LRENPIE

Bitfield<2> gem5::Gicv3CPUInterface::LRENPIE
protected

Definition at line 216 of file gic_v3_cpu_interface.hh.

◆ maintenanceInterrupt

ArmInterruptPin* gem5::Gicv3CPUInterface::maintenanceInterrupt
protected

Definition at line 67 of file gic_v3_cpu_interface.hh.

Referenced by setThreadContext(), and virtualUpdate().

◆ nDS

Bitfield<17> gem5::Gicv3CPUInterface::nDS
protected

Definition at line 89 of file gic_v3_cpu_interface.hh.

◆ NP

Bitfield<3> gem5::Gicv3CPUInterface::NP
protected

Definition at line 255 of file gic_v3_cpu_interface.hh.

◆ NPIE

Bitfield<3> gem5::Gicv3CPUInterface::NPIE
protected

Definition at line 215 of file gic_v3_cpu_interface.hh.

◆ pINTID [1/2]

Bitfield<44, 32> gem5::Gicv3CPUInterface::pINTID
protected

Definition at line 228 of file gic_v3_cpu_interface.hh.

◆ pINTID [2/2]

Bitfield<12, 0> gem5::Gicv3CPUInterface::pINTID
protected

Definition at line 245 of file gic_v3_cpu_interface.hh.

◆ PMHE

Bitfield< 6 > gem5::Gicv3CPUInterface::PMHE
protected

Definition at line 79 of file gic_v3_cpu_interface.hh.

◆ PREbits

Bitfield<28, 26> gem5::Gicv3CPUInterface::PREbits
protected

Definition at line 279 of file gic_v3_cpu_interface.hh.

◆ PRIbits [1/2]

Bitfield< 10, 8 > gem5::Gicv3CPUInterface::PRIbits
protected

Definition at line 77 of file gic_v3_cpu_interface.hh.

◆ PRIbits [2/2]

Bitfield<31, 29> gem5::Gicv3CPUInterface::PRIbits
protected

Definition at line 278 of file gic_v3_cpu_interface.hh.

◆ Priority [1/2]

Bitfield<55, 48> gem5::Gicv3CPUInterface::Priority
protected

Definition at line 226 of file gic_v3_cpu_interface.hh.

◆ Priority [2/2]

Bitfield<23, 16> gem5::Gicv3CPUInterface::Priority
protected

Definition at line 243 of file gic_v3_cpu_interface.hh.

◆ redistributor

Gicv3Redistributor* gem5::Gicv3CPUInterface::redistributor
protected

◆ res0

gem5::Gicv3CPUInterface::res0
protected

Definition at line 106 of file gic_v3_cpu_interface.hh.

◆ res0_0 [1/8]

Bitfield<5, 2> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 80 of file gic_v3_cpu_interface.hh.

◆ res0_0 [2/8]

Bitfield<7> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 95 of file gic_v3_cpu_interface.hh.

◆ res0_0 [3/8]

Bitfield<9, 8> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 210 of file gic_v3_cpu_interface.hh.

◆ res0_0 [4/8]

Bitfield<47, 45> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 227 of file gic_v3_cpu_interface.hh.

◆ res0_0 [5/8]

Bitfield<15, 13> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 244 of file gic_v3_cpu_interface.hh.

◆ res0_0 [6/8]

Bitfield<8, 5> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 268 of file gic_v3_cpu_interface.hh.

◆ res0_0 [7/8]

Bitfield<18, 5> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 285 of file gic_v3_cpu_interface.hh.

◆ res0_0 [8/8]

Bitfield<7, 2> gem5::Gicv3CPUInterface::res0_0
protected

Definition at line 297 of file gic_v3_cpu_interface.hh.

◆ res0_1 [1/8]

Bitfield<7> gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 78 of file gic_v3_cpu_interface.hh.

◆ res0_1 [2/8]

Bitfield<16> gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 90 of file gic_v3_cpu_interface.hh.

◆ res0_1 [3/8]

Bitfield<26, 15> gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 204 of file gic_v3_cpu_interface.hh.

◆ res0_1 [4/8]

Bitfield<59, 56> gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 225 of file gic_v3_cpu_interface.hh.

◆ res0_1 [5/8]

Bitfield<27, 24> gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 242 of file gic_v3_cpu_interface.hh.

◆ res0_1 [6/8]

Bitfield<17, 10> gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 266 of file gic_v3_cpu_interface.hh.

◆ res0_1 [7/8]

gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 277 of file gic_v3_cpu_interface.hh.

◆ res0_1 [8/8]

Bitfield<17, 16> gem5::Gicv3CPUInterface::res0_1
protected

Definition at line 292 of file gic_v3_cpu_interface.hh.

◆ res0_2 [1/2]

Bitfield<17, 16> gem5::Gicv3CPUInterface::res0_2
protected

Definition at line 73 of file gic_v3_cpu_interface.hh.

◆ res0_2 [2/2]

gem5::Gicv3CPUInterface::res0_2
protected

Definition at line 86 of file gic_v3_cpu_interface.hh.

◆ res0_3

gem5::Gicv3CPUInterface::res0_3
protected

Definition at line 70 of file gic_v3_cpu_interface.hh.

◆ res1

Bitfield<20> gem5::Gicv3CPUInterface::res1
protected

Definition at line 283 of file gic_v3_cpu_interface.hh.

◆ RM

Bitfield<5> gem5::Gicv3CPUInterface::RM
protected

Definition at line 97 of file gic_v3_cpu_interface.hh.

◆ RSS

Bitfield< 18 > gem5::Gicv3CPUInterface::RSS
protected

Definition at line 72 of file gic_v3_cpu_interface.hh.

◆ SEIS [1/2]

Bitfield< 14 > gem5::Gicv3CPUInterface::SEIS
protected

Definition at line 75 of file gic_v3_cpu_interface.hh.

◆ SEIS [2/2]

Bitfield<22> gem5::Gicv3CPUInterface::SEIS
protected

Definition at line 281 of file gic_v3_cpu_interface.hh.

◆ SRE

Bitfield< 0 > gem5::Gicv3CPUInterface::SRE
protected

Definition at line 125 of file gic_v3_cpu_interface.hh.

◆ State

gem5::Gicv3CPUInterface::State
protected

Definition at line 222 of file gic_v3_cpu_interface.hh.

◆ TALL0

Bitfield<11> gem5::Gicv3CPUInterface::TALL0
protected

Definition at line 208 of file gic_v3_cpu_interface.hh.

◆ TALL1

Bitfield<12> gem5::Gicv3CPUInterface::TALL1
protected

Definition at line 207 of file gic_v3_cpu_interface.hh.

◆ TC

Bitfield<10> gem5::Gicv3CPUInterface::TC
protected

Definition at line 209 of file gic_v3_cpu_interface.hh.

◆ TDIR

Bitfield<14> gem5::Gicv3CPUInterface::TDIR
protected

Definition at line 205 of file gic_v3_cpu_interface.hh.

◆ TDS

Bitfield<19> gem5::Gicv3CPUInterface::TDS
protected

Definition at line 284 of file gic_v3_cpu_interface.hh.

◆ TSEI

Bitfield<13> gem5::Gicv3CPUInterface::TSEI
protected

Definition at line 206 of file gic_v3_cpu_interface.hh.

◆ U

Bitfield<1> gem5::Gicv3CPUInterface::U
protected

◆ UIE

Bitfield<1> gem5::Gicv3CPUInterface::UIE
protected

Definition at line 217 of file gic_v3_cpu_interface.hh.

◆ VAckCtl

Bitfield<2> gem5::Gicv3CPUInterface::VAckCtl
protected

Definition at line 271 of file gic_v3_cpu_interface.hh.

◆ VBPR0

Bitfield<23, 21> gem5::Gicv3CPUInterface::VBPR0
protected

Definition at line 264 of file gic_v3_cpu_interface.hh.

◆ VBPR1

Bitfield<20, 18> gem5::Gicv3CPUInterface::VBPR1
protected

Definition at line 265 of file gic_v3_cpu_interface.hh.

◆ VCBPR

Bitfield<4> gem5::Gicv3CPUInterface::VCBPR
protected

Definition at line 269 of file gic_v3_cpu_interface.hh.

◆ VENG0

Bitfield<0> gem5::Gicv3CPUInterface::VENG0
protected

Definition at line 273 of file gic_v3_cpu_interface.hh.

◆ VENG1

Bitfield<1> gem5::Gicv3CPUInterface::VENG1
protected

Definition at line 272 of file gic_v3_cpu_interface.hh.

◆ VEOIM

Bitfield<9> gem5::Gicv3CPUInterface::VEOIM
protected

Definition at line 267 of file gic_v3_cpu_interface.hh.

◆ VFIQEn

Bitfield<3> gem5::Gicv3CPUInterface::VFIQEn
protected

Definition at line 270 of file gic_v3_cpu_interface.hh.

◆ VGrp0D

Bitfield<5> gem5::Gicv3CPUInterface::VGrp0D
protected

Definition at line 253 of file gic_v3_cpu_interface.hh.

◆ VGrp0DIE

Bitfield<5> gem5::Gicv3CPUInterface::VGrp0DIE
protected

Definition at line 213 of file gic_v3_cpu_interface.hh.

◆ VGrp0E

Bitfield<4> gem5::Gicv3CPUInterface::VGrp0E
protected

Definition at line 254 of file gic_v3_cpu_interface.hh.

◆ VGrp0EIE

Bitfield<4> gem5::Gicv3CPUInterface::VGrp0EIE
protected

Definition at line 214 of file gic_v3_cpu_interface.hh.

◆ VGrp1D

Bitfield<7> gem5::Gicv3CPUInterface::VGrp1D
protected

Definition at line 251 of file gic_v3_cpu_interface.hh.

◆ VGrp1DIE

Bitfield<7> gem5::Gicv3CPUInterface::VGrp1DIE
protected

Definition at line 211 of file gic_v3_cpu_interface.hh.

◆ VGrp1E

Bitfield<6> gem5::Gicv3CPUInterface::VGrp1E
protected

Definition at line 252 of file gic_v3_cpu_interface.hh.

◆ VGrp1EIE

Bitfield<6> gem5::Gicv3CPUInterface::VGrp1EIE
protected

Definition at line 212 of file gic_v3_cpu_interface.hh.

◆ vINTID

Bitfield<31, 0> gem5::Gicv3CPUInterface::vINTID
protected

Definition at line 230 of file gic_v3_cpu_interface.hh.

◆ VIRTUAL_NUM_LIST_REGS

const uint8_t gem5::Gicv3CPUInterface::VIRTUAL_NUM_LIST_REGS = 16
staticprotected

◆ VIRTUAL_PREEMPTION_BITS

const uint8_t gem5::Gicv3CPUInterface::VIRTUAL_PREEMPTION_BITS = 5
staticprotected

◆ VIRTUAL_PRIORITY_BITS

const uint8_t gem5::Gicv3CPUInterface::VIRTUAL_PRIORITY_BITS = 5
staticprotected

Definition at line 151 of file gic_v3_cpu_interface.hh.

Referenced by readMiscReg(), and virtualHighestActivePriority().

◆ VPMR

Bitfield<31, 24> gem5::Gicv3CPUInterface::VPMR
protected

Definition at line 263 of file gic_v3_cpu_interface.hh.


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:27:38 for gem5 by doxygen 1.8.17