gem5::Gicv3CPUInterface Class Reference

#include <gic_v3_cpu_interface.hh>

Inheritance diagram for gem5::Gicv3CPUInterface:

Classes
struct	hppi_t

Public Member Functions
	BitUnion64 (ICH_HCR_EL2) Bitfield< 63
	EndBitUnion (ICH_LR_EL2) static const uint64_t ICH_LR_EL2_STATE_INVALID=0
	BitUnion32 (ICH_LRC) Bitfield< 31
	EndBitUnion (ICH_LRC) BitUnion64(ICH_MISR_EL2) Bitfield< 63
	EndBitUnion (ICH_MISR_EL2) BitUnion64(ICH_VMCR_EL2) Bitfield< 63
	EndBitUnion (ICH_VMCR_EL2) BitUnion64(ICH_VTR_EL2) Bitfield< 63
	EndBitUnion (ICH_VTR_EL2) BitUnion64(ICV_CTLR_EL1) Bitfield< 63
EndBitUnion(ICV_CTLR_EL1) protected void	generateSGI (RegVal val, Gicv3::GroupId group)
ArmISA::ExceptionLevel	currEL () const
void	deactivateIRQ (uint32_t intid, Gicv3::GroupId group)
void	dropPriority (Gicv3::GroupId group)
uint64_t	eoiMaintenanceInterruptStatus () const
bool	getHCREL2FMO () const
bool	getHCREL2IMO () const
uint32_t	getHPPIR0 () const
uint32_t	getHPPIR1 () const
int	getHPPVILR () const
bool	groupEnabled (Gicv3::GroupId group) const
uint32_t	groupPriorityMask (Gicv3::GroupId group)
bool	haveEL (ArmISA::ExceptionLevel el) const
int	highestActiveGroup () const
uint8_t	highestActivePriority () const
bool	hppiCanPreempt ()
bool	hppviCanPreempt (int lrIdx) const
bool	inSecureState () const
ArmISA::InterruptTypes	intSignalType (Gicv3::GroupId group) const
bool	isAA64 () const
bool	isEL3OrMon () const
bool	isEOISplitMode () const
bool	isSecureBelowEL3 () const
ICH_MISR_EL2	maintenanceInterruptStatus () const
void	resetHppi (uint32_t intid)
void	serialize (CheckpointOut &cp) const override
	Serialize an object.
void	unserialize (CheckpointIn &cp) override
	Unserialize an object.
void	update ()
void	updateDistributor ()
void	virtualActivateIRQ (uint32_t lrIdx)
void	virtualDeactivateIRQ (int lrIdx)
uint8_t	virtualDropPriority ()
int	virtualFindActive (uint32_t intid) const
uint32_t	virtualGroupPriorityMask (Gicv3::GroupId group) const
uint8_t	virtualHighestActivePriority () const
void	virtualIncrementEOICount ()
bool	virtualIsEOISplitMode () const
void	virtualUpdate ()
RegVal	bpr1 (Gicv3::GroupId group)
bool	havePendingInterrupts (void) const
void	clearPendingInterrupts (void)
void	assertWakeRequest (void)
void	deassertWakeRequest (void)
RegVal	readBankedMiscReg (ArmISA::MiscRegIndex misc_reg) const
void	setBankedMiscReg (ArmISA::MiscRegIndex misc_reg, RegVal val) const
	Gicv3CPUInterface (Gicv3 *gic, ThreadContext *tc)
void	init ()
void	copy (Gicv3Registers *from, Gicv3Registers *to)
RegVal	readMiscReg (int misc_reg) override
	Read a system register belonging to this device.
void	setMiscReg (int misc_reg, RegVal val) override
	Write to a system register belonging to this device.
void	setThreadContext (ThreadContext *tc) override
Public Member Functions inherited from gem5::ArmISA::BaseISADevice
	BaseISADevice ()
virtual	~BaseISADevice ()
virtual void	setISA (ISA *isa)
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.
void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Attributes
Bitfield< 31, 27 >	EOIcount
Bitfield< 26, 15 >	res0_1
Bitfield< 14 >	TDIR
Bitfield< 13 >	TSEI
Bitfield< 12 >	TALL1
Bitfield< 11 >	TALL0
Bitfield< 10 >	TC
Bitfield< 9, 8 >	res0_0
Bitfield< 7 >	VGrp1DIE
Bitfield< 6 >	VGrp1EIE
Bitfield< 5 >	VGrp0DIE
Bitfield< 4 >	VGrp0EIE
Bitfield< 3 >	NPIE
Bitfield< 2 >	LRENPIE
Bitfield< 1 >	UIE
Bitfield< 0 >	En
EndBitUnion(ICH_HCR_EL2) protected Bitfield< 61 >	HW
Bitfield< 60 >	Group
Bitfield< 59, 56 >	res0_1
Bitfield< 55, 48 >	Priority
Bitfield< 47, 45 >	res0_0
Bitfield< 44, 32 >	pINTID
Bitfield< 41 >	EOI
Bitfield< 31, 0 >	vINTID
	State
Bitfield< 29 >	HW
Bitfield< 28 >	Group
Bitfield< 27, 24 >	res0_1
Bitfield< 23, 16 >	Priority
Bitfield< 15, 13 >	res0_0
Bitfield< 12, 0 >	pINTID
Bitfield< 9 >	EOI
Bitfield< 7 >	VGrp1D
Bitfield< 6 >	VGrp1E
Bitfield< 5 >	VGrp0D
Bitfield< 4 >	VGrp0E
Bitfield< 3 >	NP
Bitfield< 2 >	LRENP
Bitfield< 1 >	U
Bitfield< 0 >	EOI
Bitfield< 31, 24 >	VPMR
Bitfield< 23, 21 >	VBPR0
Bitfield< 20, 18 >	VBPR1
Bitfield< 17, 10 >	res0_1
Bitfield< 9 >	VEOIM
Bitfield< 8, 5 >	res0_0
Bitfield< 4 >	VCBPR
Bitfield< 3 >	VFIQEn
Bitfield< 2 >	VAckCtl
Bitfield< 1 >	VENG1
Bitfield< 0 >	VENG0
	res0_1
Bitfield< 31, 29 >	PRIbits
Bitfield< 28, 26 >	PREbits
Bitfield< 25, 23 >	IDbits
Bitfield< 22 >	SEIS
Bitfield< 21 >	A3V
Bitfield< 20 >	res1
Bitfield< 19 >	TDS
Bitfield< 18, 5 >	res0_0
Bitfield< 4, 0 >	ListRegs
Bitfield< 17, 16 >	res0_1
Bitfield< 7, 2 >	res0_0

Static Public Attributes
static const uint64_t	ICH_LR_EL2_STATE_PENDING = 1
static const uint64_t	ICH_LR_EL2_STATE_ACTIVE = 2
static const uint64_t	ICH_LR_EL2_STATE_ACTIVE_PENDING = 3

Protected Types
enum	{   GICC_CTLR = 0x0000 , GICC_PMR = 0x0004 , GICC_BPR = 0x0008 , GICC_IAR = 0x000C ,   GICC_EOIR = 0x0010 , GICC_RPR = 0x0014 , GICC_HPPI = 0x0018 , GICC_ABPR = 0x001C ,   GICC_AIAR = 0x0020 , GICC_AEOIR = 0x0024 , GICC_AHPPIR = 0x0028 , GICC_STATUSR = 0x002C ,   GICC_IIDR = 0x00FC }
enum	{   GICH_HCR = 0x0000 , GICH_VTR = 0x0004 , GICH_VMCR = 0x0008 , GICH_MISR = 0x0010 ,   GICH_EISR = 0x0020 , GICH_ELRSR = 0x0030 }

Protected Member Functions
	BitUnion64 (ICC_CTLR_EL1) Bitfield< 63
	EndBitUnion (ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63
	EndBitUnion (ICC_CTLR_EL3) BitUnion64(ICC_IGRPEN0_EL1) Bitfield< 63
	EndBitUnion (ICC_IGRPEN0_EL1) BitUnion64(ICC_IGRPEN1_EL1) Bitfield< 63
	EndBitUnion (ICC_IGRPEN1_EL1) BitUnion64(ICC_IGRPEN1_EL3) Bitfield< 63
	EndBitUnion (ICC_IGRPEN1_EL3) BitUnion64(ICC_SRE_EL1) Bitfield< 63
	EndBitUnion (ICC_SRE_EL1) BitUnion64(ICC_SRE_EL2) Bitfield< 63
	EndBitUnion (ICC_SRE_EL2) BitUnion64(ICC_SRE_EL3) Bitfield< 63
	EndBitUnion (ICC_SRE_EL3) static const uint8_t PRIORITY_BITS

Protected Attributes
Gicv3 *	gic
Gicv3Redistributor *	redistributor
Gicv3Distributor *	distributor
ThreadContext *	tc
ArmInterruptPin *	maintenanceInterrupt
uint32_t	cpuId
	res0_3
Bitfield< 19 >	ExtRange
Bitfield< 18 >	RSS
Bitfield< 17, 16 >	res0_2
Bitfield< 15 >	A3V
Bitfield< 14 >	SEIS
Bitfield< 13, 11 >	IDbits
Bitfield< 10, 8 >	PRIbits
Bitfield< 7 >	res0_1
Bitfield< 6 >	PMHE
Bitfield< 5, 2 >	res0_0
Bitfield< 1 >	EOImode
Bitfield< 0 >	CBPR
	res0_2
Bitfield< 17 >	nDS
Bitfield< 16 >	res0_1
Bitfield< 7 >	res0_0
Bitfield< 5 >	RM
Bitfield< 4 >	EOImode_EL1NS
Bitfield< 3 >	EOImode_EL1S
Bitfield< 2 >	EOImode_EL3
Bitfield< 1 >	CBPR_EL1NS
Bitfield< 0 >	CBPR_EL1S
	res0
Bitfield< 0 >	Enable
Bitfield< 1 >	EnableGrp1S
Bitfield< 0 >	EnableGrp1NS
Bitfield< 2 >	DIB
Bitfield< 1 >	DFB
Bitfield< 0 >	SRE
Bitfield< 3 >	Enable
hppi_t	hppi
Protected Attributes inherited from gem5::ArmISA::BaseISADevice
ISA *	isa

Static Protected Attributes
static const uint8_t	GIC_MIN_BPR = 2
static const uint8_t	GIC_MIN_BPR_NS = GIC_MIN_BPR + 1
static const uint8_t	VIRTUAL_PRIORITY_BITS = 5
static const uint8_t	VIRTUAL_PREEMPTION_BITS = 5
static const uint8_t	VIRTUAL_NUM_LIST_REGS = 16
static const uint8_t	GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS
static const AddrRange	GICC_APR
static const AddrRange	GICC_NSAPR
static const AddrRange	GICH_APR
static const AddrRange	GICH_LR

Friends
class	Gicv3Distributor
class	Gicv3Redistributor
class	ArmISA::ISA

Additional Inherited Members
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Detailed Description

Definition at line 58 of file gic_v3_cpu_interface.hh.

Member Enumeration Documentation

anonymous enum

anonymous enum

protected

Enumerator
GICC_CTLR
GICC_PMR
GICC_BPR
GICC_IAR
GICC_EOIR
GICC_RPR
GICC_HPPI
GICC_ABPR
GICC_AIAR
GICC_AEOIR
GICC_AHPPIR
GICC_STATUSR
GICC_IIDR

Definition at line 174 of file gic_v3_cpu_interface.hh.

anonymous enum

anonymous enum

protected

Enumerator
GICH_HCR
GICH_VTR
GICH_VMCR
GICH_MISR
GICH_EISR
GICH_ELRSR

Definition at line 195 of file gic_v3_cpu_interface.hh.

Constructor & Destructor Documentation

Gicv3CPUInterface()

gem5::Gicv3CPUInterface::Gicv3CPUInterface	(	Gicv3 *	gic,
		ThreadContext *	tc )

Definition at line 58 of file gic_v3_cpu_interface.cc.

References gem5::ThreadContext::getIsaPtr(), hppi, gem5::Gicv3CPUInterface::hppi_t::intid, gem5::Gicv3::INTID_SPURIOUS, gem5::Gicv3CPUInterface::hppi_t::prio, gem5::ArmISA::BaseISADevice::setISA(), and tc.

Member Function Documentation

assertWakeRequest()

void gem5::Gicv3CPUInterface::assertWakeRequest

(

void

)

Definition at line 2571 of file gic_v3_cpu_interface.cc.

References gem5::ThreadContext::activate(), gem5::ArmSystem::callSetWakeRequest(), cpuId, gem5::BaseGic::getSystem(), gic, gem5::ArmISA::Reset::invoke(), tc, and gem5::System::threads.

Referenced by gem5::Gicv3Redistributor::update().

BitUnion32()

gem5::Gicv3CPUInterface::BitUnion32

(

ICH_LRC

)

BitUnion64() [1/2]

gem5::Gicv3CPUInterface::BitUnion64 ( ICC_CTLR_EL1 )

protected

BitUnion64() [2/2]

gem5::Gicv3CPUInterface::BitUnion64

(

ICH_HCR_EL2

)

bpr1()

RegVal gem5::Gicv3CPUInterface::bpr1

(

Gicv3::GroupId

group

)

Definition at line 2517 of file gic_v3_cpu_interface.cc.

References currEL(), gem5::ArmISA::EL1, gem5::ArmISA::EL3, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, getHCREL2IMO(), GIC_MIN_BPR, GIC_MIN_BPR_NS, haveEL(), inSecureState(), gem5::ArmISA::BaseISADevice::isa, isEL3OrMon(), gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S, gem5::ArmISA::MISCREG_ICV_BPR1_EL1, panic, readMiscReg(), and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by groupPriorityMask(), and readMiscReg().

clearPendingInterrupts()

void gem5::Gicv3CPUInterface::clearPendingInterrupts

(

void

)

Definition at line 2564 of file gic_v3_cpu_interface.cc.

References cpuId, gem5::Gicv3::deassertAll(), gic, hppi, gem5::Gicv3CPUInterface::hppi_t::intid, and resetHppi().

Referenced by gem5::Gicv3Redistributor::update().

copy()

void gem5::Gicv3CPUInterface::copy	(	Gicv3Registers *	from,
		Gicv3Registers *	to )

Definition at line 2588 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::affinity, gem5::Gicv3Registers::copyCpuRegister(), gem5::Gicv3Redistributor::getAffinity(), gic, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICC_SRE_EL1, redistributor, and gem5::PowerISA::to.

currEL()

ExceptionLevel gem5::Gicv3CPUInterface::currEL

(

)

const

Definition at line 2351 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::currEL(), and tc.

Referenced by bpr1(), getHPPIR1(), intSignalType(), isEL3OrMon(), readMiscReg(), and setMiscReg().

deactivateIRQ()

void gem5::Gicv3CPUInterface::deactivateIRQ	(	uint32_t	intid,
		Gicv3::GroupId	group )

Definition at line 1890 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3Distributor::deactivateIRQ(), gem5::Gicv3Redistributor::deactivateIRQ(), distributor, gem5::Gicv3::INTID_SECURE, gem5::Gicv3::PPI_MAX, redistributor, gem5::Gicv3::SGI_MAX, and updateDistributor().

Referenced by setMiscReg(), and virtualDeactivateIRQ().

deassertWakeRequest()

void gem5::Gicv3CPUInterface::deassertWakeRequest

(

void

)

Definition at line 2581 of file gic_v3_cpu_interface.cc.

References gem5::ArmSystem::callClearWakeRequest(), cpuId, gem5::BaseGic::getSystem(), gic, tc, and gem5::System::threads.

Referenced by gem5::Gicv3Redistributor::write().

dropPriority()

void gem5::Gicv3CPUInterface::dropPriority

(

Gicv3::GroupId

group

)

Definition at line 1720 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S, panic, gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::ISA::setMiscRegNoEffect(), and update().

Referenced by setMiscReg().

EndBitUnion() [1/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_CTLR_EL1 )

protected

EndBitUnion() [2/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_CTLR_EL3 )

protected

EndBitUnion() [3/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_IGRPEN0_EL1 )

protected

EndBitUnion() [4/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_IGRPEN1_EL1 )

protected

EndBitUnion() [5/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_IGRPEN1_EL3 )

protected

EndBitUnion() [6/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_SRE_EL1 )

protected

EndBitUnion() [7/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_SRE_EL2 )

protected

EndBitUnion() [8/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICC_SRE_EL3 ) const

protected

EndBitUnion() [9/13]

gem5::Gicv3CPUInterface::EndBitUnion ( ICH_LR_EL2 ) const

pure virtual

EndBitUnion() [10/13]

gem5::Gicv3CPUInterface::EndBitUnion

(

ICH_LRC

)

EndBitUnion() [11/13]

gem5::Gicv3CPUInterface::EndBitUnion

(

ICH_MISR_EL2

)

EndBitUnion() [12/13]

gem5::Gicv3CPUInterface::EndBitUnion

(

ICH_VMCR_EL2

)

EndBitUnion() [13/13]

gem5::Gicv3CPUInterface::EndBitUnion

(

ICH_VTR_EL2

)

eoiMaintenanceInterruptStatus()

uint64_t gem5::Gicv3CPUInterface::eoiMaintenanceInterruptStatus

(

)

const

Definition at line 2396 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), and VIRTUAL_NUM_LIST_REGS.

Referenced by maintenanceInterruptStatus(), and readMiscReg().

generateSGI()

void gem5::Gicv3CPUInterface::generateSGI	(	RegVal	val,
		Gicv3::GroupId	group )

Definition at line 1779 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::aff1, gem5::ArmISA::aff2, gem5::ArmISA::aff3, gem5::bits(), gem5::Gicv3Redistributor::getAffinity(), gem5::Gicv3::getRedistributor(), gem5::BaseGic::getSystem(), gic, gem5::ArmISA::i, inSecureState(), gem5::ArmISA::ns, redistributor, gem5::ArmISA::rs, gem5::Gicv3Redistributor::sendSGI(), and gem5::X86ISA::val.

Referenced by setMiscReg().

getHCREL2FMO()

bool gem5::Gicv3CPUInterface::getHCREL2FMO

(

)

const

Definition at line 97 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::MISCREG_HCR_EL2, gem5::ThreadContext::readMiscRegNoEffect(), and tc.

Referenced by readMiscReg(), and setMiscReg().

getHCREL2IMO()

bool gem5::Gicv3CPUInterface::getHCREL2IMO

(

)

const

Definition at line 111 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::MISCREG_HCR_EL2, gem5::ThreadContext::readMiscRegNoEffect(), and tc.

Referenced by bpr1(), readMiscReg(), and setMiscReg().

getHPPIR0()

uint32_t gem5::Gicv3CPUInterface::getHPPIR0

(

)

const

Definition at line 1659 of file gic_v3_cpu_interface.cc.

References distributor, gem5::Gicv3Distributor::DS, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3CPUInterface::hppi_t::group, groupEnabled(), hppi, inSecureState(), gem5::Gicv3CPUInterface::hppi_t::intid, gem5::Gicv3::INTID_NONSECURE, gem5::Gicv3::INTID_SECURE, gem5::Gicv3::INTID_SPURIOUS, isEL3OrMon(), and gem5::Gicv3CPUInterface::hppi_t::prio.

Referenced by readMiscReg().

getHPPIR1()

uint32_t gem5::Gicv3CPUInterface::getHPPIR1

(

)

const

Definition at line 1685 of file gic_v3_cpu_interface.cc.

References currEL(), distributor, gem5::Gicv3Distributor::DS, gem5::ArmISA::EL3, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3CPUInterface::hppi_t::group, groupEnabled(), hppi, inSecureState(), gem5::Gicv3CPUInterface::hppi_t::intid, gem5::Gicv3::INTID_NONSECURE, gem5::Gicv3::INTID_SECURE, gem5::Gicv3::INTID_SPURIOUS, gem5::ArmISA::BaseISADevice::isa, isEL3OrMon(), gem5::ArmISA::MISCREG_ICC_CTLR_EL3, gem5::Gicv3CPUInterface::hppi_t::prio, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by readMiscReg().

getHPPVILR()

int gem5::Gicv3CPUInterface::getHPPVILR

(

)

const

Definition at line 2127 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::i, gem5::Gicv3::INT_PENDING, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by readMiscReg(), and virtualUpdate().

groupEnabled()

bool gem5::Gicv3CPUInterface::groupEnabled

(

Gicv3::GroupId

group

)

const

Definition at line 2318 of file gic_v3_cpu_interface.cc.

References distributor, gem5::Gicv3Distributor::EnableGrp0, gem5::Gicv3Distributor::EnableGrp1NS, gem5::Gicv3Distributor::EnableGrp1S, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, panic, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by getHPPIR0(), getHPPIR1(), and hppiCanPreempt().

groupPriorityMask()

uint32_t gem5::Gicv3CPUInterface::groupPriorityMask

(

Gicv3::GroupId

group

)

Definition at line 1929 of file gic_v3_cpu_interface.cc.

References bpr1(), gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S, readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), and U.

Referenced by hppiCanPreempt().

haveEL()

bool gem5::Gicv3CPUInterface::haveEL

(

ArmISA::ExceptionLevel

el

)

const

Definition at line 2357 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::el, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::BaseGic::getSystem(), gic, gem5::ArmSystem::has(), and warn.

Referenced by bpr1(), readMiscReg(), setMiscReg(), and update().

havePendingInterrupts()

bool gem5::Gicv3CPUInterface::havePendingInterrupts

(

void

)

const

Definition at line 2558 of file gic_v3_cpu_interface.cc.

References cpuId, gic, gem5::Gicv3::haveAsserted(), hppi, and gem5::Gicv3CPUInterface::hppi_t::prio.

Referenced by gem5::Gicv3Redistributor::update().

highestActiveGroup()

int gem5::Gicv3CPUInterface::highestActiveGroup

(

)

const

Definition at line 2010 of file gic_v3_cpu_interface.cc.

References gem5::ctz32(), gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by setMiscReg().

highestActivePriority()

uint8_t gem5::Gicv3CPUInterface::highestActivePriority

(

)

const

Definition at line 2303 of file gic_v3_cpu_interface.cc.

References gem5::ctz32(), GIC_MIN_BPR, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by hppiCanPreempt(), and readMiscReg().

hppiCanPreempt()

bool gem5::Gicv3CPUInterface::hppiCanPreempt

(

)

Definition at line 2270 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3CPUInterface::hppi_t::group, groupEnabled(), groupPriorityMask(), highestActivePriority(), hppi, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::Gicv3CPUInterface::hppi_t::prio, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by readMiscReg(), and update().

hppviCanPreempt()

bool gem5::Gicv3CPUInterface::hppviCanPreempt

(

int

lrIdx

)

const

Definition at line 2171 of file gic_v3_cpu_interface.cc.

References gem5::bits(), gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), virtualGroupPriorityMask(), and virtualHighestActivePriority().

Referenced by readMiscReg(), and virtualUpdate().

init()

void gem5::Gicv3CPUInterface::init

(

)

Definition at line 74 of file gic_v3_cpu_interface.cc.

References cpuId, distributor, gem5::Gicv3::getDistributor(), gem5::Gicv3::getRedistributor(), gic, and redistributor.

inSecureState()

bool gem5::Gicv3CPUInterface::inSecureState

(

)

const

Definition at line 2345 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::isSecure(), and tc.

Referenced by bpr1(), generateSGI(), getHPPIR0(), getHPPIR1(), intSignalType(), isEOISplitMode(), readMiscReg(), and setMiscReg().

intSignalType()

InterruptTypes gem5::Gicv3CPUInterface::intSignalType

(

Gicv3::GroupId

group

)

const

Definition at line 2240 of file gic_v3_cpu_interface.cc.

References currEL(), distributor, gem5::Gicv3Distributor::DS, gem5::ArmISA::EL3, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, inSecureState(), gem5::ArmISA::INT_FIQ, gem5::ArmISA::INT_IRQ, isAA64(), and panic.

Referenced by update().

isAA64()

bool gem5::Gicv3CPUInterface::isAA64

(

)

const

Definition at line 2383 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::inAArch64(), and tc.

Referenced by intSignalType().

isEL3OrMon()

bool gem5::Gicv3CPUInterface::isEL3OrMon

(

)

const

Definition at line 2389 of file gic_v3_cpu_interface.cc.

References currEL(), and gem5::ArmISA::EL3.

Referenced by bpr1(), getHPPIR0(), getHPPIR1(), isEOISplitMode(), and setMiscReg().

isEOISplitMode()

bool gem5::Gicv3CPUInterface::isEOISplitMode

(

)

const

Definition at line 1986 of file gic_v3_cpu_interface.cc.

References inSecureState(), gem5::ArmISA::BaseISADevice::isa, isEL3OrMon(), gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR_EL3, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by setMiscReg().

isSecureBelowEL3()

bool gem5::Gicv3CPUInterface::isSecureBelowEL3

(

)

const

Definition at line 2377 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::isSecureBelowEL3(), and tc.

Referenced by readBankedMiscReg(), readMiscReg(), setBankedMiscReg(), and setMiscReg().

maintenanceInterruptStatus()

Gicv3CPUInterface::ICH_MISR_EL2 gem5::Gicv3CPUInterface::maintenanceInterruptStatus

(

)

const

Definition at line 2429 of file gic_v3_cpu_interface.cc.

References eoiMaintenanceInterruptStatus(), ICH_LR_EL2_STATE_PENDING, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), and VIRTUAL_NUM_LIST_REGS.

Referenced by readMiscReg(), and virtualUpdate().

readBankedMiscReg()

RegVal gem5::Gicv3CPUInterface::readBankedMiscReg

(

ArmISA::MiscRegIndex

misc_reg

)

const

Definition at line 1628 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::BaseISADevice::isa, isSecureBelowEL3(), gem5::ArmISA::ISA::readMiscRegNoEffect(), and gem5::ArmISA::ISA::snsBankedIndex64().

Referenced by readMiscReg(), and setMiscReg().

readMiscReg()

RegVal gem5::Gicv3CPUInterface::readMiscReg ( int misc_reg )

overridevirtual

Read a system register belonging to this device.

Parameters

misc_reg

Register number (see regs/misc.hh)

Returns

Register value.

Implements gem5::ArmISA::BaseISADevice.

Definition at line 125 of file gic_v3_cpu_interface.cc.

References bpr1(), currEL(), DPRINTF, gem5::ArmISA::EL1, gem5::ArmISA::EL3, Enable, eoiMaintenanceInterruptStatus(), gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, getHCREL2FMO(), getHCREL2IMO(), getHPPIR0(), getHPPIR1(), getHPPVILR(), gem5::Gicv3CPUInterface::hppi_t::group, haveEL(), highestActivePriority(), hppi, hppiCanPreempt(), hppviCanPreempt(), inSecureState(), gem5::Gicv3::INTID_SECURE, gem5::Gicv3::INTID_SPURIOUS, gem5::ArmISA::BaseISADevice::isa, isSecureBelowEL3(), maintenanceInterruptStatus(), gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP0R1, gem5::ArmISA::MISCREG_ICC_AP0R1_EL1, gem5::ArmISA::MISCREG_ICC_AP0R2, gem5::ArmISA::MISCREG_ICC_AP0R2_EL1, gem5::ArmISA::MISCREG_ICC_AP0R3, gem5::ArmISA::MISCREG_ICC_AP0R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1, gem5::ArmISA::MISCREG_ICC_AP1R2, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1, gem5::ArmISA::MISCREG_ICC_AP1R3, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1, gem5::ArmISA::MISCREG_ICC_BPR0, gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_BPR1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1, gem5::ArmISA::MISCREG_ICC_CTLR, gem5::ArmISA::MISCREG_ICC_CTLR_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL3, gem5::ArmISA::MISCREG_ICC_HPPIR0, gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1, gem5::ArmISA::MISCREG_ICC_HPPIR1, gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1, gem5::ArmISA::MISCREG_ICC_HSRE, gem5::ArmISA::MISCREG_ICC_IAR0, gem5::ArmISA::MISCREG_ICC_IAR0_EL1, gem5::ArmISA::MISCREG_ICC_IAR1, gem5::ArmISA::MISCREG_ICC_IAR1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN0, gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3, gem5::ArmISA::MISCREG_ICC_MCTLR, gem5::ArmISA::MISCREG_ICC_MGRPEN1, gem5::ArmISA::MISCREG_ICC_MSRE, gem5::ArmISA::MISCREG_ICC_PMR, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICC_RPR, gem5::ArmISA::MISCREG_ICC_RPR_EL1, gem5::ArmISA::MISCREG_ICC_SRE, gem5::ArmISA::MISCREG_ICC_SRE_EL1, gem5::ArmISA::MISCREG_ICC_SRE_EL2, gem5::ArmISA::MISCREG_ICC_SRE_EL3, gem5::ArmISA::MISCREG_ICH_AP0R0, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP0R1, gem5::ArmISA::MISCREG_ICH_AP0R1_EL2, gem5::ArmISA::MISCREG_ICH_AP0R2, gem5::ArmISA::MISCREG_ICH_AP0R2_EL2, gem5::ArmISA::MISCREG_ICH_AP0R3, gem5::ArmISA::MISCREG_ICH_AP0R3_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R1, gem5::ArmISA::MISCREG_ICH_AP1R1_EL2, gem5::ArmISA::MISCREG_ICH_AP1R2, gem5::ArmISA::MISCREG_ICH_AP1R2_EL2, gem5::ArmISA::MISCREG_ICH_AP1R3, gem5::ArmISA::MISCREG_ICH_AP1R3_EL2, gem5::ArmISA::MISCREG_ICH_EISR, gem5::ArmISA::MISCREG_ICH_EISR_EL2, gem5::ArmISA::MISCREG_ICH_ELRSR, gem5::ArmISA::MISCREG_ICH_ELRSR_EL2, gem5::ArmISA::MISCREG_ICH_HCR, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_LR15, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICH_LRC0, gem5::ArmISA::MISCREG_ICH_LRC15, gem5::ArmISA::MISCREG_ICH_MISR, gem5::ArmISA::MISCREG_ICH_MISR_EL2, gem5::ArmISA::MISCREG_ICH_VMCR, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::MISCREG_ICH_VTR, gem5::ArmISA::MISCREG_ICH_VTR_EL2, gem5::ArmISA::MISCREG_ICV_AP0R0_EL1, gem5::ArmISA::MISCREG_ICV_AP1R0_EL1, gem5::ArmISA::MISCREG_ICV_BPR0_EL1, gem5::ArmISA::MISCREG_ICV_BPR1_EL1, gem5::ArmISA::MISCREG_ICV_CTLR_EL1, gem5::ArmISA::MISCREG_ICV_HPPIR0_EL1, gem5::ArmISA::MISCREG_ICV_HPPIR1_EL1, gem5::ArmISA::MISCREG_ICV_IAR0_EL1, gem5::ArmISA::MISCREG_ICV_IAR1_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICV_PMR_EL1, gem5::ArmISA::MISCREG_ICV_RPR_EL1, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::miscRegName, panic, readBankedMiscReg(), readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::Gicv3Redistributor::SMALLEST_LPI_ID, tc, VIRTUAL_NUM_LIST_REGS, VIRTUAL_PREEMPTION_BITS, VIRTUAL_PRIORITY_BITS, virtualActivateIRQ(), virtualHighestActivePriority(), and virtualUpdate().

Referenced by bpr1(), groupPriorityMask(), and readMiscReg().

resetHppi()

void gem5::Gicv3CPUInterface::resetHppi

(

uint32_t

intid

)

Definition at line 81 of file gic_v3_cpu_interface.cc.

References hppi, gem5::Gicv3CPUInterface::hppi_t::intid, and gem5::Gicv3CPUInterface::hppi_t::prio.

Referenced by clearPendingInterrupts(), and gem5::Gicv3Redistributor::setClrLPI().

serialize()

void gem5::Gicv3CPUInterface::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 2611 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3CPUInterface::hppi_t::group, hppi, gem5::Gicv3CPUInterface::hppi_t::intid, gem5::Gicv3CPUInterface::hppi_t::prio, SERIALIZE_ENUM, and SERIALIZE_SCALAR.

setBankedMiscReg()

void gem5::Gicv3CPUInterface::setBankedMiscReg	(	ArmISA::MiscRegIndex	misc_reg,
		RegVal	val ) const

Definition at line 1635 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::BaseISADevice::isa, isSecureBelowEL3(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::ArmISA::ISA::snsBankedIndex64(), and gem5::X86ISA::val.

Referenced by setMiscReg().

setMiscReg()

void gem5::Gicv3CPUInterface::setMiscReg ( int misc_reg, RegVal val )

overridevirtual

Write to a system register belonging to this device.

Parameters

misc_reg	Register number (see regs/misc.hh)
val	Value to store

Implements gem5::ArmISA::BaseISADevice.

Definition at line 745 of file gic_v3_cpu_interface.cc.

References currEL(), deactivateIRQ(), distributor, DPRINTF, dropPriority(), gem5::Gicv3Distributor::DS, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::X86ISA::enable, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, generateSGI(), getHCREL2FMO(), getHCREL2IMO(), gem5::Gicv3Distributor::getIntGroup(), gem5::Gicv3Redistributor::getIntGroup(), GIC_MIN_BPR, GIC_MIN_BPR_NS, haveEL(), highestActiveGroup(), inSecureState(), gem5::Gicv3::INTID_SECURE, gem5::Gicv3::INTID_SPURIOUS, gem5::ArmISA::BaseISADevice::isa, isEL3OrMon(), isEOISplitMode(), isSecureBelowEL3(), gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP0R1, gem5::ArmISA::MISCREG_ICC_AP0R1_EL1, gem5::ArmISA::MISCREG_ICC_AP0R2, gem5::ArmISA::MISCREG_ICC_AP0R2_EL1, gem5::ArmISA::MISCREG_ICC_AP0R3, gem5::ArmISA::MISCREG_ICC_AP0R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1, gem5::ArmISA::MISCREG_ICC_AP1R2, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1, gem5::ArmISA::MISCREG_ICC_AP1R3, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1, gem5::ArmISA::MISCREG_ICC_ASGI1R, gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1, gem5::ArmISA::MISCREG_ICC_BPR0, gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_BPR1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR, gem5::ArmISA::MISCREG_ICC_CTLR_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR_EL3, gem5::ArmISA::MISCREG_ICC_DIR, gem5::ArmISA::MISCREG_ICC_DIR_EL1, gem5::ArmISA::MISCREG_ICC_EOIR0, gem5::ArmISA::MISCREG_ICC_EOIR0_EL1, gem5::ArmISA::MISCREG_ICC_EOIR1, gem5::ArmISA::MISCREG_ICC_EOIR1_EL1, gem5::ArmISA::MISCREG_ICC_HSRE, gem5::ArmISA::MISCREG_ICC_IGRPEN0, gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3, gem5::ArmISA::MISCREG_ICC_MCTLR, gem5::ArmISA::MISCREG_ICC_MGRPEN1, gem5::ArmISA::MISCREG_ICC_MSRE, gem5::ArmISA::MISCREG_ICC_PMR, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICC_SGI0R, gem5::ArmISA::MISCREG_ICC_SGI0R_EL1, gem5::ArmISA::MISCREG_ICC_SGI1R, gem5::ArmISA::MISCREG_ICC_SGI1R_EL1, gem5::ArmISA::MISCREG_ICC_SRE, gem5::ArmISA::MISCREG_ICC_SRE_EL1, gem5::ArmISA::MISCREG_ICC_SRE_EL2, gem5::ArmISA::MISCREG_ICC_SRE_EL3, gem5::ArmISA::MISCREG_ICH_AP0R0, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP0R1, gem5::ArmISA::MISCREG_ICH_AP0R1_EL2, gem5::ArmISA::MISCREG_ICH_AP0R2, gem5::ArmISA::MISCREG_ICH_AP0R2_EL2, gem5::ArmISA::MISCREG_ICH_AP0R3, gem5::ArmISA::MISCREG_ICH_AP0R3_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R1, gem5::ArmISA::MISCREG_ICH_AP1R1_EL2, gem5::ArmISA::MISCREG_ICH_AP1R2, gem5::ArmISA::MISCREG_ICH_AP1R2_EL2, gem5::ArmISA::MISCREG_ICH_AP1R3, gem5::ArmISA::MISCREG_ICH_AP1R3_EL2, gem5::ArmISA::MISCREG_ICH_HCR, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_LR15, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICH_LRC0, gem5::ArmISA::MISCREG_ICH_LRC15, gem5::ArmISA::MISCREG_ICH_VMCR, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::MISCREG_ICV_AP0R0_EL1, gem5::ArmISA::MISCREG_ICV_AP1R0_EL1, gem5::ArmISA::MISCREG_ICV_BPR0_EL1, gem5::ArmISA::MISCREG_ICV_BPR1_EL1, gem5::ArmISA::MISCREG_ICV_CTLR_EL1, gem5::ArmISA::MISCREG_ICV_DIR_EL1, gem5::ArmISA::MISCREG_ICV_EOIR0_EL1, gem5::ArmISA::MISCREG_ICV_EOIR1_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICV_PMR_EL1, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::miscRegName, panic, readBankedMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ThreadContext::readMiscRegNoEffect(), redistributor, setBankedMiscReg(), setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), tc, U, updateDistributor(), gem5::X86ISA::val, VIRTUAL_PREEMPTION_BITS, virtualDeactivateIRQ(), virtualDropPriority(), virtualFindActive(), virtualIncrementEOICount(), virtualIsEOISplitMode(), and virtualUpdate().

Referenced by setMiscReg().

setThreadContext()

void gem5::Gicv3CPUInterface::setThreadContext ( ThreadContext * tc )

overridevirtual

Reimplemented from gem5::ArmISA::BaseISADevice.

Definition at line 88 of file gic_v3_cpu_interface.cc.

References fatal_if, gic, gem5::Gicv3Redistributor::irqPending, maintenanceInterrupt, gem5::ArmInterruptPin::num(), gem5::BaseGic::params(), redistributor, and tc.

unserialize()

void gem5::Gicv3CPUInterface::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 2619 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3CPUInterface::hppi_t::group, hppi, gem5::Gicv3CPUInterface::hppi_t::intid, gem5::Gicv3CPUInterface::hppi_t::prio, UNSERIALIZE_ENUM, and UNSERIALIZE_SCALAR.

update()

void gem5::Gicv3CPUInterface::update

(

)

Definition at line 2038 of file gic_v3_cpu_interface.cc.

References gem5::BaseGic::blockIntUpdate(), cpuId, gem5::Gicv3::deassertInt(), DPRINTF, gem5::ArmISA::EL3, gem5::Gicv3::G0S, gem5::Gicv3::G1S, gic, gem5::Gicv3CPUInterface::hppi_t::group, haveEL(), hppi, hppiCanPreempt(), gem5::ArmISA::INT_FIQ, gem5::ArmISA::INT_IRQ, intSignalType(), and gem5::Gicv3::postInt().

Referenced by dropPriority(), and gem5::Gicv3Redistributor::update().

updateDistributor()

void gem5::Gicv3CPUInterface::updateDistributor

(

)

Definition at line 2032 of file gic_v3_cpu_interface.cc.

References distributor, and gem5::Gicv3Distributor::update().

Referenced by deactivateIRQ(), and setMiscReg().

virtualActivateIRQ()

void gem5::Gicv3CPUInterface::virtualActivateIRQ

(

uint32_t

lrIdx

)

Definition at line 1869 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3::G0S, gem5::Gicv3::G1NS, ICH_LR_EL2_STATE_ACTIVE, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::ISA::setMiscRegNoEffect(), and VIRTUAL_PREEMPTION_BITS.

Referenced by readMiscReg().

virtualDeactivateIRQ()

void gem5::Gicv3CPUInterface::virtualDeactivateIRQ

(

int

lrIdx

)

Definition at line 1904 of file gic_v3_cpu_interface.cc.

References deactivateIRQ(), distributor, gem5::Gicv3Distributor::getIntGroup(), gem5::Gicv3Redistributor::getIntGroup(), gem5::Gicv3::INTID_SECURE, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), redistributor, and gem5::ArmISA::ISA::setMiscRegNoEffect().

Referenced by setMiscReg().

virtualDropPriority()

uint8_t gem5::Gicv3CPUInterface::virtualDropPriority

(

)

Definition at line 1749 of file gic_v3_cpu_interface.cc.

References gem5::ctz32(), GIC_MIN_VBPR, gem5::ArmISA::i, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::ISA::setMiscRegNoEffect(), and VIRTUAL_PREEMPTION_BITS.

Referenced by setMiscReg().

virtualFindActive()

int gem5::Gicv3CPUInterface::virtualFindActive

(

uint32_t

intid

)

const

Definition at line 1642 of file gic_v3_cpu_interface.cc.

References ICH_LR_EL2_STATE_ACTIVE, ICH_LR_EL2_STATE_ACTIVE_PENDING, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), and VIRTUAL_NUM_LIST_REGS.

Referenced by setMiscReg().

virtualGroupPriorityMask()

uint32_t gem5::Gicv3CPUInterface::virtualGroupPriorityMask

(

Gicv3::GroupId

group

)

const

Definition at line 1960 of file gic_v3_cpu_interface.cc.

References gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), and U.

Referenced by hppviCanPreempt().

virtualHighestActivePriority()

uint8_t gem5::Gicv3CPUInterface::virtualHighestActivePriority

(

)

const

Definition at line 2207 of file gic_v3_cpu_interface.cc.

References gem5::ctz32(), GIC_MIN_VBPR, gem5::ArmISA::i, gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), and VIRTUAL_PRIORITY_BITS.

Referenced by hppviCanPreempt(), and readMiscReg().

virtualIncrementEOICount()

void gem5::Gicv3CPUInterface::virtualIncrementEOICount

(

)

Definition at line 2228 of file gic_v3_cpu_interface.cc.

References gem5::bits(), gem5::insertBits(), gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::ISA::readMiscRegNoEffect(), and gem5::ArmISA::ISA::setMiscRegNoEffect().

Referenced by setMiscReg().

virtualIsEOISplitMode()

bool gem5::Gicv3CPUInterface::virtualIsEOISplitMode

(

)

const

Definition at line 2003 of file gic_v3_cpu_interface.cc.

References gem5::ArmISA::BaseISADevice::isa, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, and gem5::ArmISA::ISA::readMiscRegNoEffect().

Referenced by setMiscReg().

virtualUpdate()

void gem5::Gicv3CPUInterface::virtualUpdate

(

)

Definition at line 2075 of file gic_v3_cpu_interface.cc.

References gem5::BaseGic::blockIntUpdate(), gem5::ArmInterruptPin::clear(), cpuId, gem5::Gicv3::deassertInt(), DPRINTF, getHPPVILR(), gic, hppviCanPreempt(), gem5::ArmISA::INT_VIRT_FIQ, gem5::ArmISA::INT_VIRT_IRQ, gem5::Gicv3Redistributor::irqPending, gem5::ArmISA::BaseISADevice::isa, maintenanceInterrupt, maintenanceInterruptStatus(), gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmInterruptPin::num(), gem5::Gicv3::postInt(), gem5::ArmInterruptPin::raise(), gem5::ArmISA::ISA::readMiscRegNoEffect(), and redistributor.

Referenced by readMiscReg(), and setMiscReg().

Friends And Related Symbol Documentation

ArmISA::ISA

friend class ArmISA::ISA

friend

Definition at line 64 of file gic_v3_cpu_interface.hh.

Gicv3Distributor

friend class Gicv3Distributor

friend

Definition at line 62 of file gic_v3_cpu_interface.hh.

Gicv3Redistributor

friend class Gicv3Redistributor

friend

Definition at line 63 of file gic_v3_cpu_interface.hh.

Member Data Documentation

A3V [1/2]

Bitfield< 15 > gem5::Gicv3CPUInterface::A3V

protected

Definition at line 81 of file gic_v3_cpu_interface.hh.

A3V [2/2]

Bitfield<21> gem5::Gicv3CPUInterface::A3V

Definition at line 291 of file gic_v3_cpu_interface.hh.

CBPR

Bitfield< 0 > gem5::Gicv3CPUInterface::CBPR

protected

Definition at line 89 of file gic_v3_cpu_interface.hh.

CBPR_EL1NS

Bitfield<1> gem5::Gicv3CPUInterface::CBPR_EL1NS

protected

Definition at line 108 of file gic_v3_cpu_interface.hh.

CBPR_EL1S

Bitfield<0> gem5::Gicv3CPUInterface::CBPR_EL1S

protected

Definition at line 109 of file gic_v3_cpu_interface.hh.

cpuId

uint32_t gem5::Gicv3CPUInterface::cpuId

protected

Definition at line 74 of file gic_v3_cpu_interface.hh.

Referenced by assertWakeRequest(), clearPendingInterrupts(), deassertWakeRequest(), havePendingInterrupts(), init(), update(), and virtualUpdate().

DFB

Bitfield< 1 > gem5::Gicv3CPUInterface::DFB

protected

Definition at line 131 of file gic_v3_cpu_interface.hh.

DIB

Bitfield< 2 > gem5::Gicv3CPUInterface::DIB

protected

Definition at line 130 of file gic_v3_cpu_interface.hh.

distributor

Gicv3Distributor* gem5::Gicv3CPUInterface::distributor

protected

Definition at line 70 of file gic_v3_cpu_interface.hh.

Referenced by deactivateIRQ(), getHPPIR0(), getHPPIR1(), groupEnabled(), init(), intSignalType(), setMiscReg(), updateDistributor(), and virtualDeactivateIRQ().

En

Bitfield<0> gem5::Gicv3CPUInterface::En

Definition at line 226 of file gic_v3_cpu_interface.hh.

Enable [1/2]

Bitfield< 3 > gem5::Gicv3CPUInterface::Enable

protected

Definition at line 114 of file gic_v3_cpu_interface.hh.

Referenced by readMiscReg().

Enable [2/2]

Bitfield<3> gem5::Gicv3CPUInterface::Enable

protected

Definition at line 137 of file gic_v3_cpu_interface.hh.

EnableGrp1NS

Bitfield<0> gem5::Gicv3CPUInterface::EnableGrp1NS

protected

Definition at line 125 of file gic_v3_cpu_interface.hh.

EnableGrp1S

Bitfield<1> gem5::Gicv3CPUInterface::EnableGrp1S

protected

Definition at line 124 of file gic_v3_cpu_interface.hh.

EOI [1/3]

Bitfield<41> gem5::Gicv3CPUInterface::EOI

Definition at line 238 of file gic_v3_cpu_interface.hh.

EOI [2/3]

Bitfield<9> gem5::Gicv3CPUInterface::EOI

Definition at line 255 of file gic_v3_cpu_interface.hh.

EOI [3/3]

Bitfield<0> gem5::Gicv3CPUInterface::EOI

Definition at line 267 of file gic_v3_cpu_interface.hh.

EOIcount

Bitfield<31, 27> gem5::Gicv3CPUInterface::EOIcount

Definition at line 211 of file gic_v3_cpu_interface.hh.

EOImode

Bitfield< 1 > gem5::Gicv3CPUInterface::EOImode

protected

Definition at line 88 of file gic_v3_cpu_interface.hh.

EOImode_EL1NS

Bitfield<4> gem5::Gicv3CPUInterface::EOImode_EL1NS

protected

Definition at line 105 of file gic_v3_cpu_interface.hh.

EOImode_EL1S

Bitfield<3> gem5::Gicv3CPUInterface::EOImode_EL1S

protected

Definition at line 106 of file gic_v3_cpu_interface.hh.

EOImode_EL3

Bitfield<2> gem5::Gicv3CPUInterface::EOImode_EL3

protected

Definition at line 107 of file gic_v3_cpu_interface.hh.

ExtRange

Bitfield< 19 > gem5::Gicv3CPUInterface::ExtRange

protected

Definition at line 78 of file gic_v3_cpu_interface.hh.

gic

Gicv3* gem5::Gicv3CPUInterface::gic

protected

Definition at line 68 of file gic_v3_cpu_interface.hh.

Referenced by assertWakeRequest(), clearPendingInterrupts(), copy(), deassertWakeRequest(), generateSGI(), haveEL(), havePendingInterrupts(), init(), setThreadContext(), update(), and virtualUpdate().

GIC_MIN_BPR

const uint8_t gem5::Gicv3CPUInterface::GIC_MIN_BPR = 2

staticprotected

Definition at line 154 of file gic_v3_cpu_interface.hh.

Referenced by bpr1(), highestActivePriority(), and setMiscReg().

GIC_MIN_BPR_NS

const uint8_t gem5::Gicv3CPUInterface::GIC_MIN_BPR_NS = GIC_MIN_BPR + 1

staticprotected

Definition at line 156 of file gic_v3_cpu_interface.hh.

Referenced by bpr1(), and setMiscReg().

GIC_MIN_VBPR

const uint8_t gem5::Gicv3CPUInterface::GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS

staticprotected

Definition at line 162 of file gic_v3_cpu_interface.hh.

Referenced by virtualDropPriority(), and virtualHighestActivePriority().

GICC_APR

const AddrRange gem5::Gicv3CPUInterface::GICC_APR

staticprotected

Definition at line 191 of file gic_v3_cpu_interface.hh.

GICC_NSAPR

const AddrRange gem5::Gicv3CPUInterface::GICC_NSAPR

staticprotected

Definition at line 192 of file gic_v3_cpu_interface.hh.

GICH_APR

const AddrRange gem5::Gicv3CPUInterface::GICH_APR

staticprotected

Definition at line 205 of file gic_v3_cpu_interface.hh.

GICH_LR

const AddrRange gem5::Gicv3CPUInterface::GICH_LR

staticprotected

Definition at line 206 of file gic_v3_cpu_interface.hh.

Group [1/2]

Bitfield<60> gem5::Gicv3CPUInterface::Group

Definition at line 233 of file gic_v3_cpu_interface.hh.

Group [2/2]

Bitfield<28> gem5::Gicv3CPUInterface::Group

Definition at line 250 of file gic_v3_cpu_interface.hh.

hppi

hppi_t gem5::Gicv3CPUInterface::hppi

protected

Definition at line 171 of file gic_v3_cpu_interface.hh.

Referenced by clearPendingInterrupts(), getHPPIR0(), getHPPIR1(), Gicv3CPUInterface(), havePendingInterrupts(), hppiCanPreempt(), readMiscReg(), resetHppi(), serialize(), unserialize(), update(), gem5::Gicv3Distributor::update(), and gem5::Gicv3Redistributor::update().

HW [1/2]

EndBitUnion (ICH_HCR_EL2) protected Bitfield<61> gem5::Gicv3CPUInterface::HW

Definition at line 232 of file gic_v3_cpu_interface.hh.

HW [2/2]

Bitfield<29> gem5::Gicv3CPUInterface::HW

Definition at line 249 of file gic_v3_cpu_interface.hh.

ICH_LR_EL2_STATE_ACTIVE

const uint64_t gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE = 2

static

Definition at line 244 of file gic_v3_cpu_interface.hh.

Referenced by virtualActivateIRQ(), and virtualFindActive().

ICH_LR_EL2_STATE_ACTIVE_PENDING

const uint64_t gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE_PENDING = 3

static

Definition at line 245 of file gic_v3_cpu_interface.hh.

Referenced by virtualFindActive().

ICH_LR_EL2_STATE_PENDING

const uint64_t gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_PENDING = 1

static

Definition at line 243 of file gic_v3_cpu_interface.hh.

Referenced by maintenanceInterruptStatus().

IDbits [1/2]

Bitfield< 13, 11 > gem5::Gicv3CPUInterface::IDbits

protected

Definition at line 83 of file gic_v3_cpu_interface.hh.

IDbits [2/2]

Bitfield<25, 23> gem5::Gicv3CPUInterface::IDbits

Definition at line 289 of file gic_v3_cpu_interface.hh.

ListRegs

Bitfield<4, 0> gem5::Gicv3CPUInterface::ListRegs

Definition at line 295 of file gic_v3_cpu_interface.hh.

LRENP

Bitfield<2> gem5::Gicv3CPUInterface::LRENP

Definition at line 265 of file gic_v3_cpu_interface.hh.

LRENPIE

Bitfield<2> gem5::Gicv3CPUInterface::LRENPIE

Definition at line 224 of file gic_v3_cpu_interface.hh.

maintenanceInterrupt

ArmInterruptPin* gem5::Gicv3CPUInterface::maintenanceInterrupt

protected

Definition at line 73 of file gic_v3_cpu_interface.hh.

Referenced by setThreadContext(), and virtualUpdate().

nDS

Bitfield<17> gem5::Gicv3CPUInterface::nDS

protected

Definition at line 96 of file gic_v3_cpu_interface.hh.

NP

Bitfield<3> gem5::Gicv3CPUInterface::NP

Definition at line 264 of file gic_v3_cpu_interface.hh.

NPIE

Bitfield<3> gem5::Gicv3CPUInterface::NPIE

Definition at line 223 of file gic_v3_cpu_interface.hh.

pINTID [1/2]

Bitfield<44, 32> gem5::Gicv3CPUInterface::pINTID

Definition at line 237 of file gic_v3_cpu_interface.hh.

pINTID [2/2]

Bitfield<12, 0> gem5::Gicv3CPUInterface::pINTID

Definition at line 254 of file gic_v3_cpu_interface.hh.

PMHE

Bitfield< 6 > gem5::Gicv3CPUInterface::PMHE

protected

Definition at line 86 of file gic_v3_cpu_interface.hh.

PREbits

Bitfield<28, 26> gem5::Gicv3CPUInterface::PREbits

Definition at line 288 of file gic_v3_cpu_interface.hh.

PRIbits [1/2]

Bitfield< 10, 8 > gem5::Gicv3CPUInterface::PRIbits

protected

Definition at line 84 of file gic_v3_cpu_interface.hh.

PRIbits [2/2]

Bitfield<31, 29> gem5::Gicv3CPUInterface::PRIbits

Definition at line 287 of file gic_v3_cpu_interface.hh.

Priority [1/2]

Bitfield<55, 48> gem5::Gicv3CPUInterface::Priority

Definition at line 235 of file gic_v3_cpu_interface.hh.

Priority [2/2]

Bitfield<23, 16> gem5::Gicv3CPUInterface::Priority

Definition at line 252 of file gic_v3_cpu_interface.hh.

redistributor

Gicv3Redistributor* gem5::Gicv3CPUInterface::redistributor

protected

Definition at line 69 of file gic_v3_cpu_interface.hh.

Referenced by copy(), deactivateIRQ(), generateSGI(), init(), setMiscReg(), setThreadContext(), virtualDeactivateIRQ(), and virtualUpdate().

res0

gem5::Gicv3CPUInterface::res0

protected

Definition at line 113 of file gic_v3_cpu_interface.hh.

res0_0 [1/8]

Bitfield<5, 2> gem5::Gicv3CPUInterface::res0_0

protected

Definition at line 87 of file gic_v3_cpu_interface.hh.

res0_0 [2/8]

Bitfield<7> gem5::Gicv3CPUInterface::res0_0

protected

Definition at line 102 of file gic_v3_cpu_interface.hh.

res0_0 [3/8]

Bitfield<9, 8> gem5::Gicv3CPUInterface::res0_0

Definition at line 218 of file gic_v3_cpu_interface.hh.

res0_0 [4/8]

Bitfield<47, 45> gem5::Gicv3CPUInterface::res0_0

Definition at line 236 of file gic_v3_cpu_interface.hh.

res0_0 [5/8]

Bitfield<15, 13> gem5::Gicv3CPUInterface::res0_0

Definition at line 253 of file gic_v3_cpu_interface.hh.

res0_0 [6/8]

Bitfield<8, 5> gem5::Gicv3CPUInterface::res0_0

Definition at line 277 of file gic_v3_cpu_interface.hh.

res0_0 [7/8]

Bitfield<18, 5> gem5::Gicv3CPUInterface::res0_0

Definition at line 294 of file gic_v3_cpu_interface.hh.

res0_0 [8/8]

Bitfield<7, 2> gem5::Gicv3CPUInterface::res0_0

Definition at line 306 of file gic_v3_cpu_interface.hh.

res0_1 [1/8]

Bitfield<7> gem5::Gicv3CPUInterface::res0_1

protected

Definition at line 85 of file gic_v3_cpu_interface.hh.

res0_1 [2/8]

Bitfield<16> gem5::Gicv3CPUInterface::res0_1

protected

Definition at line 97 of file gic_v3_cpu_interface.hh.

res0_1 [3/8]

Bitfield<26, 15> gem5::Gicv3CPUInterface::res0_1

Definition at line 212 of file gic_v3_cpu_interface.hh.

res0_1 [4/8]

Bitfield<59, 56> gem5::Gicv3CPUInterface::res0_1

Definition at line 234 of file gic_v3_cpu_interface.hh.

res0_1 [5/8]

Bitfield<27, 24> gem5::Gicv3CPUInterface::res0_1

Definition at line 251 of file gic_v3_cpu_interface.hh.

res0_1 [6/8]

Bitfield<17, 10> gem5::Gicv3CPUInterface::res0_1

Definition at line 275 of file gic_v3_cpu_interface.hh.

res0_1 [7/8]

gem5::Gicv3CPUInterface::res0_1

Definition at line 286 of file gic_v3_cpu_interface.hh.

res0_1 [8/8]

Bitfield<17, 16> gem5::Gicv3CPUInterface::res0_1

Definition at line 301 of file gic_v3_cpu_interface.hh.

res0_2 [1/2]

Bitfield<17, 16> gem5::Gicv3CPUInterface::res0_2

protected

Definition at line 80 of file gic_v3_cpu_interface.hh.

res0_2 [2/2]

gem5::Gicv3CPUInterface::res0_2

protected

Definition at line 93 of file gic_v3_cpu_interface.hh.

res0_3

gem5::Gicv3CPUInterface::res0_3

protected

Definition at line 77 of file gic_v3_cpu_interface.hh.

res1

Bitfield<20> gem5::Gicv3CPUInterface::res1

Definition at line 292 of file gic_v3_cpu_interface.hh.

RM

Bitfield<5> gem5::Gicv3CPUInterface::RM

protected

Definition at line 104 of file gic_v3_cpu_interface.hh.

RSS

Bitfield< 18 > gem5::Gicv3CPUInterface::RSS

protected

Definition at line 79 of file gic_v3_cpu_interface.hh.

SEIS [1/2]

Bitfield< 14 > gem5::Gicv3CPUInterface::SEIS

protected

Definition at line 82 of file gic_v3_cpu_interface.hh.

SEIS [2/2]

Bitfield<22> gem5::Gicv3CPUInterface::SEIS

Definition at line 290 of file gic_v3_cpu_interface.hh.

SRE

Bitfield< 0 > gem5::Gicv3CPUInterface::SRE

protected

Definition at line 132 of file gic_v3_cpu_interface.hh.

State

gem5::Gicv3CPUInterface::State

Definition at line 248 of file gic_v3_cpu_interface.hh.

TALL0

Bitfield<11> gem5::Gicv3CPUInterface::TALL0

Definition at line 216 of file gic_v3_cpu_interface.hh.

TALL1

Bitfield<12> gem5::Gicv3CPUInterface::TALL1

Definition at line 215 of file gic_v3_cpu_interface.hh.

TC

Bitfield<10> gem5::Gicv3CPUInterface::TC

Definition at line 217 of file gic_v3_cpu_interface.hh.

tc

ThreadContext* gem5::Gicv3CPUInterface::tc

protected

Definition at line 72 of file gic_v3_cpu_interface.hh.

Referenced by assertWakeRequest(), currEL(), deassertWakeRequest(), getHCREL2FMO(), getHCREL2IMO(), Gicv3CPUInterface(), inSecureState(), isAA64(), isSecureBelowEL3(), readMiscReg(), setMiscReg(), and setThreadContext().

TDIR

Bitfield<14> gem5::Gicv3CPUInterface::TDIR

Definition at line 213 of file gic_v3_cpu_interface.hh.

TDS

Bitfield<19> gem5::Gicv3CPUInterface::TDS

Definition at line 293 of file gic_v3_cpu_interface.hh.

TSEI

Bitfield<13> gem5::Gicv3CPUInterface::TSEI

Definition at line 214 of file gic_v3_cpu_interface.hh.

U

Bitfield<1> gem5::Gicv3CPUInterface::U

Definition at line 266 of file gic_v3_cpu_interface.hh.

Referenced by groupPriorityMask(), setMiscReg(), and virtualGroupPriorityMask().

UIE

Bitfield<1> gem5::Gicv3CPUInterface::UIE

Definition at line 225 of file gic_v3_cpu_interface.hh.

VAckCtl

Bitfield<2> gem5::Gicv3CPUInterface::VAckCtl

Definition at line 280 of file gic_v3_cpu_interface.hh.

VBPR0

Bitfield<23, 21> gem5::Gicv3CPUInterface::VBPR0

Definition at line 273 of file gic_v3_cpu_interface.hh.

VBPR1

Bitfield<20, 18> gem5::Gicv3CPUInterface::VBPR1

Definition at line 274 of file gic_v3_cpu_interface.hh.

VCBPR

Bitfield<4> gem5::Gicv3CPUInterface::VCBPR

Definition at line 278 of file gic_v3_cpu_interface.hh.

VENG0

Bitfield<0> gem5::Gicv3CPUInterface::VENG0

Definition at line 282 of file gic_v3_cpu_interface.hh.

VENG1

Bitfield<1> gem5::Gicv3CPUInterface::VENG1

Definition at line 281 of file gic_v3_cpu_interface.hh.

VEOIM

Bitfield<9> gem5::Gicv3CPUInterface::VEOIM

Definition at line 276 of file gic_v3_cpu_interface.hh.

VFIQEn

Bitfield<3> gem5::Gicv3CPUInterface::VFIQEn

Definition at line 279 of file gic_v3_cpu_interface.hh.

VGrp0D

Bitfield<5> gem5::Gicv3CPUInterface::VGrp0D

Definition at line 262 of file gic_v3_cpu_interface.hh.

VGrp0DIE

Bitfield<5> gem5::Gicv3CPUInterface::VGrp0DIE

Definition at line 221 of file gic_v3_cpu_interface.hh.

VGrp0E

Bitfield<4> gem5::Gicv3CPUInterface::VGrp0E

Definition at line 263 of file gic_v3_cpu_interface.hh.

VGrp0EIE

Bitfield<4> gem5::Gicv3CPUInterface::VGrp0EIE

Definition at line 222 of file gic_v3_cpu_interface.hh.

VGrp1D

Bitfield<7> gem5::Gicv3CPUInterface::VGrp1D

Definition at line 260 of file gic_v3_cpu_interface.hh.

VGrp1DIE

Bitfield<7> gem5::Gicv3CPUInterface::VGrp1DIE

Definition at line 219 of file gic_v3_cpu_interface.hh.

VGrp1E

Bitfield<6> gem5::Gicv3CPUInterface::VGrp1E

Definition at line 261 of file gic_v3_cpu_interface.hh.

VGrp1EIE

Bitfield<6> gem5::Gicv3CPUInterface::VGrp1EIE

Definition at line 220 of file gic_v3_cpu_interface.hh.

vINTID

Bitfield<31, 0> gem5::Gicv3CPUInterface::vINTID

Definition at line 239 of file gic_v3_cpu_interface.hh.

VIRTUAL_NUM_LIST_REGS

const uint8_t gem5::Gicv3CPUInterface::VIRTUAL_NUM_LIST_REGS = 16

staticprotected

Definition at line 160 of file gic_v3_cpu_interface.hh.

Referenced by eoiMaintenanceInterruptStatus(), maintenanceInterruptStatus(), readMiscReg(), and virtualFindActive().

VIRTUAL_PREEMPTION_BITS

const uint8_t gem5::Gicv3CPUInterface::VIRTUAL_PREEMPTION_BITS = 5

staticprotected

Definition at line 159 of file gic_v3_cpu_interface.hh.

Referenced by readMiscReg(), setMiscReg(), virtualActivateIRQ(), and virtualDropPriority().

VIRTUAL_PRIORITY_BITS

const uint8_t gem5::Gicv3CPUInterface::VIRTUAL_PRIORITY_BITS = 5

staticprotected

Definition at line 158 of file gic_v3_cpu_interface.hh.

Referenced by readMiscReg(), and virtualHighestActivePriority().

VPMR

Bitfield<31, 24> gem5::Gicv3CPUInterface::VPMR

Definition at line 272 of file gic_v3_cpu_interface.hh.

---

The documentation for this class was generated from the following files:

• dev/arm/gic_v3_cpu_interface.hh
• dev/arm/gic_v3_cpu_interface.cc